JPS6218074B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to an interface conversion device that enables an interface between devices having different memory address bit widths and data widths.

[Prior art]

In a data processing device that transfers data to memory, if the address width of the data processing device is insufficient to specify the entire address space of the memory,
It is necessary to use some means to expand the memory address sent from the data processing device.

Conventionally, the mapping register method has been commonly used as this expansion method. This method assumes that the data widths are the same. However, not only the address width but also the data width during memory transfer,
In systems where the data width sent by the data processing device is different, the data also needs to be converted. Here, when the address widths are different and the data widths are different, it means that the number of address bits transferred in one transfer is different, and the number of data bits transferred in one transfer is different.

Conventionally, data processing devices and memories either have different address widths or different data widths. When the address widths are different, it has been common practice to convert the address widths using the above-mentioned mapping register. When the data widths are different, generally the data width sent from the data processing device is small and the data width when transferred to the memory is large, so a buffer is provided in the middle of the data transfer path between these two. The method used was to transfer data from the buffer to memory when the data width reached a size that could be transferred to memory. but,
Conventionally, there has been no means for efficiently transferring data between memories when there are a plurality of data processing devices with different address widths and different data widths.

[Purpose of the invention]

An object of the present invention is to solve the problem of memory address width when the memory address width and data width are different between a memory and an input/output device in a data processing system.
The present invention provides an interface conversion device for converting data width and data width.

[Summary of the invention]

In the present invention, a data buffering method is added to the mapping register method used for memory address expansion. That is, the data buffer number or data buffer address is also stored in the mapping register, and when data is transferred from the input/output device to the memory, the memory mapping function, which is the original function of the mapping register, is used. For data buffering that is required due to address extension and different data widths, the buffer number is also read from the mapping register at the same time, and the data is placed at the buffer number determined for each input/output device. Store.
As a result, address conversion and data buffering operations of a plurality of input/output devices are performed in a time-sharing manner.

[Embodiments of the invention]

Examples of the present invention will be described.

FIG. 1 shows an overall configuration diagram of a data processing system to which the present invention is applied. This data processing system includes a main memory (M) 101, a memory control unit (MCU) 102, a data bus (BUS) 103, a service processor (SVP) 104, a job processor (JOBP) 105, an input/output processor (IOP) 106, File control processor (FCP) 107, interface processor (IFP) 108, external memory (FILE) 110, bus 111, various input/output devices 131, 132, 13
3,134, buffer 120, various input/output devices 1
It consists of 21, 122, 123, and 124.

The memory 101 has address and data width.
Has 32 bits. BUS 103 and each processor 104 to 108 similarly have a 32-bit address signal line and a 32-bit data signal line.
3, data is transferred to and from the memory 101.
These data transfers are controlled by the MCU 102.

The SVP104 performs initialization and start-up processing of the entire system and RAS (Reliability,
It collects various error information and monitors the status of other processors for the purpose of Availability and Serviceability.

JOP 105 is a processor that executes instructions. The IOP 106 controls general input/output devices 131 to 134 other than external storage devices using a loop bus 111, and connects these input/output devices and the memory 10.
Controls data transfer between 1 and 1. FCP107 is
A processor that controls FILE110,
110 and the memory 101 at high speed.

The IFP 108 is an input/output device 12 having an address width and a data width different from those on the bus 103.
1 to 124.

The data processing system configured as described above is characterized in that a plurality of processors whose functions are distributed are connected to the bus 103. This can also be called a functionally distributed multiprocessor.

In this system, the IFP has the address width and
Buses 120 each having a data width of 20 bits and 16 bits were connected. It is assumed that up to 16 input/output devices, each having an address width of 20 bits and a data width of 16 bits, can be connected to this bus. In this example, four input/output devices 121
~124 were connected.

These input/output devices 121 to 124 are memory 1
When transferring data with 01, follow the procedure 2 described below.
Two operations are required.

(1) Since the address space of the memory 101 has a capacity indicated by 32 bits, the input/output devices 121 to 1
It is necessary to expand the 20-bit address sent from 24 to 32 bits.

(2) Similarly, data must be 32 bits wide to be transferred to and from the memory 101, but the input/output devices 121-124 send or receive 16 bits. Therefore,
Connect two 16-bit data somewhere (so-called packing) to create 32-bit data, and send it to the memory 101 or store it in the memory 101.
The 32-bit data from the host must be converted into 16-bit data and received.

Therefore, in this embodiment, the above-mentioned
It has the functions (1) and (2). Note that there are two types of transfer via the IFP 108: transfer from the input/output devices 121 to 124 to the memory 101, and transfer from the memory 101 to the input/output devices 121 to 124. Both are the same in that they perform address conversion and data conversion, and their functions are opposite to each other. In the following, the explanation will be limited to data transfer from the input/output device side to the memory 101.

FIG. 2 shows a block diagram of a portion of the IFP 108 that achieves address mapping and data buffering functions. The mapping register 201 is
Inside it, the input/output device control information 210 and the upper 16 of the 32-bit address sent to the memory 101 are stored.
Among the bit information 211, the addresses of the data buffer memory 202 for buffering 16-bit data, the first address 212 of the buffer address used by one input/output device and the buffer address 213 used in the current transfer. Information is written under the control of IFP 108 when the input/output device is activated. Regarding this writing, since it is not the essence of the present invention, it will be omitted below. Note that starting the input/output device mentioned above means that after the JOP 105 issues a start command to the IFP 108 using the bus 103 in FIG. This refers to giving commands to the input/output devices 121 to 124 by input/output activation to start operations. Therefore, the IFP 108 has a processor in addition to the components shown in FIG. 2, and this processor performs the original function of the IFP.

Address register 203 is a register that latches an address (20 bits) from a 16-bit input/output device, and data register 204 is a register that latches data (16 bits) from a 16-bit input/output device.

The address register 205 contains the address after address conversion.
This is a register that temporarily latches a 32-bit address, and the data register 206 is a register that temporarily latches a 32-bit address.
This register temporarily latches 32-bit data. A switch 207 switches the writing destination of the contents of the data register 204 to the buffer memory 202.

The buffer memory 202 is a memory in which the data length in one address is 32 bits long, and the total number of addresses requires at least 16. The reason is that the minimum condition is that each of the 16 input/output devices correspond to one address. In general
16 or more. In particular, when the bus is busy or when the device is a high-speed input/output control device, the capacity of the buffer memory 202 needs to be even larger.

Now, the address register 203 has a 20-bit configuration, and the upper 4 bits indicate the address of the mapping register 201. According to the upper 4 bits of the address, the contents of the corresponding address in the mapping register 201 are read out, and the information on the upper 16 bits of the memory address therein and the contents of the lower 16 bits of the register 203, which is the address from the input/output device, are read out. are concatenated to generate a send address to memory 101 and latched into register 205. It is then sent to memory 101 via bus 103.

The 16-bit data from the input/output device is latched into the register 204 and then transferred to the data buffer register 20 under the switching of the switch 207.
The data is divided into the upper 16 bits and lower 16 bits of 2 and stored. Thus, the data is packed into 32-bit data and then stored in register 2.
06 and is sent to the memory 10 via the bus 103.
Sent to 1. Since the data in the buffer memory 202 is no longer needed after being sent, it may be reset at the same time as sending, or it may be forcibly reset after being sent. The address of the data buffer memory 202 is specified by the address 213 of the mapping register 201.

The buffer start address 212 in the mapping register 201 is an address indicating the beginning of the area of the buffer memory 202 allocated to each input/output device connected under the IFP 108. By calculating the difference between this value and the current buffer address 213, the amount of data stored in the buffer can be determined. This current buffer address 213 is incremented by one by hardware (not shown) within IFP 108 every time two pieces of data are stored in the buffer memory.

The mapping register 201 has a configuration of 16 registers, but this is because the maximum number of input/output devices connected to the IFP 108 is 16. It can vary in many ways.

Figure 3 shows IFP10, which is a more specific version of Figure 2.
FIG. 8 is an example diagram of FIG. IFP internal control circuit 221
generates a switching signal 225 that switches the input to the address register 224. When initializing or updating data in the mapping register 201 at startup, etc., the address register 224
selects the signal line 223 side and takes in the address via the signal line 223. The data to be stored at this time is supplied from the IFP internal control circuit 221 through the signal line 222 and stored at the address specified by the register 224.

When reading the contents of the mapping register 201, the switching signal 225 transfers the upper 4 bits of the address register 203 to the register 22 via the signal line 226.
4. According to the address specified by this register 224, data at the corresponding address is read out.

The selector 207A switches whether to store the contents of the register 204 in the upper 16 bits or the lower 16 bits of the buffer memory 202, depending on whether the least significant bit LSB 229 of the address register 203 is "1" or "0". conduct. For example, LSB22
When 9 is "0", the upper 16 bits are selected as the distribution destination, and when it is "1", the lower 16 bits are selected as the distribution destination. The storage address of the buffer memory 202 at this time is specified by the mapping register 201 via the signal line 230. buffer memory 2
When 32 bits of data are stored in 02, this 32
The bits of data are latched into data register 206 and sent to memory.

According to the above embodiment, when data is transferred from multiple input/output devices to memory, the memory side has an address width and data width of 32 bits, and the input/output device side has an address width of 20 bits and a data width of 16 bits. With this, it was possible to extend an address from a 20-bit address width to a 32-bit address width and to perform packing from 16-bit data to 32-bit data. In particular, by having the IFP perform this address expansion and data packing, it has become possible to perform time-division transfer between multiple input/output devices and memory. The time division referred to here means that the input/output devices 121 to
124 are operating simultaneously at a certain moment, and each input/output device sequentially stores data in the buffer register within the IFP using the bus under the IFP. Furthermore, in this embodiment, the data transfer from the input/output device to the memory 103 is a DMA transfer, and by providing one mapping register in the middle of the data transfer path for both, ○I. Address expansion, buffering management of data coming from multiple input/output devices, and data packing can be performed using hardware. Furthermore, this enables time-sharing simultaneous operation of multiple input/output devices, allowing various data in the system to be Collection becomes faster, which has the effect of speeding up system control. Note that the unit of writing data to the memory 101 is 32
Being bits has the advantage that software does not have to take special care when using the data.

The various bit lengths handled in this example are just examples;
This does not mean that other bit lengths are not allowed. Furthermore, the data processing system is not limited to that shown in FIG.

Further, although data is transferred between the memory and the input/output device, the present invention is also applicable to data transfer between the memory and a data processing device, a communication control device, etc. other than the input/output device. Furthermore, the memory may be other than the main memory, and in short, the present invention can be extended between devices having different transfer bit lengths.

〔Effect of the invention〕

According to the present invention, data buffer address information can be stored in a register for address conversion, and address conversion and buffer control can be performed simultaneously. This made data transfer more efficient.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a data processing system to which the present invention is applied, FIG. 2 is a diagram of an embodiment of the IFP 108, and FIG. 3 is a diagram of a more specific embodiment of the IFP 108. 101... Main memory (M), 102... Memory control unit (MCU), 103... Bus (BUS), 104... Service processor (SVP), 105... Job processor (JOP),
106...Input/output processor (IOP), 107...
...File control processor (FCP), 108...
Interface processor (IFP), 121~
124...I/O device.

Claims (1)

[Scope of Claims] 1. A first memory for buffering data from one of the devices, and a first memory for buffering address information and data for converting addresses from the one device. A second memory that stores two pieces of information, the address information of the first memory, and can read them simultaneously; and the second memory is accessed by the address information from one of the devices, and the address information corresponding to the address is accessed. means for simultaneously reading address information for address conversion and a buffer address of the first memory;
means for creating an address for the other device from the read address information for address conversion and a part of the address information from the one device, and according to the read buffer address of the first memory. means for creating data for the other device based on the data from the one device and storing it in the first memory; and the address created and the created data stored in the first memory. an interface conversion device comprising: means for transferring the information to the other device; 2. The interface conversion device according to claim 1, wherein the one device and the other device are memory and input/output devices.