JPS62176382A - Receiving circuit for teletext - Google Patents

Abstract

PURPOSE:To increase the time capable of fetching of a CPU by storing data outputted from an error correction part in plural buffer memories by changing over in time division for a 1-vertical blanking period. CONSTITUTION:The serial/parallel conversion and error correction part 3 outputs the data after the error is corrected, a designation address on the buffer RAM 4I, 4II, an error correction processing completion signal (2) and a bus control signal (5). The error correction processing completion signal (2) forms a select signal (3) of a multiplexer 4i and a select signal (4) of a multiplexer 4ii through an inversion element 11 through an FF10 and the period for receiving the signal from the error correction part 3 and the period for receiving the signal from the CPU5 are shifted in time alternately with respect to the buffer RAMs 4I, 4II respectively. The buffer RAMs 4I, 4II are mutually shifted in timing by the 1-vertical blanking period and respectively operate by making 2-vertical blanking periods a cycle and the time capable of fetching of the CPU 5 is remarkably increased.

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to a teletext receiving circuit, and more particularly, the present invention relates to a teletext receiving circuit, and more particularly, the present invention relates to a teletext receiving circuit, and more particularly, to a teletext receiving circuit, the present invention relates to a teletext receiving circuit. The present invention relates to a teletext receiving circuit configured to be able to display teletext content on a display unit by extracting a broadcast signal and subjecting it to serial-to-parallel conversion processing, error correction processing, decoding processing, display processing, etc.

Technical Background and Prior Art In a teletext system using a coded transmission method that has only recently been put into practical use, a teletext signal is transmitted using the vertical blanking period of a television video signal. The data superimposed in the l-horizontal scanning period is time-division multiplexed in the form of digital data in the form of a data packet whose length is the length. In other words, the signal related to one teletext program is superimposed on the vertical blanking period almost continuously, one packet at a time during the 1-vertical blanking period. Therefore, the teletext signal superimposed in the 1-vertical blanking interval must be completely captured and processed before the teletext signal superimposed in the next vertical blanking interval arrives. .

On the other hand, as shown in Figure 5, in the future 1-vertical return VA
/l! 4. In the last period, up to 12 programs (IO
Up to 12 packets (H~211) can be superimposed.

By the way, if a conventional teletext receiving circuit is not equipped with a data memory capable of storing data of multiple teletext programs, it is only necessary to import the program selected by the receiver. It was only necessary to capture one data packet during the blanking period, and there was plenty of time, so there was no problem. When trying to store and accumulate the latest data, especially when a large number of data packets are superimposed in the 1-vertical blanking period, the process of capturing the large number of data packets is performed in the next vertical blanking period. It must be completed by the time the data packet superimposed on C arrives.
The PU import processing time becomes a major problem.

That is, data is stored in one buffer RA in the order in which it is transmitted.
In a conventional teletext receiving circuit using a simple means of sequentially capturing data using M, as shown in FIG.
During the V period, primary capture processing of superimposed data, data transfer to buffer RAM after error correction processing, error checking,
While checking the reservation status and selected programs,
CPU processing must be performed to store the data in the buffer RAM after error correction processing in the data memory.

Further, if the error correction unit performs error correction processing multiple times, the correction ability will increase, but if the error correction processing is performed multiple times, the error correction processing time will increase. In addition, the data packet superimposition H
The larger the number, the longer the error correction process will take. Therefore, the worse the reception condition is, and the greater the number of superimposed data packets, the more time is required for error correction processing, and the longer the CPU can process the data, t.
becomes shorter. In addition, the CPU's acquisition processing time also increases as the number of superimposed data packets H increases, so there is a limit to the number of superimposed data packets that can be captured simultaneously.

<Object of the Invention> The present invention has been made in view of the above-mentioned circumstances, and its purpose is to record and store data of a plurality of teletext programs. In addition to providing a large capacity data memory that can store data,
The object of the present invention is to provide a teletext receiving circuit which stores the latest data in the data memory and does not require a CPU's acquisition processing time as in the past.

<Configuration of the Invention> In order to achieve the above object, the teletext receiving circuit according to the present invention has the basic configuration as described at the beginning, and is capable of storing data of a plurality of teletext programs. In addition to providing a large-capacity data memory, in order to store the latest data in the data memory, the data output from the error correction unit is stored in multiple buffer memories by time-sharing switching in units of 1-vertical blanking period. The feature is that the CPU is configured to be able to increase the available processing time by doing so.

<Example> Hereinafter, a specific example of the present invention will be described based on the drawings (FIGS. 1 to 4 [iJ)].

FIG. 1 is a schematic block circuit diagram of the main parts of the teletext receiving circuit according to the present embodiment. In the figure, 1 is an antenna, 2 is a teletext signal extraction section, 3 is a serial/parallel conversion and error correction section, 4 is a buffer memory equipped with a plurality of buffer RAMs, 5 is a CPU, 6 is a data memory with a large capacity sufficient to store data of a plurality of teletext programs, 7 is a decoding and display processing section, and 8 is a CRT or Indicates a display such as a liquid crystal display, where antenna 1 receives a multiplexed television signal sent from a broadcasting station, and characters are superimposed from the multiplexed television signal during the vertical blanking period of the video signal. The teletext signal extractor 2 extracts the broadcast signal, and the extracted data undergoes serial-to-parallel conversion and error correction in units of packet processors 3, and then the data is transferred to the buffer memory 4. C
The PU 5 sequentially processes the data in the buffer memory 4 after checking for errors, and in the case of a system that allows program reservations, stores and accumulates the data in the data memory 6 for each program while checking the program reservation status. , the accumulated data is transferred to the decoding and display processing unit 7 in accordance with the receiver's program selection by keystrokes from an operation panel (not shown), where it is subjected to decoding and display processing and converted into pixel data. It is configured to convert the image into a file and display it on the display 8.

As described above, in the teletext receiving circuit according to the present invention, a large capacity data memory 6 is provided so as to store and accumulate a plurality of teletext programs, and a plurality of buffers RA
By providing the buffer memory 4 with M
This is an attempt to improve the processing time for U5 to process data, but for the sake of simplicity, the detailed block circuit diagram of the main part shown in FIG. 2 is for the case where two buffer RAMs are provided as the backup memory 4. , the buffer R in FIG.
The operation will be explained with reference to the AM switching timing chart and the operation diagram of FIG. Note that FIG. 2 is conceptual, and positive logic and negative logic are not taken into consideration.

That is, as shown in FIGS. 2 and 3, the serial-to-parallel converter and error correction section 3 receives the ``--synchronization signal ``.

H- Synchronization signal, serial data, operation clock, etc. are input, and after performing serial-to-parallel conversion processing and error correction processing, the error-corrected data and buffer RAM 4T, which will be described later, are
, 411, and outputs an error correction processing completion signal ■ which indicates that the error correction processing of all data superimposed in the 1-vertical blanking period has been completed, and the buffer RAM 41, 4■ A bus control signal (■) for switching the access destination to the serial/parallel conversion and error correction section 3 and the CPU 5 is output. 2 barraa R
AM41.411 has an address bus from CPU5,
Multiplexers 4i and 4ii are added for temporally switching and connecting the data bus, the address bus from the serial/parallel converter and error correction section 3, and the data bus. The CPU 5 receives the error correction processing end signal ■
Accept the message and start the import process. The address bus and data bus from the CPU 5 are sent to the respective buffer RAMs 41゜4■ through the two multiplexers 4i and 4ii.
It also controls the chip select terminals of the respective buffer RAMs 41 and 4 through the address decoder 9.

The V-synchronization signal (2) and the error correction processing completion signal (2) are signals with waveforms as shown in (a) and (b) in FIG. 3, respectively. The error correction processing end signal (■) is a signal for causing the CPU 5 to start the acquisition process, and the select signal (■) of the multiplexer 41, which changes at the fall of the error correction processing end signal (■), is sent via the flip-flop 10. (C) in FIG. 3 is generated, and the select signal ■ of the multiplexer 41 is inverted by the inverting element 11 to create the select signal ■ of the multiplexer 411 ((2) in FIG. 3), and the two buffers R
For each AM41.41, the period in which the signal from the serial/parallel converter and error correction section 3 is received and the period in which the signal from the CPU 5 is received are alternately shifted in time. Therefore, the two buffer RAMs 41 and 411 operate at a cycle of 2 vertical blanking periods, with the timings shifted from each other by 1 vertical blanking period.

On the other hand, the serial/parallel converter and error correction section 3 outputs the bus control signal ■ ((e) in FIG. 3) to each of the two buffer RAMs 41 and 411. With the select signals ■ and ■, the signals are sent from the serial-to-parallel conversion and error correction unit 3 to both buffer RAMs 41 .
4[1] respectively controls the timing of control signals related to reading and writing of the buffer RAM. Also,
The cp
Control signals related to reading and writing of the buffer RAMs 41 and 411 output from the us are switched.

As described above, the host accessing each buffer RAM 4 L4■ receives the select signal ■ of the buffer RAM 41 shown in (g) in FIG. This increases the time that the CPU 5 can spend on import processing.

In other words, as shown in FIG. 4, C
The capture processing time T of the PU 5 is extended until the end of the error correction process for the next field, and is significantly longer than the CPU capture processing time t in the conventional case shown in FIG. 6 described above. increases to

In FIG. 3, only the timing of the capture processing operation of the CPU 5 is shown, but the CPU 5 performs decoding processing and display processing of the selected program during the time remaining after the capture processing is completed. Furthermore, in order to speed up the processing, it is also possible to provide a plurality of CPUs, one for the capture process and the other for displaying the decoding process 1.

In addition, in the above embodiment, for the sake of simplifying the explanation,
Two buffer RAMs 41, 4 as buffer memory 4
11, but with more buffers RA
It is clear that by providing M, the CPU's available processing time T can be further extended significantly.

<Effects of the Invention> As is clear from the above detailed description, the teletext receiving circuit according to the present invention includes a large-capacity data memory capable of storing data of a plurality of teletext programs, and In order to store the latest data in the data memory, the data output from the error correction unit is switched and stored in multiple buffer memories in a time-sharing manner, thereby increasing the available processing time for the CPU. Because of this, it is possible to store and accumulate multiple teletext programs, as well as to store the latest data in the data memory, as well as to store a large number of data packets superimposed within the 1-vertical blanking period. In some cases, instead of simply loading the data into one buffer memory in the order in which it is transmitted, as in the past, the data output from the error correction unit is stored in multiple buffer memories in one vertical return. By time-divisionally switching and storing data in units of line erasing periods, it is now possible to simultaneously capture and process multiple data packets within the extended CPU capture and processing time.
Even if a large number of data packets are superimposed and transmitted within the 1-vertical blanking period, C
This provides an excellent effect in that the PU capture processing time does not become a problem, and all data packets can be processed with sufficient margin.

[Brief explanation of drawings]

1 to 4 show a specific embodiment of the teletext receiving circuit according to the present invention, FIG. 1 is a schematic block circuit diagram of the main part, and FIG. 2 is a detailed block circuit diagram of the main part. FIG. 3 is a timing chart of the signals of each part, and FIG. 4 is an explanatory diagram of the operation. Further, FIGS. 5 and 6 are for explaining the technical background of the present invention and problems of the prior art,
FIG. 5 is an explanatory diagram of the state of a multiplexed television video signal, and FIG. 6 is an explanatory diagram of the operation in a conventional teletext receiving circuit. 2... Teletext signal extraction section, 3...
...Serial to parallel conversion and error correction unit, 4 (4I
, 411)...Buffer memory (RAM), 5
・・・・・・・・・CPU. 6......Large capacity data memory, 7...
...Decoding and display processing section.

Claims (1)

[Claims] A teletext signal that is time-division multiplexed during the vertical blanking period of the video signal is extracted from the received multiplexed television signal, and serial-to-parallel conversion processing, error correction processing, decoding processing, In a teletext receiving circuit configured to be able to display teletext content on a display section by performing display processing, etc., a large capacity data memory capable of storing data of a plurality of teletext programs is provided, In order to store the latest data in the data memory, the data output from the error correction unit is stored in multiple buffer memories in a time-division manner in units of 1-vertical blanking period, which allows the CPU to process the data. A teletext receiving circuit characterized in that it is configured to increase the available time.