JPS62171228A - Digital pll circuit - Google Patents

Abstract

PURPOSE:To simplify the circuit constitution and to easily decide the lock range width by providing an x/y frequency-divider outputting a frequency pulse being N times of a lower limit frequency of the lock range based on an output signal from an oscillator having a crystal resonator. CONSTITUTION:A phase comparator 1 compares the phase difference between an input signal a1 and an output signal d1 from the frequency divider 5 and outputs a signal shown in figure b1 to a frequency changeover circuit 2. The frequency changeover circuit 2, according to the said signal, changes over an output from the oscillator 3 and the output from the x/y frequency divider 6. Then optional integers x/y are decided so that the output of the x/y frequency divider 6 is fXx/y at the lower limit of the lock range, where (f) is the oscillation frequency of the oscillator 3. Then the output of the x/y frequency divider 6 is fXx/y and the lock range of a digital PLL circuit is in the range from f/N to fXx/y/N, where N is the frequency division ratio of the frequency divider 5 and the center frequency fo of the loop is a median between the values f/N and fXx/y/N.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention provides a digital PLL (Phase Locked L) which obtains an output signal phase-locked to an input signal by alternately switching the outputs of a plurality of fixed frequency oscillators.
The present invention relates to a digital PLL circuit in which the oscillator described above can be configured with one oscillation element.

[Prior Art] A conventional digital PLL circuit of this type is shown in FIG. In the figure, (1) is a phase comparator that compares the phases of two input signals using, for example, a general EX-○R circuit (exclusive OR circuit) and outputs the phase difference; (2) ) is a frequency switching circuit that alternately switches the oscillation frequency signal, (3) is an oscillator that generates pulses at a frequency that is N times the lock range upper limit frequency (N is any integer), and (4) is the lock range lower limit. frequency N
The oscillator (5) generates pulses at twice the frequency, and the frequency divider (5) divides the output of the frequency switching circuit (2) by N.

FIG. 5 is a time chart showing each input/output signal of the phase comparator (1) shown in FIG. 4, and FIG. 3 is a time chart showing the switching state of the frequency switching circuit (2).

The conventional digital PLL circuit is configured as described above, and its operation will be explained below. First, the phase comparator (1) compares the phase difference between the input signal (a) and the signal (d) from the frequency divider (5), and obtains a signal output (b) as shown in FIG. This output is input to the frequency switching circuit (2), which outputs the output from the oscillator (3) [Fig. 6(e)] and the oscillator (4).
The output from [Fig. 6(f)] is exchanged with the output from Fig. 6(c).
) Outputs a pulse with the waveform shown in The frequency divider (5) smoothes the sudden change in the signal outputted during switching in the frequency switching circuit (2) since the signal is a discontinuous signal. The output of the frequency divider (5) is looped to the input side of the phase comparator (1), and the ratio of switching between the two frequencies is determined by the phase difference between the looped output signal (d) and the input signal (a). and continuously adjust the phase of the output signal (d).

[Problems to be Solved by the Invention] The conventional digital PLL device as described above requires two or more oscillators that generate pulses with a frequency N times the upper and lower limits of the lock range.

Therefore, two or more expensive crystal oscillators or ceramic oscillators are required to be built into these oscillators, which poses a problem in that they are expensive and the circuit configuration becomes large.

This invention was made to solve this problem, and it is possible to configure a circuit with only one oscillator having an oscillator.
Another object of the present invention is to obtain a digital PLL circuit with a simple configuration.

[Means for Solving the Problems] A digital PLL circuit according to the present invention includes an oscillator having a crystal resonator, etc., and a signal having a frequency obtained by multiplying the output signal of the oscillator by an integer frequency division ratio x /y frequency divider to form two oscillators.

By alternately switching the output signals from these oscillators, an output signal whose phase is synchronized with the input signal is obtained.

[Function] This invention outputs a frequency pulse whose x/y frequency is N times the lower limit frequency of the lock range based on the output signal of the oscillator that generates the fundamental frequency signal. It becomes possible to configure it with one oscillator.

[Embodiment of the Invention] Hereinafter, an embodiment of the present invention will be described with reference to FIGS. 1 to 3. Components in the figure with the same reference numerals as in FIG. 4 are completely the same, and their explanation will be omitted here. In FIG. 1, (6) is an x/y frequency divider (x+y is an arbitrary integer, where x<y). 2 is a time chart showing each input signal of the phase comparator (1) shown in FIG. 1, and FIG. 3 is a time chart showing details of the signals in the main part of FIG. 1.

Next, the operation will be explained. The phase comparator (1) receives the input signal (a
The phase difference between the output signal (di) from the frequency divider (5) and the output signal (di) from the frequency divider (5) is compared, and the signal shown in FIG. 2 (bl) is output to the frequency switching circuit (2). In the frequency switching circuit (2), according to this signal, the output from the oscillator (3) and x/y
The output from the frequency divider (6) is switched. The time chart shown in FIG. 2 shows the time chart before and after this switching. Here, when the output of the x/y frequency divider (6) is the oscillation frequency of the oscillator (3) as f, at the lower limit of the lock range, select an arbitrary integer X so that (f) + Determine V. As a result, the output of the x/y frequency divider (6) becomes (f) Then, from (f)/N to (f
) x (x/y) / H, and the center frequency fo of the loop is (f)/N and (f)
/N. This can be expressed as a formula.

f o= ((f)/N+ (f) X (x/y)/
N)/2. In this case, the lock range fL (frequency range in which the PLL locks) is as follows.

f L = f/N - (f)/(x/y)/N.

Therefore 1, for example x=2. When y=3 and the lower limit frequency is 2/3 of the upper limit frequency, the output of the oscillator (3) in the x/y frequency divider (6) [Fig. When the pulses are erased at a ratio, the resulting pulse [FIG. 3 (fl)] has a duty change of this value, but is given a frequency of 2/3f. In this way, for the x/y frequency divider (6), the x/y frequency division ratio is
By setting 73.

The lower limit frequency can be easily obtained.

Here, the output of the frequency switching circuit (2) becomes a discontinuous signal at the time of switching (when switching between the output of the oscillator (3) and the x/y frequency divider 'a (6)), so the frequency is divided by 1. (5)
smooth out the sudden changes. After smoothing, divide by 1
The output of (5) is returned to the phase comparator (1) to form a loop. As a result, the switching ratio between the two frequencies is adjusted based on the phase difference between the input signal and the output signal, and the phase of the output signal is continuously adjusted.

[Effects of the Invention] As described above, according to the present invention, a digital P L is provided with an Since the L circuit is configured, an oscillator that requires a vibrator etc. can be configured with one, making it inexpensive, simplifying the circuit configuration, and furthermore, making it possible to easily determine the lock range width. This has the effect of providing a digital PLL circuit.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the block configuration of a digital PLL circuit according to an embodiment of the present invention, FIG. 2 is a time chart showing input and output waveforms of the phase comparator shown in FIG. 1, and FIG. 3 is a further diagram of FIG. A time chart showing the main output waveforms before and after switching the phase comparator, Figure 4 is a conventional digital PLL.
Figure S is a time chart showing the input and output waveforms of the phase comparator in Figure 4, and Figure 6 is a time chart showing the main part output waveforms before and after switching the phase comparator in Figure 5. It is a chart. In the figure, (1) is a phase comparator, (2) is a frequency switching circuit, (3) is an oscillator, (5) is a frequency divider, and (6) is an x/y frequency divider. Note that the same reference numerals in each figure indicate the same or equivalent parts.

Claims (1)

[Claims] In a digital PLL circuit that includes a plurality of oscillators that generate fixed frequency signals and obtains an output signal that is phase-synchronized with an input signal by alternately switching the outputs of the oscillators, the plurality of oscillators have a crystal resonator or the like. One oscillator and an x/y frequency divider that receives the output of this oscillator, sets a predetermined integer frequency division ratio, and outputs a signal with a frequency obtained by multiplying the frequency from the oscillator by the integer frequency division ratio. The output signal from the oscillator and the x/y frequency divider is alternately switched, and the discontinuous output signal after switching is smoothed to output an output signal that is phase-synchronized with the input signal. digital P
LL circuit.