JPS62169356A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS62169356A JPS62169356A JP61008959A JP895986A JPS62169356A JP S62169356 A JPS62169356 A JP S62169356A JP 61008959 A JP61008959 A JP 61008959A JP 895986 A JP895986 A JP 895986A JP S62169356 A JPS62169356 A JP S62169356A
- Authority
- JP
- Japan
- Prior art keywords
- oxide film
- silicon
- oxidation
- substrate
- gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims description 12
- 238000004519 manufacturing process Methods 0.000 title claims description 9
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 20
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 19
- 239000010703 silicon Substances 0.000 claims abstract description 18
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 238000005530 etching Methods 0.000 claims abstract description 8
- 238000000034 method Methods 0.000 claims description 10
- 150000002222 fluorine compounds Chemical class 0.000 claims description 7
- 230000001590 oxidative effect Effects 0.000 claims description 6
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims 1
- 239000003990 capacitor Substances 0.000 abstract description 17
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 abstract description 10
- 229910052760 oxygen Inorganic materials 0.000 abstract description 10
- 239000001301 oxygen Substances 0.000 abstract description 10
- 239000007789 gas Substances 0.000 abstract description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 abstract 1
- 229910052698 phosphorus Inorganic materials 0.000 abstract 1
- 239000011574 phosphorus Substances 0.000 abstract 1
- 230000003647 oxidation Effects 0.000 description 19
- 238000007254 oxidation reaction Methods 0.000 description 19
- 230000000694 effects Effects 0.000 description 7
- 229910052731 fluorine Inorganic materials 0.000 description 4
- 238000001020 plasma etching Methods 0.000 description 4
- 239000011737 fluorine Substances 0.000 description 3
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 230000007257 malfunction Effects 0.000 description 2
- 230000015654 memory Effects 0.000 description 2
- NJNFCDQQEIAOIF-UHFFFAOYSA-N 2-(3,4-dimethoxy-2-methylsulfanylphenyl)ethanamine Chemical compound COC1=CC=C(CCN)C(SC)=C1OC NJNFCDQQEIAOIF-UHFFFAOYSA-N 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 230000000052 comparative effect Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 125000001153 fluoro group Chemical group F* 0.000 description 1
- 238000010406 interfacial reaction Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- RJCRUVXAWQRZKQ-UHFFFAOYSA-N oxosilicon;silicon Chemical compound [Si].[Si]=O RJCRUVXAWQRZKQ-UHFFFAOYSA-N 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000012498 ultrapure water Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
- H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
- H01L21/28211—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation in a gaseous ambient using an oxygen or a water vapour, e.g. RTO, possibly through a layer
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/038—Making the capacitor or connections thereto the capacitor being in a trench in the substrate
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Chemical & Material Sciences (AREA)
- Physics & Mathematics (AREA)
- Crystallography & Structural Chemistry (AREA)
- Chemical & Material Sciences (AREA)
- General Physics & Mathematics (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、半導体装置の製造方法に係わり、たとえば立
体形状を有するシリコン基板上におけるＭＯＳキャパシ
タの製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device, and for example, to a method for manufacturing a MOS capacitor on a silicon substrate having a three-dimensional shape.
ＭＯＳダイナミックメモリ（ｄＲＡＭ）は比例縮小期に
従って素子の微細化、高集積化が進められている。ｄＲ
ＡＭの構成要素であるＭＯＳキャパシタも例外ではなく
、ゲート酸化膜厚ｔａｘ及び面積Ｓの縮小が進んでいる
。スケーリング係数をαとすると、ゲート酸化膜厚はｔ
ｏｘ／αに１面積はＳ／α２になる。ＭＯＳキャパシタ
の容量Ｃは誘電率をｉとして、 Ｃ＝εＳ／ｌａｘと表
わされるため。MOS dynamic memories (dRAMs) are becoming increasingly finer and more highly integrated in accordance with the period of proportional shrinkage. dR
MOS capacitors, which are components of AM, are no exception, and the gate oxide film thickness tax and area S are being reduced. When the scaling factor is α, the gate oxide film thickness is t
One area of ox/α becomes S/α2. The capacitance C of a MOS capacitor is expressed as C=εS/lax, where i is the dielectric constant.
比例縮小後の容量Ｃ′は、Ｃ’ ＝Ｃ／αとなり、１１
αに小さくなる。こうしてＭＯＳキャパシタの容量が小
さくなると、アルファ線飛来によるソフトエラーが起り
易くなり、またビット線の容量との比が小さくなってセ
ンス余裕が小さくなる結果誤動作を生じる原因になった
りする。このため一般にＭＯＳキャパシタの面積はＳ／
α２ではなく、Ｓ／αの縮小に止めることが行われてい
た。しかし世代毎に寸法縮小は進み、信頼性の高いｄ
ＲＡＭを得ることは限界に近付きつつある。The capacitance C' after proportional reduction is C' = C/α, which is 11
becomes smaller than α. When the capacitance of the MOS capacitor is reduced in this way, soft errors due to alpha rays are likely to occur, and the ratio with the capacitance of the bit line becomes smaller, resulting in a smaller sensing margin and resulting in malfunctions. For this reason, the area of a MOS capacitor is generally S/
The reduction was limited to S/α instead of α2. However, with each generation, the dimensions have been reduced, and highly reliable d
RAM availability is approaching its limits.
ＭＯＳキャパシタの容量を大きくする手段として、誘電
率の大きい絶縁膜１例えばＴａ２Ｏ，膜等を用いること
も検討されているが、未だ実用になっていない。また１
０ｎｍ以下の極めて薄い信頼性の高いシリコン酸化膜の
適用が検討されているが、これも極めて高純度の純水や
薬品を必要とし、また清浄度の高いクリーンルームを必
要とする、等の理由で実用になっていない。As a means to increase the capacitance of a MOS capacitor, the use of an insulating film 1 having a high dielectric constant, such as a Ta2O film, has been considered, but this has not yet been put to practical use. Also 1
The application of extremely thin and highly reliable silicon oxide films of 0 nm or less is being considered, but this also requires extremely high purity water and chemicals, as well as a highly clean room. It has not become practical.
そこで現在、ＭＯＳキャパシタの容量を増大する有力な
方法として、半導体基板表面に溝を掘り、占有面積を増
大させることなく実質的にキャパシタ面積の増大を図る
方法が検討されている。ところがこのような溝を１反応
性イオンエツチング（ＲＩＥ）のような異方性エツチン
グ法により垂直の側壁をもって形成すると、次のような
問題が生じる。即ちこの様な１（凹部）の上部或いは底
部のコーナーの部分（角部）は曲率半径が極めて小さく
、熱酸化によりゲート膜を形成した時、この角部におい
て平坦部より酸化膜厚が簿くなる。Therefore, currently, as an effective method for increasing the capacitance of a MOS capacitor, a method is being considered in which a groove is dug in the surface of a semiconductor substrate to substantially increase the capacitor area without increasing the occupied area. However, when such grooves are formed with vertical sidewalls by an anisotropic etching method such as reactive ion etching (RIE), the following problems occur. In other words, the radius of curvature of the top or bottom corner part (corner part) of such 1 (concave part) is extremely small, and when the gate film is formed by thermal oxidation, the oxide film thickness is smaller at this corner part than on the flat part. Become.
この現象は次のように説明されている。シリコンを酸化
すると、形成される酸化膜の体積は元のシリコンの約２
．３倍になる。 このため酸化が進行すると、シリコン
−シリコン酸化膜界面の酸化膜側では圧縮応力が働き、
前述の角部では応力の集中が起こる結果、酸化が抑制さ
れるものと思われる。This phenomenon is explained as follows. When silicon is oxidized, the volume of the oxide film formed is approximately 2 that of the original silicon.
．． It will be tripled. Therefore, as oxidation progresses, compressive stress acts on the oxide film side of the silicon-silicon oxide film interface.
It is thought that oxidation is suppressed as a result of stress concentration occurring at the aforementioned corners.
このように溝の底部或いは上部の角部で酸化膜厚が平坦
部より薄くなると、この部分は耐圧が低くなり低い電界
で大きいリーク電流が流れる原因となる。使用電圧での
リーク電流を十分小さく保つためにゲート酸化膜厚を厚
くすると、平坦部では厚くなりすぎ、溝を掘って面積を
大きくすることによる容量増大の効果が減殺されること
になる。If the oxide film thickness is thinner at the bottom or upper corner of the groove than at the flat portion, the withstand voltage will be lower in this portion, causing a large leakage current to flow in a low electric field. If the thickness of the gate oxide film is increased in order to keep the leakage current sufficiently small at the operating voltage, it will become too thick on the flat portion, and the effect of increasing the capacitance by enlarging the area by digging a trench will be negated.
本発明は、凹部または凸部を形成した半導体基板表面に
均一な厚さの酸化膜、例えばゲート酸化膜を形成して、
ＭＯＳキャパシタ等の信頼性を向上することができる。The present invention forms an oxide film of uniform thickness, for example, a gate oxide film, on the surface of a semiconductor substrate in which concave or convex portions are formed.
The reliability of MOS capacitors and the like can be improved.
半導体装置の製造方法を提供することを目的とする。The purpose of the present invention is to provide a method for manufacturing a semiconductor device.
本発明は、凹部または凸部が形成された半導体基板表面
を一旦フッ素化合物を含んだ酸化零四気中にさらし、前
記半導体基板上に熱酸化膜を形成する。しかる後、この
熱酸化膜をエツチング除去することによってシリコン表
面の凹部または凸部の形状に丸みをもたせ、その後シリ
コン表面に新たに酸化膜を形成する。In the present invention, the surface of a semiconductor substrate on which recesses or projections are formed is once exposed to oxidizing gas containing a fluorine compound, and a thermal oxide film is formed on the semiconductor substrate. Thereafter, this thermal oxide film is removed by etching to round the shape of the recesses or projections on the silicon surface, and then a new oxide film is formed on the silicon surface.
次に作用について簡単に説明する。 Next, the effect will be briefly explained.
フッ素化合物たとえばＮＦ３ガスを酸化性雰囲気に添加
するとＮＦ、はシリコン表面で熱的に解離し。When a fluorine compound such as NF3 gas is added to an oxidizing atmosphere, NF is thermally dissociated on the silicon surface.
ＮＦ、 ＮＦ、、 ＦあるいはＦ２といったフッ素系の
ラジカルを形成する。フッ素原子はシリコンに比べ電気
陰性度も太きく５ｉ−Ｆ結合の結合エネルギーは５ｉ−
Ｓｉ結合より大きいため、Ｓｉ表面ではフッ素化合物の
到達によってＳｉとＦが結合した状態とＳｉのダングリ
ングボンドの状態を形成する。ダングリングボンドにお
いてシリコンは酸素と結合しやすい。Forms fluorine radicals such as NF, NF,, F or F2. Fluorine atoms have higher electronegativity than silicon, and the bond energy of the 5i-F bond is 5i-
Since it is larger than a Si bond, a state in which Si and F are bonded and a state in which Si dangling bonds are formed are formed by the arrival of the fluorine compound on the Si surface. Silicon easily combines with oxygen in dangling bonds.
また５ｉ−１’結合はＦの電気陰性度がシリコンよりか
なり大きいためシリコン原子は正に電荷をもったイオン
性結合となっている。このため負のイオンをもつ酸素分
子との結合はより容易になる。Further, in the 5i-1' bond, since the electronegativity of F is considerably higher than that of silicon, the silicon atom is an ionic bond with a positive charge. Therefore, bonding with oxygen molecules containing negative ions becomes easier.
従ってフッ素のシリコン表面への到達はシリコンの酸化
性をより高くし、平均的に酸化における界面反応速度を
大きくする。Therefore, the arrival of fluorine on the silicon surface makes silicon more oxidizable and increases the interfacial reaction rate in oxidation on average.
例えば７００℃で１１００ｐｐのＮＦ、を添加した乾燥
酸素中でシリコン表面を酸化した場合、Ｍ形則酸化係数
Ｂ／Ａと放物線側酸化係数Ｂはそれぞれ、２．６Ｘ１０
″″２ｔＩＭ／ｈと４．９ Ｘ １０−’μｓ”／ｈで
あり、同温度の乾燥酸素中での酸化の場合は、［１／Ａ
＝２．６Ｘ１０−μｓ／ ｈ 、 Ｂ ＝３．６Ｘ１０
−４ｍ”／ ｈであり、ＮＦ３添加よりＢ／Ａが２桁大
きくなっている。 これから線形則領域から放物線側領
域への移行の目安となるＡ値は、 ＮＦ、を添加する
ことにより１．４μｓから１９０人に減少することがわ
かる。For example, when a silicon surface is oxidized in dry oxygen containing 1100 pp of NF at 700°C, the M-shaped oxidation coefficient B/A and the parabolic oxidation coefficient B are 2.6X10
""2 tIM/h and 4.9
=2.6X10-μs/h, B =3.6X10
-4 m"/h, and B/A is two orders of magnitude larger than when NF3 is added. From now on, the A value, which is a guideline for transitioning from the linear law region to the parabolic side region, is 1. It can be seen that the number of people decreases from 4 μs to 190 people.
つまり、 ＮＦ、を添加した乾燥酸素中の場合、乾燥
酸素中のみで酸化した場合と比べ、より薄い膜厚から拡
散律速による酸化に移行する。That is, in the case of dry oxygen containing NF, oxidation shifts to diffusion-controlled oxidation from a thinner film thickness, compared to the case of oxidation only in dry oxygen.
その結果、例えば凸部コーナ一部分は、凸部のコーナ一
部以外の平坦部に比べ応力の作用で酸化膜厚が薄く形成
されるがフッ素の到達によってフッ素化合物を添加しな
い場合に比べより早く拡散律速による酸化に入り、コー
ナ一部分でも平坦部とほぼ均一な膜厚を得ることができ
、又凹部コーナ一部分においては拡散律速による酸化は
逆に抑制されるのでＳｉ／５ｉｎ２界面は丸みを帯びた
形状に形成されるものと考えられる。As a result, for example, the oxide film is formed thinner on a part of the convex corner due to the effect of stress than on the flat part other than the part of the convex corner, but the fluorine reaches it and diffuses faster than when no fluorine compound is added. The rate-determined oxidation makes it possible to obtain a film thickness that is almost uniform with that of the flat part even in a corner part, and on the contrary, the diffusion rate-determined oxidation is suppressed in a part of the concave corner, so the Si/5in2 interface has a rounded shape. It is thought that it is formed in
第７図（ａ）〜（ｅ）は本発明の一実施例としてｄＲＡ
Ｍセルの製造工程を示す断面図である。先ず第１図（ａ
）に示すように、比抵抗ｌＯΩ／ａｍ程度のｐ型Ｓｉ基
板■に、 １００〜ｌｏｏＯｎｍ程度のフィールド酸化
膜■を形成する。このフィールド酸化膜■は例えば、窒
化膜をマスクとしたＬＯＣＯ８法。FIGS. 7(a) to (e) show dRA as an embodiment of the present invention.
It is a sectional view showing the manufacturing process of M cell. First, Figure 1 (a
), a field oxide film (2) with a thickness of about 100 to 100 nm is formed on a p-type Si substrate (2) with a specific resistance of about 10Ω/am. This field oxide film (2) is formed, for example, by the LOCO8 method using a nitride film as a mask.
全面に酸化膜を形成してこれを選択エツチングする方法
、或いはフィールド領域に予め溝を掘ってこの溝に酸化
膜の埋め込みを行う方法、等により形成する。この後、
ｄＲＡＭセルのＭＯＳキャパシタ領域内に、第１図（ｂ
）に示すように溝（３）を形成する。この溝■は例えば
、ＣＦ４． ＳＦ、 、 ＣＣｆｆ１．等を主成分とす
るガス或いはこれにＨが入ったガスを用いたＲＩＥ法に
より形成する。このＲＩＥ工程のマスクは通常のフォト
レジストではそれ自体もエツチングされて消失する場合
があるので、例えばＣＶ Ｄ ４ニーよる５ｘＯ２／
Ｓｘ３ Ｎ４ ／ ＳｘＯ，膜等を用イルことが好まし
い。The oxide film is formed by forming an oxide film on the entire surface and selectively etching it, or by digging a trench in the field region in advance and filling the trench with an oxide film. After this,
In the MOS capacitor area of the dRAM cell, there is a
) A groove (3) is formed as shown in FIG. This groove ■ is, for example, CF4. SF, , CCff1. It is formed by the RIE method using a gas mainly composed of or a gas containing H. Since the mask for this RIE process may be etched and disappear with ordinary photoresist, for example, 5xO2/
It is preferable to use a film such as Sx3N4/SxO.
この後、第１図（ｃ）のように８００℃で５０ｐｐｍの
ＮＦ。After this, 50 ppm of NF was applied at 800° C. as shown in FIG. 1(c).
を含んだ酸素中３０分間で一旦、酸化膜（イ）（丸め酸
化膜）を形成し、その後この酸化膜（イ）をエツチング
除去する。しかる後１周知の方法により第１図（ｄ）に
示す如く９００℃の乾燥酸素中で膜厚１５ｎｍのゲート
酸化膜■を形成し、さらにその上にグー１−１１極用リ
ン添加多結晶シリコン０を形成する。An oxide film (a) (rounded oxide film) is formed for 30 minutes in oxygen containing oxygen, and then this oxide film (a) is removed by etching. Thereafter, a gate oxide film (1) with a thickness of 15 nm is formed in dry oxygen at 900° C. as shown in FIG. form 0.
その後第１図（６）に示すように、第１図（ｄ）の多結
晶シリコン０をパターニングしてキャパシタ電極（６′
）を形成し、 次いでスイッチングＭＯ３ＦＥＴ領域■
に新たにゲート酸化膜（５′）を形成し、更にその上に
ゲート電極（６’）を形成し、ソース。Thereafter, as shown in FIG. 1(6), the polycrystalline silicon 0 of FIG. 1(d) is patterned to form a capacitor electrode (6'
), then the switching MO3FET region■
A new gate oxide film (5') is formed on top of the gate oxide film (5'), and a gate electrode (6') is formed thereon.
ドレイン領域のｎ＋形層■、（８）を形成して、第一図
（ｅ）に示したメモリセルを完成する。An n+ type layer (8) of the drain region is formed to complete the memory cell shown in FIG. 1(e).
以上のような実施例の効果を次に説明する。上記実施例
に従ってゲート酸化膜が形成された、１０００００個の
溝を含み且つキャパシタ電極を共通にしたＭＯＳキャパ
シタと、従来用いられている方法で乾Ｍ！酸素雰囲気中
、９００℃の条件でゲート酸゛化膜が形成された同様の
構造のＭＯＳキャパシタのリーク電流（ゲート電圧Ｖｇ
−電流ｒｇ特性）を比較した。第２図はその比較データ
である。図がら明らかなように本実施例では、従来方法
に比べてリーク電流が大幅に低減されている。The effects of the above-described embodiment will be explained next. A MOS capacitor including 100,000 grooves and having a common capacitor electrode, in which a gate oxide film is formed according to the above embodiment, and a dry M! Leakage current (gate voltage Vg
- current rg characteristics) were compared. Figure 2 shows the comparative data. As is clear from the figure, in this example, the leakage current is significantly reduced compared to the conventional method.
こうして本実施例によれば、酸化時に溝の角の部分での
応力集中をおこすことなく均一な厚さでゲート酸化膜を
形成することができ、ＭＯＳキャパシタのリーク電流の
増大をもたらすことなく、ゲート酸化膜厚を小さくして
大きい容量を得ることができる。In this way, according to this embodiment, the gate oxide film can be formed with a uniform thickness without causing stress concentration at the corner portions of the groove during oxidation, and without causing an increase in leakage current of the MOS capacitor. Large capacitance can be obtained by reducing the gate oxide film thickness.
なお上記実施例ではＮＦ、添加の酸化は８００’Ｃ，５
０ｐｐｍ、 Ｎ［’、１０□雰囲気で３０分間としたが
、 その条件は、本実施例に限定されるものではない。In the above example, NF was added, and the oxidation was at 800'C, 5
Although the conditions were set to 0 ppm, N[', and 10 □ atmosphere for 30 minutes, the conditions are not limited to those of this example.
例えば文献（Ｍ、Ｍｏｒｉｔａ、 ｅｔ、 ａｌ、 ａ
ｐｐｌ、 Ｐｈｙｓ。For example, in the literature (M. Morita et al.
ppl, Phys.
Ｌｅｔｔ、、Ｖｏｌ、４５．Ｎｏ、１２．Ｐ、］３１２
”Ｆｌｕｏｒｉｎｅ−ｅｎｈａｎｃｓｄ ｔｈｅｒ
ｍａｌ ｏｘｉｄａｔｉｏｎ ｏｆ ５ｉｌｉｃ
ｏｎ ｉｎ ｔｈｅｐｒｅｓｅｎｃｅ ｏｆ ＮＦ
、”（１９８４））に説明されているように酸化膜厚の
増加はＮＦ、の添加が微量の場合、酸化温度が高い程、
顕著である。又、ＮＦ、の添加量は増加するに従い酸化
膜のエツチングも同時に進行するので、酸化膜厚はＮＦ
ユ添加量に対してほぼ一定になる。それ故、ＮＦ、添加
量と酸化温度をパラメータとして、所望の酸化膜厚を適
宜形成してもよい。Lett, Vol. 45. No, 12. P,]312
”Fluorine-enhancsd the
mal oxidation of 5ilic
on in the presence of NF
(1984)), the increase in oxide film thickness increases as the oxidation temperature increases when a small amount of NF is added.
Remarkable. Furthermore, as the amount of NF added increases, the etching of the oxide film also progresses, so the thickness of the oxide film increases as the amount of NF increases.
It becomes almost constant depending on the amount of Yu added. Therefore, a desired oxide film thickness may be formed as appropriate by using NF, the amount added, and the oxidation temperature as parameters.
また本実施例ではＮＦ、添加による酸化膜Ｇ）はエツチ
ング除去し、その後ゲート酸化膜０を新たに形成したが
、ＮＦ、添加による酸化膜■をそのままゲート酸化膜と
して用いることも可能である。Further, in this embodiment, the oxide film G) caused by addition of NF was removed by etching, and then a new gate oxide film 0 was formed, but it is also possible to use the oxide film ① caused by addition of NF as it is as the gate oxide film.
本発明によれば、凹部または凸部等の立体形状を有する
半導体基板表面に均一な膜厚のゲート酸化膜を形成する
ことができる。これは本発明の条件に従えば、成長する
酸化膜中に残存する応力のＨ’ＪＰｊメ方向の積分値の
ばらつき（即ち、凹部や凸部の平坦部と角部での応力の
膜厚方向の積分値の差）が１０％程度以下に保たれ、こ
の結果応力集中が効果的に防止されるためである。従っ
てこのゲート酸化膜を用いて例えば容量が大きく且つリ
ーク電流の小さいＭＯＳキャパシタを形成することがで
きる。またこのＭＯＳキャパシタを用いて高集積化ｄＲ
ＡＭを構成すれば、ｄＲＡＭのソフトエラーによる誤動
作の確率を下げ、またセンスアンプの動作余裕を大きい
ものとすることができる。According to the present invention, a gate oxide film having a uniform thickness can be formed on the surface of a semiconductor substrate having a three-dimensional shape such as a concave portion or a convex portion. According to the conditions of the present invention, this is due to the variation in the integral value of the stress remaining in the growing oxide film in the H'JPj direction (i.e., the variation in the stress in the film thickness direction at the flat and corner parts of concave and convex parts). This is because the difference in the integral value of Therefore, this gate oxide film can be used to form, for example, a MOS capacitor with a large capacity and a small leakage current. Also, using this MOS capacitor, highly integrated dR
By configuring AM, it is possible to lower the probability of malfunction due to soft errors in dRAM, and to increase the operating margin of the sense amplifier.
更に一般に、酸化膜中の応力集中の緩和は、酸化雰囲気
中では約９５０℃以上から顕著となり、それ以下では応
力集中を緩和することは実際上困難となってくる。Furthermore, in general, relaxation of stress concentration in an oxide film becomes noticeable at temperatures above about 950° C. in an oxidizing atmosphere, and below that temperature, it becomes practically difficult to alleviate stress concentration.
しかし本発明においては凸部又は凹部等の立体形状を有
する半導体基板表面を酸化によって丸める（丸め酸化）
際、フッ素化合物を醸化性雰囲気中に添加することによ
り、８００℃以下の条件でも十分基板表面の立体形状を
丸める効果のある丸め酸化を低温処理にて行なうことが
可能である。However, in the present invention, the surface of a semiconductor substrate having a three-dimensional shape such as a convex portion or a concave portion is rounded by oxidation (rounding oxidation).
In this case, by adding a fluorine compound to the nurturing atmosphere, it is possible to perform rounding oxidation, which is effective in rounding the three-dimensional shape of the substrate surface, by low-temperature treatment even under conditions of 800° C. or lower.
第１図（ａ）〜（ｅ）は本発明の一実施例としてｄＲＡ
Ｍセルの製造工程を示す断面図、第２図は同実施例の効
果を説明する為のゲート酸化膜のリーク電流特性を従来
例と比較して示す特性図である。
１・・・ｐ型Ｓｉ基板、 ２・・・フィールド酸
化膜、３・・・溝、 ４・・・丸め酸化膜
。
５．５’、５“・・・ゲート酸化膜。
６・・・多結晶シリコソゲ−１−ｆｉｔ極、６’、６’
・・・多結晶シリコンゲート［極、７．８・・・ｎ十型
層。
代理人 弁理士 則 近 憲 倍
量 竹 花 喜久男FIGS. 1(a) to (e) show dRA as an embodiment of the present invention.
FIG. 2 is a cross-sectional view showing the manufacturing process of the M cell, and is a characteristic diagram showing the leakage current characteristics of the gate oxide film in comparison with a conventional example, in order to explain the effects of the same embodiment. DESCRIPTION OF SYMBOLS 1...p-type Si substrate, 2...field oxide film, 3...trench, 4...rounded oxide film. 5.5', 5"...Gate oxide film. 6...Polycrystalline silicon oxide-1-fit pole, 6', 6'
...Polycrystalline silicon gate [pole, 7.8...n-type layer. Agent Patent Attorney Nori Chika Kikuo Takehana
Claims (3)
を形成するにあたり、シリコン表面をフッ素化合物ガス
を添加した酸化性零囲気中で熱酸化して酸化膜を形成す
ることを特徴とする半導体装置の製造方法。(1) A semiconductor characterized in that when oxidizing a silicon surface having a three-dimensional shape to form an oxide film, the silicon surface is thermally oxidized in an oxidizing atmosphere containing a fluorine compound gas to form an oxide film. Method of manufacturing the device.
基板であることを特徴とする特許請求の範囲第１項記載
の半導体装置の製造方法。(2) The method for manufacturing a semiconductor device according to claim 1, wherein the silicon having a three-dimensional shape is a single crystal silicon substrate.
中で熱酸化膜を形成した後、これをエッチング除去し、
この熱酸化膜を除去した前記シリコン表面に所望の酸化
膜を形成することを特徴とする特許請求の範囲第１項記
載の半導体装置の製造方法。(3) After forming a thermal oxide film in an oxidizing zero atmosphere to which the fluorine compound gas is added, this is removed by etching,
2. The method of manufacturing a semiconductor device according to claim 1, further comprising forming a desired oxide film on the silicon surface from which the thermal oxide film has been removed.
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61008959A JP2602808B2 (en) | 1986-01-21 | 1986-01-21 | Method for manufacturing semiconductor device |
| US06/866,310 US4735824A (en) | 1985-05-31 | 1986-05-23 | Method of manufacturing an MOS capacitor |
| KR1019860004247A KR900000064B1 (en) | 1985-05-31 | 1986-05-29 | Method of manufacturing of capacity |
| DE19863618128 DE3618128A1 (en) | 1985-05-31 | 1986-05-30 | METHOD FOR PRODUCING A MOS CONDENSER |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61008959A JP2602808B2 (en) | 1986-01-21 | 1986-01-21 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62169356A true JPS62169356A (en) | 1987-07-25 |
| JP2602808B2 JP2602808B2 (en) | 1997-04-23 |
Family
ID=11707206
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61008959A Expired - Lifetime JP2602808B2 (en) | 1985-05-31 | 1986-01-21 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2602808B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6459847A (en) * | 1987-08-29 | 1989-03-07 | Sony Corp | Manufacture of semiconductor device |
| US6063654A (en) * | 1996-02-20 | 2000-05-16 | Semiconductor Energy Laboratory Co., Ltd. | Method of manufacturing a thin film transistor involving laser treatment |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4244456B2 (en) | 1999-08-04 | 2009-03-25 | 株式会社デンソー | Manufacturing method of semiconductor device, manufacturing method of insulated gate bipolar transistor, and insulated gate bipolar transistor |
| ITMI20010039A1 (en) | 2000-01-14 | 2002-07-11 | Denso Corp | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING ITSELF |
| US6864532B2 (en) | 2000-01-14 | 2005-03-08 | Denso Corporation | Semiconductor device and method for manufacturing the same |
| JP4200626B2 (en) | 2000-02-28 | 2008-12-24 | 株式会社デンソー | Method for manufacturing insulated gate type power device |
-
1986
- 1986-01-21 JP JP61008959A patent/JP2602808B2/en not_active Expired - Lifetime
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6459847A (en) * | 1987-08-29 | 1989-03-07 | Sony Corp | Manufacture of semiconductor device |
| US6063654A (en) * | 1996-02-20 | 2000-05-16 | Semiconductor Energy Laboratory Co., Ltd. | Method of manufacturing a thin film transistor involving laser treatment |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2602808B2 (en) | 1997-04-23 |
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