JPS62156835A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To make tapered throughholes with one step by a method wherein an interlayer film is etched by reactive ion etching process using a thin insulating film formed on the interlayer film as a mask. CONSTITUTION:An intermediate layer 5 (Silanol solution, heat treatment) comprising thin insulating film is formed to be coated with a resist film 6 for patterning process and then the intermediate layer 5 is etched by reactive ion etching process (RIE process) using CF4+H2 gas and the resist film 6 as a mask. Later, an interlayer film 4 is anisotropically etched by RIE process using mixed gas of O2 gas with CHF3 gas as fleon base gas as well as the resist film 6 and intermediate layer 5 as masks to make throughholes 7. After removing the resist film 6 in parallel with the etching process of throughholes 7, the intermediate layer 5 is removed by side etching process from the periphery of opening windows. Through these procedures, the throughholes 7 can be formed taking tapered sectional shape with less dimensional conversion difference.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device in which a multilayer wiring structure is formed on a semiconductor substrate, and in particular to a method for manufacturing a semiconductor device in which a multilayer wiring structure is formed on a semiconductor substrate. Regarding how to open.

[Conventional technology]

2. Description of the Related Art With the recent increase in the degree of integration of semiconductor devices, a multilayer wiring structure has been adopted as a wiring structure formed on a semiconductor substrate. In this multilayer wiring structure, an insulating interlayer film is used to insulate and separate the upper and lower wiring layers, and the upper and lower wiring layers are electrically connected to each other from the base to the substrate through through holes opened in this interlayer film. is connected to.

Conventionally, this type of interlayer film using polyimide resin containing silicon has been proposed, and an anisotropic etching method using 02 gas has been used to form through holes in this. There is.

[Problem that the invention seeks to solve]

In the conventional through hole forming method described above, in order to perform etching with a small dimensional difference between the planned through hole and the actually formed through hole, that is, a small dimensional conversion difference, the pressure of the 02 gas must be set to 15 mTorr or less. It is necessary to set it to a low pressure. However, etching using this pressure has a low etching rate and tends to generate silicon residue, making it difficult to quickly form good through holes.

Additionally, a method of etching by mixing 02 gas with fluorine gas has been proposed, but there is a limit to increasing the etching speed, and it is difficult to eliminate the silicon residue mentioned above. There are problems such as the reaction products re-adhering to the side walls of the through-hole or causing deposition.

Furthermore, it is preferable to form through holes in the wiring layer on the interlayer film in a tapered shape in order to improve the coverage at the step, but in the conventional method, wet etching method and dry etching method must be used in combination. There is also the problem that a tapered through ball cannot be formed in one step.

[Means for solving problems]

The method of manufacturing a semiconductor device of the present invention is capable of forming a tapered through hole in one step without causing reattachment or deposition of silicon residue or products.

The method for manufacturing a semiconductor device of the present invention includes forming a thin insulating film as an intermediate layer on the interlayer film and using this as a mask when forming a through hole in a multilayer wiring using silicon-containing polyimide resin as an interlayer film, and Etching is performed by a reactive ion etching method using a mixed gas of 02 gas and Freon gas.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIGS. 1(a) to 1(e) are cross-sectional views showing an embodiment of the present invention in the order of steps.

First, as shown in FIG. 1A, the surface insulation 11 of the semiconductor substrate 1 is
'i! Aluminum wiring 3 of a desired pattern is formed on 2 by a conventional method. Then, a polyimide resin containing silicon is applied onto these aluminum wiring lines 3,
This is then heat-treated at a high temperature to form an interlayer film 4 as shown in FIG.
form.

Next, apply a silanol solution as shown in the same figure (c),
This is baked at 200° C. for 30 minutes to form an intermediate layer 5 made of a thin insulating film. A resist film 6 is coated thereon and patterned, and the intermediate layer 5 is etched using the resist film 6 as a mask to obtain the structure shown in FIG. 4(d). The intermediate layer 5 is etched using a reactive ion etching method (RrE method) using CF4 + H2 gas.

Thereafter, the interlayer film 4 is etched using the resist film 6 and the intermediate layer 5 as a mask, and a through hole 7 is formed as shown in FIG. 4(e). For this etching, anisotropic etching is performed by the tE method using a mixed gas of 0□ gas and CHF, which is a Freon gas. In addition, at this time, the total amount of mixed gas is 1005 CCM or more, the flow rate ratio (0□/CHF,) is set to 1.0 to 1.4, and the pressure is set to 45 to 75 mT.

Set to the range of rr. In addition, the electrodes of etching equipment,
Here, a high frequency of 13.56 MHz is applied to the cathode side.
．． It is applied at a power density of 3 W/cm'' or more.

As a result, after the resist film 6 is removed as the etching of the through hole 7 progresses, the intermediate layer 5 is side-etched from the periphery of the opening window and retreats, as shown in FIG. The through hole 7 is formed to have a small dimensional conversion difference and a tapered cross-sectional shape.

In addition, Figure 2 shows that when etching silicon-containing polyimide resin by mixing 02 gas and CHF:+ gas, side wall re-adhesion and bottom surface deposition may occur due to differences in gas flow rate and pressure settings, and the diagonally shaded area may occur. This shows that a result is obtained in which these defects do not occur at all.

Furthermore, Figure 3 shows that depending on the difference in the flow rate ratio between 02 gas and CHF3 gas, silicon residue, redeposition, and deposition may occur, or results may be obtained in which these do not occur at all as shown in the shaded area. ing.

The through hole 7 formed in this way has an interlayer llI
For the silicon-containing polyimide resin that constitutes 24,
RIE using a mixed gas of 02 gas and Freon gas
Since the etching is carried out using the etching method and under the conditions of the shaded areas in FIGS. 2 and 3, through-holes can be formed without silicon residue, redeposition, or deposition. Additionally, silanol solution is applied as a mask during etching.

Since the intermediate layer 5 is a heat-treated thin insulating film, in combination with the RIE etching method using a mixed gas described above, a through hole with a small dimensional change difference and a tapered cross section can be formed in one step. It can also be formed.

〔Effect of the invention〕

As explained above, in the present invention, when forming through-holes in multilayer wiring using silicon-containing polyimide resin as an interlayer film, etching is performed by the RIE method using a mixed gas of 0□ gas and Freon gas. Therefore, it is possible to easily form a good through hole without silicon residue, redeposition, or deposition. Furthermore, by using a thin intermediate layer made of insulating material as a mask during etching of through holes, in conjunction with the etching method described above, through holes with small dimensional conversion differences and tapered cross sections can be easily formed.

[Brief explanation of drawings]

FIGS. 1(a) to (e) are cross-sectional views showing an embodiment of the present invention in the order of steps, and FIGS. 2 and 3 are diagrams showing the correlation between gas flow rate-pressure, flow rate ratio, and etching state, respectively. be. 1... Semiconductor substrate, 2...'4tA edge film, 3...
Aluminum wiring, 4... interlayer film, 5... intermediate layer,
6...Resist, 7...Through hole. Figure 1 Figure 2 Drawing force (mbrr) Figure 3 CHF, J-p (sccm)

Claims (1)

[Scope of Claims] 1. An interlayer film formed on a substrate that insulates and isolates upper and lower wiring layers from each other is composed of silicon-containing polyimide resin, and the above-mentioned upper,
When manufacturing a semiconductor device having a multilayer wiring structure that electrically connects the lower wiring layer, a thin insulating film as an intermediate layer is formed in a desired pattern on the interlayer film, and O_2 gas is applied using this thin insulating film as a mask. A method for manufacturing a semiconductor device, comprising etching the interlayer film using a reactive ion etching method using a mixed gas of a Freon gas and a Freon gas to form a through hole. 2. The method of manufacturing a semiconductor device according to claim 1, wherein a thin insulating film as the intermediate layer is coated with a silanol solution and heat-treated. 3. The method of manufacturing a semiconductor device according to claim 1, wherein the flow rate ratio of the mixed gas of O_2 gas and Freon gas is set in the range of 1.0 to 1.4, and the pressure is set in the range of 45 to 75 mTorr. 4. The method of manufacturing a semiconductor device according to claim 1, wherein the etching is performed by applying a high frequency of 13.56 MHz between the electrodes of an etching device at a power density of 1.3 W/cm^2 or more.