JPS62155523U - - Google Patents
Info
- Publication number
- JPS62155523U JPS62155523U JP4224386U JP4224386U JPS62155523U JP S62155523 U JPS62155523 U JP S62155523U JP 4224386 U JP4224386 U JP 4224386U JP 4224386 U JP4224386 U JP 4224386U JP S62155523 U JPS62155523 U JP S62155523U
- Authority
- JP
- Japan
- Prior art keywords
- input terminal
- voltage
- resistor
- pulse width
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000000295 complement effect Effects 0.000 claims 6
- 238000010586 diagram Methods 0.000 description 5
- 239000003990 capacitor Substances 0.000 description 2
Landscapes
- Pulse Circuits (AREA)
Description
第１図は本考案の１実施例を示す回路図、第２
図は従来例を示す回路図、第３図は従内来例の動
作を説明する波形図、第４図は本考案の１実施例
の動作を説明するための波形図。
１，２：原信号入力端子、３，８，１５：ＩＣ
ゲート、４，５，９，１０，１６，１７：エミツ
タ抵抗、１３：入力抵抗、１４：帰還抵抗、６，
７，１８，１９：入力信号と調整電圧の結合抵抗
するための抵抗、１１：原調整電圧入力端子、１
２：ＶＢＢ入力端子、２１，２２：調整幅拡大用
コンデンサ、１０１：原信号入力端子、１０２，
１０６，１１１：ＩＣゲート、１０３，１０７，
１１３：エミツタ抵抗、１０４：調整幅拡大用抵
抗、１０５：調整幅拡大用コンデンサ、１０８：
原調整電圧入力端子、１０９：ＶＢＢ入力端子、
１１０：入力抵抗、１１２：帰還抵抗。
Figure 1 is a circuit diagram showing one embodiment of the present invention, Figure 2 is a circuit diagram showing one embodiment of the present invention.
The figure is a circuit diagram showing a conventional example, FIG. 3 is a waveform diagram explaining the operation of the conventional example, and FIG. 4 is a waveform diagram explaining the operation of one embodiment of the present invention. 1, 2: Original signal input terminal, 3, 8, 15: IC
Gate, 4, 5, 9, 10, 16, 17: Emitter resistance, 13: Input resistance, 14: Feedback resistance, 6,
7, 18, 19: Resistor for combining input signal and adjustment voltage, 11: Original adjustment voltage input terminal, 1
2: VBB input terminal, 21, 22: Adjustment width expansion capacitor, 101: Original signal input terminal, 102,
106, 111: IC gate, 103, 107,
113: Emitter resistance, 104: Resistor for expanding adjustment width, 105: Capacitor for expanding adjustment width, 108:
Original adjustment voltage input terminal, 109: VBB input terminal,
110: Input resistance, 112: Feedback resistance.
Claims (1)
、前記第１の入力端子に接続された第１の電圧入
力回路と、前記第２の入力端子に接続された第２
の電圧入力回路とから構成され、前記第１の電圧
入力回路が信号入力端子と前記第１の入力端子を
結ぶ第１の抵抗と、調整電圧入力端子と前記第１
の入力端子を結ぶ第２の抵抗とから構成されるパ
ルス幅調整回路。 ２ 前記第２の電圧入力回路が前記第２の入力端
子に接続された定電圧電源であることを含む実用
新案登録請求の範囲第１項記載のパルス幅調整回
路。 ３ 前記第２の電圧入力回路が相補信号入力端子
と前記第２の入力端子を結ぶ第３の抵抗と、相補
調整電圧入力端子と前記第２の入力端子を結ぶ第
４の抵抗とで構成され、前記相補信号が前記信号
の相補信号で、前記相補調整電圧が前記調整電圧
の相補電圧である実用新案請求の範囲第２項記載
のパルス幅調整回路。 ４ 前記第１の抵抗と前記第２の抵抗の抵抗値の
比が前記第３の抵抗と前記第４の抵抗の抵抗値の
比に等しいことを含む実用新案登録請求の範囲第
３項記載のパルス幅調整回路。 ５ 前記第１、第２、第３、第４の抵抗の全てを
同一の抵抗値のものとすることを含む実用新案登
録請求の範囲第４項記載のパルス幅調整回路。 ６ 前記第１、第２の抵抗の抵抗値を等しくする
ことを含む実用新案登録請求の範囲第１項記載の
パルス幅調整回路。[Claims for Utility Model Registration] 1. A differential comparator having first and second input terminals, a first voltage input circuit connected to the first input terminal, and a first voltage input circuit connected to the second input terminal. connected second
a voltage input circuit, the first voltage input circuit includes a first resistor that connects the signal input terminal and the first input terminal, and a voltage input circuit that connects the adjustment voltage input terminal and the first input terminal.
and a second resistor connected to the input terminal of the pulse width adjustment circuit. 2. The pulse width adjustment circuit according to claim 1, wherein the second voltage input circuit is a constant voltage power supply connected to the second input terminal. 3. The second voltage input circuit includes a third resistor that connects the complementary signal input terminal and the second input terminal, and a fourth resistor that connects the complementary adjustment voltage input terminal and the second input terminal. 3. The pulse width adjustment circuit according to claim 2, wherein the complementary signal is a complementary signal of the signal, and the complementary adjustment voltage is a complementary voltage of the adjustment voltage. 4. Utility model registration claim 3, wherein the ratio of the resistance values of the first resistor and the second resistor is equal to the ratio of the resistance values of the third resistor and the fourth resistor. Pulse width adjustment circuit. 5. The pulse width adjustment circuit according to claim 4, wherein the first, second, third, and fourth resistors all have the same resistance value. 6. The pulse width adjustment circuit according to claim 1, which includes making the resistance values of the first and second resistors equal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1986042243U JPH0339945Y2 (en) | 1986-03-20 | 1986-03-20 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1986042243U JPH0339945Y2 (en) | 1986-03-20 | 1986-03-20 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62155523U true JPS62155523U (en) | 1987-10-02 |
| JPH0339945Y2 JPH0339945Y2 (en) | 1991-08-22 |
Family
ID=30857972
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1986042243U Expired JPH0339945Y2 (en) | 1986-03-20 | 1986-03-20 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0339945Y2 (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS53906A (en) * | 1976-05-04 | 1978-01-07 | Bio Communication Res | Method and device for filtering environmental noise from speech |
| JPS53114949U (en) * | 1977-02-18 | 1978-09-12 | ||
| JPS5922436A (en) * | 1982-07-28 | 1984-02-04 | Hitachi Ltd | Variable delay circuit |
| JPS61127224A (en) * | 1984-11-26 | 1986-06-14 | Fujitsu Ltd | Pulse width variable circuit |
-
1986
- 1986-03-20 JP JP1986042243U patent/JPH0339945Y2/ja not_active Expired
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS53906A (en) * | 1976-05-04 | 1978-01-07 | Bio Communication Res | Method and device for filtering environmental noise from speech |
| JPS53114949U (en) * | 1977-02-18 | 1978-09-12 | ||
| JPS5922436A (en) * | 1982-07-28 | 1984-02-04 | Hitachi Ltd | Variable delay circuit |
| JPS61127224A (en) * | 1984-11-26 | 1986-06-14 | Fujitsu Ltd | Pulse width variable circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0339945Y2 (en) | 1991-08-22 |
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