JPS62154023A - Mask read control system for operand data - Google Patents

Abstract

PURPOSE:To operate a floating point arithmetic at high speed by separating and fetching the code of an operand, an exponential part and a mantessa part in the floating point arithmetic through the use of a microinstruction having a mask specification field when said separating and fetching are executed by the architecture of one bus type. CONSTITUTION:Information specifying the operand in a floating register FR2 is set to the source field 11 of the microinstruction 1. Information controlling the mask logical function of a mask logic circuit 3 is set in mask control fields MSK and CTL. Then mask data is set to an immediate data field 13. Plural fetched operands (floating point data) are stored in the floating register FR2. The mask logic circuit 3 executes a logic operation, extracts the specified part in the operand, and outputs it to an internal bus 4. Since the microinstruction includes mask information in it and mask processing is executed the moment the operand is read, the mask of the operand can be quickly processed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] When separate fetching of the sign, exponent part, mantissa part, etc. of an operand in a floating-point operation is performed using a one-bus architecture, it is performed using a microinstruction having a mask specification field.

[Industrial application field]

The present invention relates to an arithmetic operation device for a computer,
In particular, the present invention relates to a mask read control method useful for separating each element part of an operand in floating point arithmetic.

[Conventional technology]

Generally, in floating point operations in computers, the operands are fetched from main memory, and the sign and exponent parts are fetched from the main memory.

It is necessary to separate the mantissa area and perform the operation.

By the way, in a computer with a one-pass architecture,
It is not possible to separate the sign, exponent, and mantissa areas from the fetched operand in one step as in a multi-bus (n-bus) architecture; in general, the fetched data is separated from the fetched operand in one step.

- After loading into the work area of reciprocal memory, a method is used to separate using a mask. This separation typically requires multiple steps.

FIG. 5 shows an example of a floating point arithmetic mechanism using a conventional one-pass architecture, and FIG. 6 shows its control flow.

In Figure 5, 2 is a floating register (2) that temporarily stores data fetched from the main memory.
FR), 4 is internal bus, 5 is work register (WR)
, 6 is an arithmetic operation unit (ALU).

Next, the operation of the mechanism shown in FIG. 5 will be explained according to steps (1) to (2) of the control flow shown in FIG. It is assumed that a first mask for separating the exponent part and a second mask for separating the mantissa part are prepared in advance as immediate data.

■ From floating register (FR) 2.

Read the first operand and read the internal bus 4. Through the arithmetic operation unit (ALU) 6, the work register (WR)
Load into 5.

(2) The arithmetic operation unit (ALU) 6 separates the exponent part from the first operand using the first mask and stores it in the work register (WR) 5.

(2) Similarly, separate the mantissa from the first operand using the second mask and store it in the work register (WR) 5.

■ Read the second operand from floating register (FR) 2 and load it into work register (WR) 5.

■ Separate the exponent part from the second operand using the first mask and store it in the work register (WR) 5.

■ Separate the mantissa from the second operand using the second mask and store it in the work register (WR) 5.

■ From work register (WR) 5, the first and second
Reads each exponent part data of the operand, executes the operation specified by the arithmetic operation unit (ALU) 6,
Store the result in work register (WR) 5.

■ From work register (WR) 5, the first and second
reads each mantissa data of the operand, executes the operation specified by the arithmetic operation unit l-(ALU) 6,
Store the result in work register (WR) 5.

■ Combine the results of the exponent and mantissa operations, store them in main memory, and exit.

[Problem that the invention seeks to solve]

Conventional computers with one-pass architecture have the disadvantage that during floating-point operations, masking of operands takes time, which slows down the operation speed. On the other hand,
By adopting a multi-bus architecture, it is easy to separate the sign, exponent, and mantissa in an operand, and
This can be achieved using steps, but on the other hand, there is a problem in that the amount of hardware increases.

[Means for solving problems]

The present invention provides immediate input to macro instructions that control floating-point operations in a one-pass architecture.
Use a microinstruction with a data (immediate) field, set mask data in that field, and fetch from the operand.

Necessary data such as sign, exponent, and mantissa can be directly specified separately.

FIG. 1 is a block diagram of a floating point arithmetic mechanism of a one-pass type architecture showing the principle of the present invention.

In the figure, 1 is a microinstruction, 11 is a source specification field (Source), 12 is a mask control field (MSK CTL), 13 is an immediate data field (1mm Data), 2 is a floating register (FR), 3 4 represents a mask logic circuit, and 4 represents an internal bus.

In source field 11 of microinstruction 1.

Information specifying the operand in floating register (FR) 2 is set. Further, information for controlling the mask logic function of the mask logic circuit 3 is set in the mask control field (MSK CTL). and immediate data field 13 (1mm Data
) is set with mask data.

Floating register (FR) 2 contains the fetched operands (in this case floating point data)
is stored.

The mask logic circuit 3 includes a floating register (FR
)2 and the immediate data field (1mm Data
) Executes logical operations such as AND and OR with the 13 mask data, extracts a specified part in the operand, and outputs it to the internal bus 4.

The internal bus 4 has 9 arithmetic units A (not shown).
It is connected to the LU and the sign, exponent, and mantissa separated from the operand are transferred.

[Effect]

According to the present invention, the mask information is included in the microinstruction itself, and the masking process is performed at the same time as operand reading, so that the operand masking process can be performed quickly.

FIG. 2 shows an example of operation for separating individual element parts from operand data according to the configuration of the present invention.

Figure 2(a) shows floating register (FR) 2
This is operand data in floating point format read from , and consists of a sign S, an exponent part, and a mantissa part.

FIG. 2(b) shows the mask data set in the immediate data field 13 of microinstruction 1. In order to separate only the exponent part from the operand data, only the bits in the area corresponding to the exponent part are "1" is set, and the rest are "0".

FIG. 2 (C1) shows data outputted onto the internal bus 4 by ANDing the data (a) and (b) in the mask logic circuit 3, masking parts other than the exponent part.

〔Example〕

FIG. 3 shows the configuration of an embodiment of a floating point arithmetic unit using a one-bus type architecture according to the present invention, and FIG. 4 shows its control flow.

In Figure 3, 1 is a microinstruction, 2 is a floating register (FR), 3 is a mask logic circuit, 4 is an internal bus, 5 is a work register (WR), and 6 is an arithmetic operation unit (ALU). be.

Next, the operation of the embodiment shown in FIG. 3 will be described in accordance with steps (1) to (2) of the control flow shown in FIG.

■ From floating register (FR) 2.

Reads the first operand of floating point operation.

The mask logic circuit 3 separates only the exponent part and loads it into the work register (WR) 5.

At this time, the mask control field and immediate data field of microinstruction 1 have information for masking logic circuit 3 other than the exponent part in the first operand.

■ Similarly, floating register (FR) 2
, the second operand is read out, its exponent part is separated and loaded into the arithmetic operation unit (ALU) 6, and the exponent parts of the two operands are operated on. The result is work.
Store in register (WR) 5.

(2) Next, the first operand is read from the floating register (FR) 2 again, and the mask logic circuit 3 separates the mantissa part and loads it into the work register (WR) 5.

■ Similarly, separate the mantissa for the second operand,
The data is loaded into the arithmetic operation unit (ALU) 6, and the mantissa parts of the two operands are operated on.

The result is stored in the work register (WR).

■ Combine the exponent and mantissa data of the calculated result and store it in main memory.

〔Effect of the invention〕

According to the present invention, the microinstruction for arithmetic control can provide mask data as an immediate value.

When fetched operand data is read into the arithmetic operation unit, it is possible to simultaneously separate the necessary elements within it, enabling high-speed processing of floating point operations even on computers with a single-bus architecture. It can be done.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the basic configuration of the present invention, FIG. 2 is an explanatory diagram showing an example of operand data separation operation according to the present invention, FIG. 3 is a diagram showing the configuration of one embodiment of the present invention, and FIG. 3 is a control flow diagram for explaining the operation of the embodiment configuration shown in FIG. 3, and FIG. 5 is a configuration diagram of a conventional example. FIG. 6 is a control flow diagram for explaining the operation of the conventional configuration shown in FIG. In Figure 1. 1: Microinstruction 11: Source field (SOURCE) 12: Mask control field (MSK CTL) 13: Immediate data field (Imm Data) 2: Floating register (FR) 3: Mask logic circuit 4: Internal lotus Patent applicant: Patent attorney representing Panafacom Co., Ltd.
Fumi Hiroshi (1 other person) for Hase (1 person) Ohe 3 nt 1 te 2 7 Hon 4 Ta Akira 1; -(Beragu No. 31211 Iashirai 5 "Oki matter'l #70- Iirirai 1511 Rito A Fig. 5

Claims (1)

[Scope of Claims] A computer with a one-bus architecture, comprising a mask logic circuit (3) that performs a predetermined mask operation using mask data on operand data read from the main memory, As a microinstruction for controlling an operation, a microinstruction (1) having an immediate data field (13) is used, mask data is set in the immediate data field (13), and the microinstruction (1) When executing, the mask data of the immediate data field (13) is applied to the mask logic circuit (3) to cause a mask operation to be performed on the operand data read from the main memory. Features a mask read control method for operand data.