JPS62152002A - Programmable controller - Google Patents

Abstract

PURPOSE:To attain the on-line editing of programs at a high speed without giving any effect to a logical decoding operation, by providing a shadow memory to store the same contents as a logic memory and changing the contents of the shadow memory. CONSTITUTION:When a request is received for change of the contents of a logic memory 1, a CPU performs the changing operations to a shadow memory 2 for insertion, addition, deletion, etc. Here a logical decoding part 3 reads out successively the memory 1 for logical decoding processing. When the change is through with the memory 2, an editing end signal 13 is supplied to a read/ write control part 4. Then the part 3 reads out successively the memory 2 for logical decoding processing in the next scan mode. In this case, the data are transferred to the memory 1 from the memory 2 via a data buffer 6. Then the contents of the memory 2 are coincident with those of the memory 1 when the logical decoding processing is through with a single scan. Thus the memory 1 is used again for the logical decoding process at and after the next scan.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a programmable controller.

[Conventional technology]

Conventionally, a programmable controller cyclically performs 170 services, logic decoding, and communication processing as shown in FIG.

Online editing, such as changing a user program, has conventionally been performed as follows.

(1) When inserting or adding a new program between existing programs.

■) Shift the last block of the part of the logical memory where the program exists backwards by the number of newly added steps.

II) Write NOP (invalid instruction) to the vacant part.

First perform the above two operations, and if the block does not require insertion, proceed as follows.

■) Shift the next block backward by the number of insertion steps.

■) Write NOP in the empty space.

Repeat the operations m) and rv) above, and when the insertion position is reached, 1) write a new program into the empty area.

The above operations are performed by dividing into several scans so that one scan is as long as possible.

(2) When deleting an existing program.

Deletion of any part of an existing program is accomplished by moving data in the opposite direction of the insertion.

(2) The program to be deleted is deleted by moving the subsequently occupied program forward by the number of steps to be deleted.

(2) Write NOP in the empty space created by the movement.

Perform the above two operations first, and then proceed to the final area. ■) Shift the program by the number of steps to be deleted.

■) Write NOP in the empty space.

m) and rV) are performed in multiple scans, and when the final area is reached, only m) is moved.

With the above steps, deletion is completed.

[The problem that the invention attempts to solve]

In the conventional method mentioned above, editing is not done all at once but divided into several sections, so it takes time to complete the editing process, and the scanning process is also long. The downside is that the responsiveness is not very good.

An object of the present invention is to provide a programmable controller that allows online editing of programs at high speed without affecting U2'W on scanning.

(Part of the solution to the problem) The programmable controller of the present invention has a shadow memory that stores the same contents as the logical memory, and when a request to change the contents of the logical memory occurs, the programmable controller of the present invention stores the same contents as the logical memory. performs a change operation, and when the change operation is completed, transfers data from the shadow memory to the logical memory;
The present invention is characterized by comprising a logic decoding unit capable of decoding the logic of the logical memory in parallel with the modification operation on the shadow memory, and also capable of decoding the logic of the shadow memory in parallel with the data transfer. .

[For production]

In this way, by providing a shadow memory that stores the same contents as the logical memory, and making changes to the contents of this shadow memory, it is possible to quickly edit programs online without affecting the logical decoding. .

〔Example〕

Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the programmable controller of the present invention.

In this embodiment, it is separate from the logical memory 1 and has the same capacity.

A shadow memory 2 is provided which stores the same contents as the logical memory 1 in a normal state. The data buffer 5 holds data read from the shadow memory 2 or data from a CPU (not shown). data buffer 6
Data 21 is held in . The data buffer 7 holds the data read from the logic memory I or the data 21 held in the data buffer 76. The read/write controller 4 normally outputs a read signal 17 or a write signal 18 to the logic memory 1 in response to a read signal 11 or a write signal 12 from the logic decoder 3, and also outputs a read signal 17 or a write signal 18 to the logic memory 1.
Read signal 9 or write from O (read signal 15 or write signal I to shadow memory 2 from No. 3 10)
6, but when the editing completion signal 13 is output manually from the CPU, the read signal 15 and the write signal! 8 and enables the data buffer 6, and
When the scan completion signal 14 is manually output from the logic decoder 3, the output of the read signal 17 is stopped. The logic memory 1 is given the address signal I9 from the logic decoder 3, and the shadow memory 2 is given the address signal I9 through the address buffer 8.
9 or an address signal 20 from the CPU is applied.

In the normal state, the logic decoder 3 sequentially reads the logic memory 1 and performs logic decoding. Here, when a request to change the contents of the logical memory 1 occurs, the CPU performs changing operations such as insertion, addition, and deletion on the shadow memory 2. At this time, at the same time, the logic decoding section 3 successively reads out the 2-fill memory 1 and performs the logic decoding process in the same way as in normal times.

Modification operations on the shadow memory 2 are continuous without being interrupted by logic decoding scans. When the changes to the shadow memory 2 are completed, an edit completion signal 13 is input to the read/write control section 4, and in the next scan, the logic decoding section 3 sequentially reads the shadow memory 2 and performs logic decoding. At this time, data is simultaneously transferred from the shadow memory 2 to the logic memory 1 via the data buffer 6. As a result, when the logical decoding of this one scan is completed, the contents of the shadow memory 2 and the contents of the logical memory 1 become the same. Therefore, from this next scan, the logic memory 1 is used again to perform logic decoding.

Note that data is transferred from the shadow memory 2 to the logic memory 1 in the cycle in which the logic decoder 3 reads the shadow memory 2. This operation will be explained in detail as follows.

(1) When the change to the shadow memory 2 is completed, the C11U outputs the edit completion r signal 13 in the form of a pulse to the read/write control unit 4 immediately before the logical decoding of the next scan begins.

(2) Read/Write: The b control section 4 holds the edit completion r signal 13.

■In this state, the read/write control unit 4 receives the read signal 11 from the logic decoding unit 3, and the read/write control unit 4 sends the read signal 15 to the shadow memory 2, and the write signal 15 to the logic memory 1. A signal 18 is output. At the same time, the address to the shadow memory 2 becomes the same as the address 19 output from the logic decoder 3, ie, the address 19 to the logic memory 1, by switching the address buffer 8.

Therefore, the data 21 read from the shadow memory 2 is input to the logic decoder 3 via the data buffer 6 and simultaneously written to the logic memory 1.

In addition, for scans other than those in which the above transfer process is performed,
Logical memory 1 and shadow memory 2 are completely separated.

〔Effect of the invention〕

As explained above, the present invention includes a shadow memory that stores the same contents as the logical memory, and by changing the contents of the shadow memory, the program can be changed without affecting the logical decoding at all. Moreover, if you practice using subroutines in the case of sequential reading/decoding type and variable program ascending type, it will be possible to make online changes that were previously impossible.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the programmable controller of the present invention, and FIG. 2 is a flowchart showing the processing of the programmable controller. 1...Logic memory, 2...Shadow memory 2
3...Logic decoding unit, 4...Read/write; outside, 5.6.7-...data buffer, 8...address buffer.

Claims (1)

[Claims] In a programmable controller, there is a shadow memory that stores the same contents as the logical memory, and when a request to change the contents of the logical memory occurs, a change operation is performed on the shadow memory, and when the change operation is completed, ,
A means for transferring data from a shadow memory to a logical memory, a means for performing logical decoding of the logical memory in parallel with a change operation to the shadow memory, and a means for performing logical decoding of the shadow memory in parallel with the data transfer. A programmable controller characterized by being equipped with a logic decoding section that can perform the following functions.