JPS6214528A - Intermediate frequency amplifying circuit with electric field intensity detecting function - Google Patents

Abstract

PURPOSE:To improve the linearity of the log characteristic of a DC output to an input voltage by connecting mutually two double balanced differential amplifiers different in gain in parallel to form a double balanced differential amplifier constituting a full-wave rectifier in each stage. CONSTITUTION:Transistors TRs Q1-Q10 constitute the full-wave rectifier in the first stage, and TRs Q11-Q20 constitute that in the second stage, and TRs Q21-Q30 constitute that in the third stage, and TRs Q31-Q40 constitute that in the fourth stage. An adding circuit ADD adds positive-phase output currents of full-wave rectifiers in the first-fourth stages and smoothes this addition current and outputs the input signal level as a DC voltage VS. If an input signal VIN is increased gradually, double balanced differential amplifiers are saturated in order from the last stage. If emitter resistances R3, R4,... R15, R16, and RE (R3=R4=...=R15=R16=RE) are provided and the value of the resistance RE is selected properly, the linearity of the log characteristic of the voltage VS to the voltage VIN is improved. Thus, the electric field detecting function which has a high saturation input signal level and a wide dynamic range is provided.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to the structure of an intermediate frequency amplifier of a receiver, and particularly to a method of detecting a received electric field of the receiver.

Prior art Prior art to the present invention includes 1, for example, Microelectronics and Reliability, No. 14, No. 3.
11! Pages 366 to 366, published by Pergamon Press in 2019 (Microelectronics and R
e1ability.

vol, /A, pp, 31Is ~ 3bb, Pe
rgamon Press,/Dekuku) exists. The circuit configuration shown in FIG. 3, which is disclosed as a conventional example of the present invention, is a part of an IC called OA 3019 shown in the above-mentioned document. Other parts related to Figure 3 of this specification in 1c in the above document are shown in Fig.
/ s F i g 2- F i g 10 w
Fig”, Fig/co and its explanatory text.

Conventionally, the configuration of an intermediate frequency amplifier with an electric field detection function is as follows:
As shown in Figure 3, a multi-stage amplifier (transistor Q
The output of each stage is connected to a capacitor (Cg, Cde, Cio), and the rectified n11IL flow waveforms of each stage were added to output electric field level information.

Problems to be Solved by the Invention In the above-mentioned conventional intermediate frequency amplifier having an electric field detection function, AC signals are rectified using diodes (Q28', Q29').

Q30';Q32',Q33',Q34'; Q
35', Q36', Q37'), the drawback is that the temperature characteristics are poor and the circuit becomes complicated to compensate for the constancy characteristics.

In addition, since the rectifier is a half-wave rectification method using diodes as mentioned above, each capacitor (Cr, Cq
, Cto), and lowering the intermediate frequency requires a larger capacitor. Therefore, when the above-mentioned capacitor is built into an IC, the chip size becomes large. Furthermore, in order to reduce the size of the balance by externally attaching a capacitor, an external capacitor is required for each stage, and external capacitors increase the number of terminals for capacitors, which is disadvantageous for IC implementation. Furthermore, since the rectifier uses diodes as mentioned above, it can only detect signal input up to the point where the first stage differential amplifier consisting of transistors Qt1 to ψ is saturated, which increases the dynamic range. Even if the total gain of the differential amplifier was increased by increasing the number of stages in order to achieve this, the maximum input level was determined at the above-mentioned saturation level, and a sufficient dynamic range could not be obtained. On the other hand, in order to reduce the deviation of the input signal detection voltage from the logarithmic characteristic, it is generally necessary to lower the gain per stage of the differential amplifier mentioned above and increase the number of stages, and the number of capacitors required is equal to the number of stages of the rectifier. There were drawbacks.

The present invention has been made in view of the above-mentioned conventional circumstances, and
SUMMARY OF THE INVENTION It is therefore an object of the present invention to overcome the above-mentioned disadvantages inherent in the prior art.

Means for Solving the Problems In order to achieve the above object, an intermediate frequency amplifier circuit with a field strength detection function according to the present invention uses a multi-stage double-wave rectifier consisting of a differential amplifier and a single-balanced differential amplifier. This is an intermediate frequency amplification circuit obtained by cascading a double-balanced differential amplifier in each stage, which consists of two differential amplifiers connected in parallel, each with a different gain. are doing.

EXAMPLE Next, a preferred embodiment of the present invention will be specifically explained with reference to the drawings.

The π7 diagram is a circuit configuration diagram illustrating a high-stage configuration as an example of an embodiment of the present invention.

Transistors Q/~Qto constitute a first-stage double-wave S rectifier, transistors Q//~Q:lD constitute a first-stage double-wave rectifier, and transistors Qcot -Q 3° are A third-stage double-wave rectifier is configured, and transistors Q, ? /
-Q tm constitutes the second stage double-wave rectifier.

The adder circuit ADD adds the positive phase output currents from the first-stage double-wave rectifier to the second-stage double-wave rectifier, and adds this addition 'jI? The current is smoothed by resistor R/7 and co/den fC/, and the input signal level is output as DC voltage v8.

Now, when the IF input signal M and N gradually increases.

The signal is saturated from the 21L balanced differential amplifier in the succeeding stage.

Here, R,y=RdarR7-Rt=R//-R
/CorR1r=Rir=Rg and 2, then each:1. are connected in parallel to form a balanced differential amplifier.
The small signal gain of the two differential amplifiers is shown as:

However, VT = kT/q ・・・・・・・・・
・・・・・・・・・・・・・・・・・・ (C) Regarding the first-stage double-balanced differential amplifier, the gain gN of the differential amplifier with current source I2/ is gll = I2'/ko VT ・・・・・・・・・・・・
・・・・・・・・・Song・(ko) The gain g1□ of a differential amplifier with current source 5 is g12=Ec3/(2vT+
RE engineering 3)...Song...4 (3).

For the second stage single balanced differential amplifier, the gain g21 of the differential amplifier with current source 2 is g21 =
a X2/2VT... Song... Song...
...4 (lI) The gain g22 of the differential amplifier with current source 5 is g22 = I! /(JVT+
REI3) - - - - - - (h).

For the third stage single balanced differential amplifier, the gain g31 of the differential amplifier with current source 2 is g, , -I
2/, 2VT ・・・・・・・・・・・・・・
(6) The gain gs2 of the differential amplifier with current source 3 is g, 2 = Is/f u v'r + RE Is
) ・・・・・・・・・・・・ (7).

λ double balanced type difference hJJjJ 1i of the first stage 1! Regarding the vessel, Current Source I2? difference vJ with amplifier gain g4
1 is g41 = engineering 2/yu VT ・・・・・・・・・
...
) ,,・・・・(It can be expressed as vl.

Here, if I2 = I2' = I3 = I3', gll = g21 '' g31 - g41 °
°°°°゛°°°°°° (10) g12 ” g22-
g32 ”” g42 °°°゛°°゛°゛-(//
). Naka, 8g The gains of the differential amplifiers from the first stage to the Hiro stage are all g. shall be.

(10) The emitter resistance RE can be set so that g, 1=f correction・g 12 ----= (/2) in the formula (//). In this case, the characteristic of the average output sink current Is in FIG.
It becomes a curve as shown in 18 in the figure, with Vgo (aB ) and a series of outflow outputs of 1! It can be seen that the relationship between the flow characteristics is almost linear. However, (, o (dB) = 2011og go...
......-(/,?) This will be explained in detail below.

8g - The curve / in the diagram is for transistor Q in the circuit diagram of Figure 1.
71 Qt IQ/? , qlt+ Q2q, QcolQ,
7ri.

This is the characteristic when q differential amplifiers composed of Q3g are removed, and it is composed only of differential amplifiers with a gain shown by equation 74.

The dihedral line in Figure 2 is the transistor Q in the circuit diagram of Figure 1.
9, Q10+ Q/9. Q 20 +
Q29. This is the characteristic when the two differential amplifiers consisting of QJO + Q39°Qm are removed,
This is a case in which only one differential amplifier with a gain shown by equation (10) is used.

Here, as can be seen from the equation (/), the size of the emitter resistance RE is selected so that the sensitivity of the rectifier for curve () is lowered by o/2aB compared to the case for curve (/).

In the following, the V-NfaB) vs. Is% characteristics in Figure 2 will be referred to as a log characteristic curve.

The curves / and 2 in FIG. 2 are curves that undulate in a concave and convex manner, and the logarithmic characteristic is approximated. In general, when a logarithmic characteristic curve is approximated by a polygonal line using a linear amplifier, a deviation from the logarithmic characteristic always occurs as shown in the curves 2 and 2 in FIG.

According to this logarithmic characteristic, in the circuit diagram of FIG. 1, the differential transistor pair constituting the single-balanced differential amplifier at each stage, that is, the transistor Q? , Qt and transistor Qde, Q10I transistor Qn, Qn and transistor Q/? , Q20+ transistor Q core, Q core and transistor Q29. Q30+ Transistor Q, 77, Q
3t and the transistors QJv and Qu have the same phase, so the characteristics of the output sink current Is of the field strength detection function shown in the circuit diagram of Fig. 1 are obtained by adding the curve / and the curve U shown in Fig. 2. Becomes a characteristic. Here, since the emitter resistor RE is selected so that the convex part of the curve / and the convex part of the curve - occur at input levels that are shifted by GO (dB) from each other, the undulating convexities cancel each other out and the convexities are straight. It can be seen that the characteristics are improved.

As described in detail, according to the present invention, in an intermediate frequency amplifier circuit obtained by cascading a differential amplifier and a single balanced differential amplifier in multiple stages, two wave rectifiers are configured in each stage. By mutually connecting single balanced differential amplifiers having different gains in parallel, it is possible to improve the linearity of the log characteristic of the DC output with respect to the input voltage.

In this circuit configuration, since the positive-phase output current waveforms of the single-balanced differential amplifiers are in phase, addition is possible without using a capacitor to convert to direct current.

According to the present invention, it is also possible to obtain a logarithmic characteristic with linearity equivalent to that of an intermediate frequency amplifier having an electric field detection function, which is composed of an xn stage differential amplifier and a con n stage rectifier. Furthermore, the differential pair configuration also improves temperature characteristics.

As described above, according to the present invention, the intermediate frequency has an electric field detection function that operates from a low intermediate frequency, has excellent temperature characteristics of the electric field detection voltage, has a wide dynamic range with a high saturation input signal level, and has significantly improved linearity. The amplifier circuit can be realized with a relatively small circuit scale, and the capacitor can be omitted, which is a great advantage.

[Brief explanation of the drawing]

FIG. 1 is a circuit configuration diagram when an embodiment of the present invention is constructed in two stages. FIG. 2 shows the characteristics of the sink current generator 8 for DC voltage output in the circuit diagram of FIG. 1, and the curve l in FIG. 1 corresponds to the transistor Q? . Q t s Q/7. Q/za + Q core + Q core + Q j ri is the characteristic when Q3g is removed, and the - curve is the transistor Q? ,Q10 IQ/de ,Qkoo,Q
Kota, Q 3o I Q 3q. Q invasion and resistance R,? , RII+R, Rg HRii, R
/co-R/s, which is the characteristic when Rtb is removed. FIG. 3 shows an example of a conventional circuit consisting of a three-stage differential amplifier circuit. Figure D is the output of S-METEROUT in Figure 3.
□The voltage is shown relative to the IF large input signal level V (aB).

Claims (1)

[Claims] There are n stages of differential amplifiers, and an intermediate frequency amplifier is configured in which the output of each differential amplifier is sequentially connected to the input of the next stage, and the output signal of each stage of the differential amplifier is
Corresponding to the differential amplifiers, there are n double-balanced differential amplifiers whose second inputs are the input signals in each stage of the differential amplifier, and the n double-balanced differential In an intermediate frequency amplifier configured with a circuit that adds the positive-sequence output currents of respective positive-sequence output currents of dynamic amplifiers, the differential amplifier to which the second input of the double-balanced differential amplifier is applied is connected to the differential amplifier through an emitter resistor. An intermediate with an electric field strength detection function, characterized in that a differential pair in which each emitter is connected in common and a differential pair in which each emitter is connected in common without an emitter resistor are connected in parallel to each other. Frequency amplification circuit.