JPS6214247A - Cash sub-system - Google Patents

Abstract

PURPOSE:To aim at high speed accessing at the time of the cash hitting by judging the data renewal in accordance with the frequency of the WRITE access to the block on the cash memory. CONSTITUTION:At a cash memory 330, plural blocks accessed previously on a direct access storage device (DASD) 35 are stored. A WRITE access frequency counting part 31, when the cash hitting of the WRITE access is detected by an entry table retrieving part 30, the WRITE access frequency is renewed, and stores it to a register 313. The maximum allowable value of the WRITE frequency is loaded to a register 312, and the WRITE access frequency value after renewal is set to a register 311 and the size is compared. When the access frequency after the renewal is not large, '1' is outputted to a signal line 41.

Description

Detailed Description of the Invention [Technical Field to which the Invention Pertains] The present invention relates to a cache subsystem having a cacher memory between the main storage device and the external storage device in a computer system including a main storage device and a plurality of external storage devices. Regarding.

[Conventional technology]

The cache subsystem can achieve faster access times by obtaining the desired record from the cache memory without accessing the external storage device one by one. However, the consistency of data between the external storage device and the cache memory need to be guaranteed. Conventionally, a store-through method and a store-in method have been known as methods for guaranteeing data consistency between the external storage device and the cache memory.

In the store-in method, in response to a WRITE access from a host device, if the corresponding record exists on the cache memory (cache hit), only the record on the cache memory is updated, and the data block on the cache memory is transferred to external storage. When destaging to a device, the block containing the updated code is destaged to an external storage device, thereby updating the corresponding record on the external storage device. This method uses WRITE
This has the advantage that high speed is guaranteed even if access is interrupted. However, since the external storage device is updated at a later date, data recovery processing in the event of a cache memory failure becomes complicated, and its uses are limited. This store-in method is applicable to rIBM3880-
Introduction to 11-inch magnetic disk controller (Ga42-0060
) J, etc.

The store-through method is a method in which, in response to a WRITE access from a host device, even if the corresponding record exists on the cache memory, the corresponding record on the cache memory is updated and the corresponding record on the external storage device is updated at the same time. be. In this method, even when a WRITE access is cached, the response performance is greatly affected by the performance of the external storage device, and while the high speed of the cache is not fully utilized, the integrity of the data on the external storage device is Because of this guarantee, it is widely used in database systems where reliability is important. This one store method is described in, for example, rIBM 3880-13 Type Magnetic Disk Controller Introduction (Ga42-0062) J.

On the other hand, for example, in bank deposit processing and databases, there are processes in which the pattern of accessing records in one transaction is constant and the contents can be predicted in advance. An example of such routine processing is shown in FIG. In this example, 1l-IN indicates a record, and 2 indicates a block containing multiple records. A block is, for example, one track when the external storage device is a disk device. Since this type of data requires high reliability, a store-only cache subsystem is usually applied. However, as shown in this example,
If multiple WRITE accesses are included, WRIT
Even if the E access hits (in this example, the block has already been staged on the cache memory due to the READ access, a hit is expected with a high probability), the disk drive is updated for each WRITE access. An update will be made. In particular, for files with a large proportion of WRITE accesses, there is a problem in that little improvement in response performance can be expected compared to the case where there is no cache memory.

[Purpose of the invention]

The purpose of the present invention is to perform the above-mentioned periodic processing and to
For files with a large proportion of TE accesses,
WRI'TE without compromising data integrity
To provide a cache subsystem that guarantees high speed even when access is cached.

[Characteristics of the invention and differences from the prior art]

The present invention provides a cache subsystem having a cache memory between a main storage device and an external storage device.
A means for counting the number of E accesses, a means for storing a maximum allowable number of WRITE accesses to the block, and a means for determining whether to update data on the external storage device based on the number of WRITE accesses to the block. It is characterized by This makes it possible to achieve faster WRITE access for data that emphasizes processing performance, and the conventional storage method for data that emphasizes reliability, in the same system, creating a flexible cache subsystem. can be provided. This is a fundamentally different point from conventional technology.

〔Example〕

FIG. 1 is a block diagram of an embodiment of the present invention. This cache subsystem includes an entry table search unit 30, a WRI
It consists of a TE access count section 31, a microcontroller section 32, a cache memory section 33, a DASD interface control section 34, and an external storage device 35. The external storage bag W35 is a direct access storage device (DASD: Direct Access Storage Device) such as a magnetic disk device or a magnetic drum device.
t Access Sh.

device).

The cache memory access unit 33 is the cache memory 3
30, and the cache memory 330 has a DAS
A plurality of previously accessed blocks on D35 are stored. The entry table search unit 30 has an entry table 300. This entry table 300
is the DA corresponding to the block of the cache memory 330.
Entry information such as SD block address is registered. FIG. 2 shows an example of the structure of the entry table 300.
In addition to the entry information of the corresponding block in the cache memory 330, for example, the DASD updated flag 301;
It has an area for storing the number of WRl and TE accesses of 02, and an area of 303 for storing the maximum allowable number of WRITE accesses to the block. Area 302
is updated every time a WRITE access is made to the block. The contents of area 303 will be changed if READ access is not cached (READ M
Information for the block may be loaded from the DASD 35 during staging triggered by the ISS, or may be changed by instructions from a higher-level device such as software. When loaded from DASD35,
For example, data previously recorded at the gap portion or the beginning of a block on the DASD 35 is loaded. On the other hand, when software or the like is changed by a command from a host device, W is changed under the control of the microcontroller section 32.
The RITE access count section 31 can be set arbitrarily. In addition to this, it is easy to think of a method for implementing a means for arbitrarily setting the maximum allowable number of WRITE accesses to the block, but this is not stipulated in 2\.

The WRITE access count unit 31 is a computing unit 310
, registers 311, 312, and 313. The counting unit 31 receives, for example, a cache hit (WRITE access) of a WRITE access by the entry table search unit 30.
HIT) is detected, the entry table 300
A copy of area 302 of the corresponding block is stored in register 3.
11 to update the number of WRITE accesses, and store the result in the register 313. Furthermore, the contents of the area 303 that stores the maximum allowable number of WRITE accesses to the block in the entry table 300 are stored in the register 3.
12, the updated number of WRITE accesses stored in the register 313 is set in the register 311, the magnitudes of the two are compared, and the result is output to the signal line 41. Further, when the update process is finished, the contents of the register 311 are registered in the entry table 300 again. The signal line 41 shows the updated number of WRITE accesses in the entry table 3.
Maximum allowable WRITE for the corresponding block in 00
If it is not smaller than the contents of the area 303 that stores the number of accesses, it becomes '1'.

FIG. 3 is a flowchart showing the operation of this cache subsystem.

First, DEA is sent to this cache subsystem from the host device.
A case where D access is issued will be explained. REA
When a D access is issued, the entry table search unit 30 searches the entry table 300 and notifies the microcontroller unit 32 of the search results. In the case of cache access, the cache memory access unit 33 accesses the cache memory 3 under the control of the microcontroller unit 32.
30, reads the data of the corresponding block, and sends it to the host device. If you do not do so,
The microcontroller unit 32 controls the DASD interface control unit 34 to access the DASD 35 and read out blocks containing the relevant data from the DASD 35. At the same time, it is checked whether there is an empty area in the cache memory 330, and if there is an empty area, the block read from the DASD 35 is staged into the area, and if there is no empty area, one block is transferred to the DASD 35 using a predetermined algorithm. An empty area is created by staging, and blocks from the DASD 35 are staged to the area. Then, the corresponding block portion of the entry table 300 is initialized.

This initial setting data includes the contents shown in FIG. 2 in addition to the entry information of the cache memory 330.

Next, a case where a WRITE access is issued from a host device will be described. The entry table search section 30 searches the entry table 300 and notifies the microcontroller section 32 of the search results. If not, the microcontroller section 32
Controlling the interface control unit 34 directly to the DASD 35
access and update the data on the DASD 35. If it is hit, the microcontroller section 32
Under the control of
10 is incremented by 1 and the result is passed through register 313 and set in register 311 again. Next, the entry table 30
The contents of the area 303 indicating the maximum allowable number of WRITE accesses of the corresponding block at 0 are loaded into the register 312 and compared by the arithmetic unit 310. The signal line 41 is 311<
312, that is, when the updated number of WRITE accesses is smaller than the maximum allowable number of WRITE accesses for the block, 1101g, and when 311≦312, that is,
When the number of WRITE accesses is equal to or greater than the maximum allowable number of WRITE accesses, LL I I+ occurs. The microcontroller unit 312 has a signal line 41 connected to the LL OI
In the case of +, the cache memory access unit 33 is controlled to update the data in the corresponding block of the cache memory 330, and the contents of the register 311 are updated to the entry table 3.
Return to 00. When the signal line 41 is "1", the cache memory access unit 33 and the DASD interface control unit 34 are controlled to update the data in the corresponding block of the cache memory 330 and to transfer the block to the DASD 3.
5 Hede staging. Then, the entry table search section 3 is controlled to initialize the corresponding block section of the entry table 300.

That is, at the time of WRITE access, W to the corresponding block is
For WR and ITE HIT accesses in which the number of RITE accesses does not reach the maximum allowable number of WRITE accesses, the DASD 35 is not updated and the accesses are processed only in the cache memory 330, so high-speed access is guaranteed. In addition, when the number of 1l-WRITE accesses reaches the maximum allowable number of WRITE accesses, the time required to destage the corresponding block is also reduced by seek operations and blocks that contain multiple updated records at once. It is possible to eliminate rotational waiting time, and compared to the conventional store-through type, it is possible to improve performance such as faster response and improved DASD throughput. Furthermore, if the maximum allowable number of WRITE accesses is set to 0 or 1, the signal line 41 will always be 1, making it possible to implement the conventional store-through method. This function allows the conventional store-through method to be applied to blocks where reliability is particularly important.

(Effects of the Invention) As is clear from the above description, the present invention provides the following advantages.

(1) By using the present invention for regular services where the number of WRITE accesses can be predicted in advance,
WRITE HIT compared to the conventional store-through one-way system
Faster access can be achieved. In addition, blocks containing multiple updated records are updated all at once, reducing seek operations and rotational waiting time.
SD throughput can be improved.

(2) For data where reliability is particularly important, it is also possible to implement the conventional store-through method by, for example, setting the maximum allowable number of WRITE accesses to 0 or 1 under software control. .

(3) Recovery control unit (for example, transaction)
The maximum number of WRITE accesses expected within the allowable WR
By matching the number of ITE accesses, the range of influence in the event of a cache failure can be minimized.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a diagram showing an example of the configuration of a cache entry table according to the present invention, FIG. 3 is a flowchart for explaining the operation of FIG. 1, and FIG. is a diagram showing an example of a routine transaction. 30... Entry table search unit, 300... Entry table, 301... Updated flag, 302... WRITE access count storage area, 303... Maximum allowable WRITE access count storage area, 31... WRI TE access count Karen 8 parts 32... Microcontroller section, 33... Cache memory access section,
330... Cache memory, 34... External storage interface control unit, 35... External storage device.

Claims (1)

[Claims] (1) A cache subsystem that includes a cache memory between a main storage device and an external storage device, stores some data blocks of the external storage device on the cache memory, and obtains target data from the cache memory, means for counting the number of write accesses to a predetermined data block on the cache memory;
means for arbitrarily storing a maximum allowable number of write accesses to the data block; and when a write access request is made to the data block, the number of write accesses of the data block is compared with the maximum allowable number of write accesses, and the corresponding data block of the external storage device is stored. A cache subsystem comprising a means for determining whether or not to update the cache subsystem.