JPS62141720A - Semiconductor-insulator films lamination structure - Google Patents
Semiconductor-insulator films lamination structureInfo
- Publication number
- JPS62141720A JPS62141720A JP28388285A JP28388285A JPS62141720A JP S62141720 A JPS62141720 A JP S62141720A JP 28388285 A JP28388285 A JP 28388285A JP 28388285 A JP28388285 A JP 28388285A JP S62141720 A JPS62141720 A JP S62141720A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor
- nitriding
- iii
- crystal
- gallium
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Abstract
Description
【発明の詳細な説明】
(産業上の利用分野)
本発明は、半導体・絶縁体膜よシなる積層構造に関する
。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a laminated structure of semiconductor and insulator films.
(従来の技術)
従来、半導体・絶縁体膜積層構造、ビームアニール技術
を用いた5OI(セミコンダクタ オンインシュレ“−
タ: Sem1conductor on In5ul
ator)構造として、シリコンを対象に作成されて来
た。この際、絶縁体膜が単結晶であればSOI構造を、
よシ容易に作成することが可能になる。シリコンの場合
ではマグネシアスピネル(Mg0−AII、O,)や弗
化カルシウム(CaF、 )を基板上にエピタキシャル
成長させ、その上に単結晶シリコンを成長させている。(Conventional technology) Conventionally, 5OI (semiconductor on-in-insulator) using a semiconductor/insulator film laminated structure and beam annealing technology has been developed.
Ta: Sem1conductor on In5ul
ator) structure has been created for silicon. At this time, if the insulator film is a single crystal, the SOI structure is
This makes it easy to create. In the case of silicon, magnesia spinel (Mg0-AII, O,) or calcium fluoride (CaF, ) is epitaxially grown on a substrate, and single crystal silicon is grown on it.
(発明が解決しようとする問題点)
しかし、マグネシアスピネルのエピタキシャル成長温度
は約900℃以上であシ、この温度では■−V化合物半
導体の表面が熱損傷を受ける。また弗化物の熱膨張率は
約20X 10” K”’で、シリコンの3xlQ−’
x−’ 、ガリウムヒ素の6X10−’に−”との差が
大きく半導体と弗化物の界面に熱歪が生じ易い。本発明
の目的は熱損傷、熱歪を避けて形成することが可能で、
I−V化合物半導体をも用いることのできる半導体・絶
縁体膜積層構造を提供することにある。(Problems to be Solved by the Invention) However, the epitaxial growth temperature of magnesia spinel is approximately 900° C. or higher, and at this temperature, the surface of the -V compound semiconductor is thermally damaged. The coefficient of thermal expansion of fluoride is approximately 20X 10"K"', which is 3xlQ-' of silicon.
x-', gallium arsenide's 6 ,
It is an object of the present invention to provide a semiconductor/insulator film laminated structure that can also use an IV compound semiconductor.
(問題点を解決するための手段)
本発明に於いては、半導体上に窒化アルミニウム結晶、
或いは窒化アルミニウムと窒化ガリウムの混晶を絶縁体
膜として用いるものとする。その成長方法は基板半導体
によって適宜選択する。例えば、シリコン基板上に窒化
アルミニウムを成長させる場合にはトリメチルアルミニ
ウムとアンモニアを原料にして900℃程度の温度で減
圧MOC■を行なえば良い。また、I−V化合物半導体
上に窒化アルミニウムを成長させる場合には、トリメチ
ルアルミニウムとアンモニアを原料にECR(電子サイ
クロトロン共鳴)プラズマを用いて成長させるか、或い
はトリメチルアルミニウムとヒドラジンを原料にして4
001::以上の温度に於いてMOCVDを行なっても
良い。(Means for solving the problem) In the present invention, aluminum nitride crystal,
Alternatively, a mixed crystal of aluminum nitride and gallium nitride may be used as the insulating film. The growth method is appropriately selected depending on the substrate semiconductor. For example, when growing aluminum nitride on a silicon substrate, low pressure MOC 2 may be performed at a temperature of about 900° C. using trimethylaluminum and ammonia as raw materials. In addition, when growing aluminum nitride on an IV compound semiconductor, it can be grown using ECR (electron cyclotron resonance) plasma using trimethylaluminum and ammonia as raw materials, or it can be grown using trimethylaluminum and hydrazine as raw materials.
MOCVD may be performed at a temperature of 001:: or higher.
窒化アルミニウムと窒化ガリウムの混晶を用いる場合、
混晶中に窒化アルミニウムが約40g6以土倉まれる様
にする。窒化アルミニウムがこれよシ少ないと混晶の絶
縁性は十分でない。When using a mixed crystal of aluminum nitride and gallium nitride,
Approximately 40 g of aluminum nitride is contained in the mixed crystal. If the amount of aluminum nitride is less than this, the insulating properties of the mixed crystal will not be sufficient.
(作用)
窒化アルミニウム、窒化ガリウムは熱膨張係数が約5X
10−’K”であシ、半導体の熱膨張係数との差が従来
の材料よりも小さく、熱歪を減少させることかできる。(Function) The thermal expansion coefficient of aluminum nitride and gallium nitride is approximately 5X.
10-'K'' has a smaller difference in thermal expansion coefficient from that of semiconductors than conventional materials, making it possible to reduce thermal strain.
また厘−■化合物半導体の表面安定化に窒素とI族元素
との結合が効果を持つことから、上記材料系が1−V化
合物半導体表面の損傷低減に役立つものと期待される。Furthermore, since the bond between nitrogen and Group I elements has an effect on stabilizing the surface of a 1-V compound semiconductor, it is expected that the above material system will be useful in reducing damage to the surface of a 1-V compound semiconductor.
(実施例)
本実施例ではI−V化合物半導体の一つであるガリウム
ヒ素(GaA+s )基板上に絶縁体膜を形成させた後
、基板と同じG a A sをその上に成長させた。(Example) In this example, an insulating film was formed on a gallium arsenide (GaA+s) substrate, which is one of the IV compound semiconductors, and then the same GaAs as the substrate was grown thereon.
GaAs(111)ウェハを化学的にエツチングする。Chemically etch a GaAs (111) wafer.
トリメチルガリウム(TMG)とアルシン(AsHa)
を原料にしてMOCVD法によシウェハ上に約1000
AGaAsを成長させる。これを基板として続けてトリ
メチルアルミニウム(TMA)、ヒドラジy(N、H,
)を原料にして、AJN 0M0CVDを行なう。この
時T MA 、N* H4温度は20℃、バブル水素流
量はそれぞれ毎分5α、200=6.基板温度は600
℃、総流量は毎分8m圧力は80Torrに設定し、1
0分間で厚さ約50OAのAIN膜を得た。更に続けて
TMG 、 A s H,を原料にしてMOCVD法に
よりGaAsを成長させることができた。Trimethyl gallium (TMG) and arsine (AsHa)
Approximately 1,000 sheets are deposited on a wafer using the MOCVD method using
Grow AGaAs. Using this as a substrate, trimethylaluminum (TMA), hydrazine (N, H,
) as a raw material, perform AJN 0M0CVD. At this time, the T MA and N*H4 temperatures were 20°C, and the bubble hydrogen flow rate was 5α/min, 200=6. The substrate temperature is 600
℃, the total flow rate was set to 8 m/min, and the pressure was set to 80 Torr.
An AIN film with a thickness of about 50 OA was obtained in 0 minutes. Furthermore, GaAs could be grown by MOCVD using TMG and AsH as raw materials.
窒化アルミニウム、窒化ガリウムの混晶作成にはTMG
、 TMA 、N、H,を原料にした。TMG、TM
A。TMG is used to create mixed crystals of aluminum nitride and gallium nitride.
, TMA, N, H, were used as raw materials. TMG, TM
A.
N、H4温度はそれぞれ一12℃、 20℃、 20t
、 バブル水素流量はそれぞれ毎分II:e、 4C
a 、 200ctI。N and H4 temperatures are -12℃, 20℃, and 20t, respectively.
, bubble hydrogen flow rate is II:e, 4C per minute, respectively.
a, 200ctI.
基板温度は600℃、総流量は毎分8g圧力は8゜T
orr に設定し、10分間で約500XのA10.。The substrate temperature is 600℃, the total flow rate is 8g/min, and the pressure is 8℃.
orr for about 500X for 10 minutes. .
G A44 N、、、を作成した。G A44 N... was created.
(発明の効果)
本発明によれば、熱損傷、熱歪を避けた半導体・絶縁体
膜積層構造が実現され、[−V化合物半導体をも積層化
することが可能になる。(Effects of the Invention) According to the present invention, a stacked structure of semiconductor/insulator films that avoids thermal damage and thermal distortion is realized, and it becomes possible to stack [-V compound semiconductors as well.
Claims (1)
構造に於いて、絶縁体膜として窒化アルミニウム結晶、
或いは窒化アルミニウム・窒化ガリウム混晶を用いるこ
とを特徴とする半導体・絶縁体膜積層構造。In a stacked structure in which an insulating film is layered on a semiconductor, and a semiconductor is further layered on top of that, aluminum nitride crystal, aluminum nitride crystal, etc. are used as the insulating film.
Alternatively, a semiconductor/insulator film laminated structure characterized by using aluminum nitride/gallium nitride mixed crystal.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP60283882A JPH0666263B2 (en) | 1985-12-16 | 1985-12-16 | III-V compound semiconductor / insulator / III-V compound semiconductor laminated structure |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP60283882A JPH0666263B2 (en) | 1985-12-16 | 1985-12-16 | III-V compound semiconductor / insulator / III-V compound semiconductor laminated structure |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS62141720A true JPS62141720A (en) | 1987-06-25 |
JPH0666263B2 JPH0666263B2 (en) | 1994-08-24 |
Family
ID=17671397
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP60283882A Expired - Lifetime JPH0666263B2 (en) | 1985-12-16 | 1985-12-16 | III-V compound semiconductor / insulator / III-V compound semiconductor laminated structure |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0666263B2 (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0512565A (en) * | 1991-07-08 | 1993-01-22 | Sanyo Electric Co Ltd | Electronic cash register |
EP1179842A2 (en) * | 1992-01-31 | 2002-02-13 | Canon Kabushiki Kaisha | Semiconductor substrate and method for preparing same |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6027699A (en) * | 1983-07-22 | 1985-02-12 | Agency Of Ind Science & Technol | Preparation of single crystal film of silicon carbide |
JPS61159724A (en) * | 1985-01-07 | 1986-07-19 | Semiconductor Energy Lab Co Ltd | Thin-film forming method |
JPS62119939A (en) * | 1985-11-19 | 1987-06-01 | Sharp Corp | Insulating substrate for semiconductor |
-
1985
- 1985-12-16 JP JP60283882A patent/JPH0666263B2/en not_active Expired - Lifetime
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6027699A (en) * | 1983-07-22 | 1985-02-12 | Agency Of Ind Science & Technol | Preparation of single crystal film of silicon carbide |
JPS61159724A (en) * | 1985-01-07 | 1986-07-19 | Semiconductor Energy Lab Co Ltd | Thin-film forming method |
JPS62119939A (en) * | 1985-11-19 | 1987-06-01 | Sharp Corp | Insulating substrate for semiconductor |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0512565A (en) * | 1991-07-08 | 1993-01-22 | Sanyo Electric Co Ltd | Electronic cash register |
EP1179842A2 (en) * | 1992-01-31 | 2002-02-13 | Canon Kabushiki Kaisha | Semiconductor substrate and method for preparing same |
Also Published As
Publication number | Publication date |
---|---|
JPH0666263B2 (en) | 1994-08-24 |
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