JPS62134890A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To eliminate the need for a word line by writing and reading data in and out of a selected memory through a power source potential line and an earth power line common to memory cells in a word direction. CONSTITUTION:When a memory cell M is unselected, the power source potential line for memory cells which is common to cells M in the word direction is held at a source potential VDD1 of 5V, etc., through an address decoder 13 and a voltage generating circuit 14 and the grounding potential line is held at the ground potential VSS1 of OV, etc., from a fixed potential of 2.5V, etc. Therefore, a base is controlled through a bit line B and the inversion of B whcih are precharged to 2.5V, etc., by a precharging circuit 15 and transistors 11 and 12 forming a transfer gate turn on and off corresponding to the H and L sides of the cell M, whose storage contents are read out. Writing operation is performed similarly and the need for word lines is eliminated to reduce the chip area of a memory and lower the precharging voltage to about a half as high as the source voltage, thereby reducing current consumption and speeding up readout operation.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention mainly relates to a semiconductor memory device (hereinafter referred to as memory) using a metal-insulating film-semiconductor (hereinafter referred to as MIS) transistor.

BACKGROUND OF THE INVENTION FIG. 4 shows a conventional example of the main parts of a CMO8 type static RAM including memory cells. M is a memory cell, and the data of the memory cell is transmitted to the bit lines B and H via transfer gates 1-51 and 52, and conversely, the data write operation to the memory cell M is also performed by selecting the word line W. ”: is carried out.

53 is an address decoder, 54 is a word line drive circuit, 5
5 is a precharge circuit, ■DD is a power supply potential line, vss
is a ground potential line, which is commonly connected to all memories, has the same potential level between memory cells, and is efficiently arranged and connected on the memory cell pattern. To read data from a memory cell, the bit line is usually precharged to a fixed potential, then the word line selected by the address decoder is turned on by the word line drive circuit, and the transfer gates 51 and 52 are turned on.
It enters the N state and data appears as a potential difference on the bit line. Data writing is performed in almost the same way.

FIG. 5 shows the main part of a conventional 2-port RAM including memory cells. The memory cell M is composed of two N-channel enhancement type MOS transistors 67 and 68 and two N-channel depletion type MOS transistors 5.66, and transfer gates 61 and 6.
2, 63, and 64 are connected to each word line 71-73. "A port l-, B port can read independently from two ports": A port read word line 7
1 and a B boat read word line 72, and a read bit line 81 corresponding to each read word line,
Has 82. When reading data from the A port, the A port read word line 71 is driven to put the data in the memory cell M on the A port read bit line 81,
It is detected by the sense amplifier 90 and output to the internal bus 91 of A.

On the other hand, the same applies to reading from the B port. In the case of data writing, the drive circuit 100 drives the write bit line 83 and the write word line 73 is used to access the memory cell M.

Problems that the invention attempts to solve In this way, it is unavoidable that a 2-bot RAM has multiple U15, word lines, bit lines, etc., and the area of the memory cell is larger than that of a normal state-of-the-art RAM. (e.g. H, Kadota).

e't al [A new register f
ile 5 structure for the high
-speed m1croprocessor, JEEE Journal of Solid State Circuits (IEEE J, 5solid-8
tate Circuits) 5C-17, p892
~897 (1982)).

The present invention aims to eliminate the word line in a semiconductor memory device.
By reducing the potential amplitude when writing and reading data, it is possible to reduce power consumption and speed up reading.

Means for Solving the Problems The present invention provides a semiconductor memory device, particularly a memory cell having a power supply potential and a ground potential, in which a 5 Be/' bit line is conventionally connected to the gate of a transfer gate connecting a bit line and a memory cell. The gate is electrically connected to the bit line.The power supply potential and ground potential of the memory cell are connected between the memory cells arranged in the conventional word line direction. The power supply potential and the ground potential are connected in common only for the memory cells, and the power supply potential line and the ground potential line are formed corresponding to the conventional word line of each memory cell.

The power supply potential line and the ground potential line are set at a predetermined fixed potential by a voltage generating circuit in correspondence with a word corresponding to a desired selected address, and data reading and writing operations are performed.

Effect of the Invention The present invention makes it possible to eliminate the conventional word line in a memory cell by the above-mentioned means, and it is possible to reduce the portion occupied by the word line in the memory cell. Area reduction can be achieved more effectively in memory cells and the like that require a plurality of word lines. In addition, when reading data from memory cells, the precharge level of the bit line is set near the level of % of the power supply potential, which reduces power consumption.
Moreover, the data High ("H") level is the precharge level and the Low ("L") level is connected to the M7M.

Since data is read at a fixed potential level near the current level, it is possible to read data at high speed by reducing the logic amplitude. On the other hand, when writing data, the potential difference between the power supply potential and the ground potential is set to approximately % of the power supply voltage, and the data writing level is set to a level of approximately % of the power supply voltage.
Since L l" is set to a fixed potential near the ground potential, it is possible to reduce the power consumption of the driver during writing.

Embodiment FIG. 1 shows a semiconductor memory device in a first embodiment of the present invention. In FIG. 1, M is a memory cell, and a transistor 11.12iJ:, in the conventional example, it is connected to the word line at the transfer gate between the memory cell and the bit line, but in the embodiment, it is connected to the word line. attitude/
This word fiI is removed and its gate is connected to the bit line.

It is something. 13 is an address decoder, 14 is a voltage generation circuit, 15 is a precharge circuit, vDDl and vssl
are a power supply potential line and a ground potential line commonly connected between memory cells in the word line direction, and a power supply potential line vDD1 and a ground potential line ■s81 connected to the memory cell selected by the address decoder and the potential generation circuit. Data writing/reading operations are performed by setting each of them to a predetermined fixed potential point. At this time, VDDl and v
The power supply potential lines and the ground potential lines that are not selected by the address decoders other than ss1 are each set to a predetermined fixed potential state of 1.

Regarding writing data to and reading data from memory cells, FIG. 2 shows the state of each potential point for explaining the operation of the apparatus of the embodiment of Mizuhiro 1.

First, the read operation will be explained with reference to FIG. The potential of the power supply voltage line vDD1 in the non-selected state is the same power supply voltage vDD (for example, 5■ here) sV as that of the peripheral circuit, and the potential of the ground potential line ■ss is the same as the GND potential of the peripheral circuit ( Normally, it is fixed at 2.5■, which is % times the power supply type rU (1ci5V here), instead of ○■). So the address decoder is 31: ref memory.
When 1 = M is selected, the power supply potential line ■DD1 and the ground potential line ■ss1 connected to it are selected, so that ■DD remains unchanged at 6■, and vss1 becomes 2.
The voltage changes from 6■ to a fixed potential point of Ov or around oV. Assuming that the potential of a single hill-like voltage immediately before the data in the memory cell is selected is "H" at 5V on the bit line B side and 2.5V of "L I+" on the bit line B side, the second As shown in figure (a), the potential on the l Hl'' side does not change by 4 dimensions of 5■,
+1L II side potential 2], vss, changes from 2.5■ to around oV, resulting in an identified potential point near 0V and oV. Therefore, the potential state to be read out from B, 1, B, and BK is that the focus line is set to the power supply voltage ■
Precharging is performed to a potential of 2.5V, which is 5% of the DD (in this case, 5■). Since the potential of Hu is 5■, 0FF9 page is reached, and the potential of bit line B remains unchanged at 2.5 V, and this value becomes "H" data for reading from the bit line.

On the other hand, the transfer gate 12 is at the potential 2 of the bit line B.
．． 6V, the potential of memory cell ``L'' is φ■ from 2.6V
When the bit line B is turned on, the potential of the bit line B decreases rapidly and finally reaches a potential that is higher than the threshold value V7 of the transfer gate 12 (Ov, l:J), resulting in data of "L I+". In this manner, the data read operation of the memory cell is performed.

Next, the data writing operation will be explained with reference to FIG. 2(b). In the non-selected state ■DD1 is 5V, vssl is 2
．． 5V, and in the selected state, unlike the read operation, VDD
Lower l from 5 V to 2.5 V, and lower vssl from 2.5 V to φ■. The reason why DD1 is lowered to 2.5 V is to lower the switching voltage of the flip-flop circuit in the memory cell, which enables faster writing without malfunction. Immediately before the potentials of vDDl and vss1 change due to memory cell selection, ilB and B are in a potential state near 2.5V, which is % times the power supply voltage vDD, and at this time, the cell state is indicated by the box in the figure. Assume that the bit line B side is at 5V, which is H", and the data on the bit line B side is approximately 2.5V, which is L".

Therefore, the write data is inputted to the bit line f3 at oV of I L 1' and "H" of 2.5 V, which is the potential of the bit line BKvDD at 3-ite "?". From this state, the potential of the transformer temporarily drops to around φ■, but since the write voltage is 2.6V, the potential of 11 and 11 is 2.69V.
As the fixed potential point in the vicinity is gradually increased, the potential 6 in the cell state on one pit line B side gradually decreases and is forcibly lowered to φ2 for writing drive.

In this way, the data write operation is completed. Here, we have explained the write operation of inverted data, but as the above results show, each potential of the memory cell and bit line in the non-selected state is
, B are both at a potential of 2.5V which is 11% times the voltage of ■DD, and the data 'H' in the memory cell is around 5V of the power supply voltage ■DD, and the data 'L' is around 5V of the power supply voltage ■DD.
'' becomes the potential of the ■s81 potential line at a fixed potential point near 2.5■.The potential of the data on the read bit line is
Data H'' is the precharge level of the bit line■
In this example, it is 2.5V at the potential point % times DD, and the data “
L'' is the potential obtained by adding vT of the transfer gate to the potential of the ground potential line of the selected memory cell, and in this example, vT■
becomes.

FIG. 3 shows the main parts of a 2-port RAM memory cell according to an embodiment of the present invention. Circuits are omitted. FIG. 4 shows the voltage at each potential point and the results of recognition of data read from the A port and the B port, just to explain the operation of the embodiment shown in FIG. In FIG. 3, B and B are bit lines, and vDDm and "S S m are m, respectively.
A power supply potential line and a ground potential line common to the word of the address, ■
DDn and vssn are a power supply potential line and a ground potential line, respectively, common to the word at address n. 35 is a voltage level detection circuit, and 36 is a data separation circuit.

At the time of reading, the power supply potential line d: the same as the peripheral circuit potential vDD, but the ground potential line d1, if selected by the address decoder of the A port, ■sA; if selected by the address decoder of the B port, ■ sB. The power supply potential line of the unselected word is DD, and the ground potential line is up to -1 of the precharge level vPR. However, vPR〉vsB〉■sA': 2ov. Now m
Consider the case where data at address is read from boat A and data at address n is read from boat B. First, memory cells Mm, M
When the data of n is the same, that is, both are 'H' or 'L' level, the potential on the bit line is as shown in the following table.
J:V3B.

B is the potential of vPR, and both data are °l Hl
``If so, the potentials of VPR, Bil, and vsB are generated on bit line B.

13ba/゛Next, let us consider the case where the data of the A port and the data of the B port are reversed, and IIL II and H''.

becomes. On the other hand, if the B port data is °゛H'' and the B port is left alone, the potential on the bit line B is vPR.

The potential on B is vsB. However, since these potentials overlap on the same bit line, the transfer gate 31 on bit line B is in the on state, so the bit line B drops to the potential ■sA. Due to the on state, the bit line B drops to the potential vsB. Conversely, if the data at port A is HI1 and the data at port B is L''', the potential of bit line B is vsB and the potential of bit line B is ■sA.
becomes.

In this way, fi
Since it is possible to distinguish between the data on the A port and the B port, just by adding a circuit to detect the potential level, the 2-port RAM can be expanded without increasing the number of bit lines or word lines. It turns out that it can be formed.

By adopting the memory cell structure of the present invention, normal RA
(2-port RAM) by simply changing the peripheral circuitry while keeping the memory cell arrangement as it is.
Of course, a multi-port RAM can be easily realized. Also,
In the present invention, the power supply voltage line and the ground potential line play the same role as the word line in a conventional memory.
This does not need to be connected to the gate of the transfer gate that connects the memory cell and the bit line, so there is no need to use polysilicon, etc., and you can simply use a low-resistance metal wiring material. -2 Enables faster access by shortening the delay time of memory cell selection.

In the present invention, it is possible to lower the potential of the power supply voltage line to near the precharge level of the y'h line by changing the potential of the power supply voltage line at the time of reading, and although an N-channel MOS transistor is used as the transfer gate, it is possible to achieve the same function. For connection, a P-channel MOS transistor or a diode or the like may be used.

Effects of the Invention As described in Section 2, according to the present invention, it is possible to reduce the memory chip area without requiring word line wiring for memory cells, and by changing the peripheral circuitry, it is possible to reduce the memory chip area.
M etc. can be easily realized. This makes it possible to reduce operating current when writing and reading data, reduce current consumption during precharging, and speed up data access.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a semiconductor memory device according to a first embodiment of the present invention, and FIG. 2 is a diagram showing potentials at each operating point during data writing and reading of the device according to the first embodiment.
FIG. 3 is a circuit diagram of a half- and nine-bit storage device according to a second embodiment of the present invention, and FIG. , Figure 6 # Title Nanaoka is a circuit diagram of a conventional semiconductor memory device. M , Mm, Mn-, , Memory cell, 11.12°3
1.32.33.34・ Transfer gate, ■D
D1. ■DDm, ■DDn-・-power supply voltage line, ■ss1
゜■5srn, ■ssn...-Ground potential line. Name of agent: Patent attorney Toshio Nakao and one other person M-
-7 Moribeiru Figure 2 (α2 [V] Saki 7', "1 (b' [vl Mutsumon Figure 3 Figure 5 Figure 4

Claims (1)

[Claims] A switch element with diode characteristics that has forward characteristics from the bit line to the memory cell is connected between the bit line and the memory cell, and the power supply potential and ground potential are made the same in the word direction without using a word line. The arranged memory cells are commonly connected to each other as a power supply potential line and a ground potential line, and when a desired memory cell is selected, the power supply potential line and the ground potential line connected to the memory cell are respectively set at a predetermined fixed potential. A semiconductor memory device configured to write and read data in and from a memory cell.