JPS6212996A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To prevent a non-selected word from floating up during recharging a bit line potential by giving a potential change in a negative direction only with respect to the non-selected word line during the recharging. CONSTITUTION:A new control signal phi1 rises to an L level at the start time (time t4) of a recharge cycle and to an H level at the time t5 on the completion of the recharging. At the time t3, when a word line WL0 is selected and other word line WL1... are non-selected, that is, at an earth potential level, an electrode opposing to the gate of a MOS capacitor C0 remains H level and other electrode opposing to the gate of a MOS capacitor C1 becomes the earth potential. Accordingly, during recharging (time t4-t5), a negative coupling is given only to the non-selected word line and a coupling noise in a positive direction due to the raise of the bit line potential during recharging is canceled.

Description

[Detailed Description of the Invention] [Industrial Field of Application] This invention is applicable to semiconductor memory devices, particularly dynamic type MO
This invention relates to a word line driving method for 8RAM (Random Access Memory).

[Prior Art J] FIG. 3 is a diagram showing an example of the configuration of a word line driving section of a conventional dynamic semiconductor memory device.

In FIG. 3, a conventional word line drive section turns on and off in response to a signal from a row address decoder 1, and applies a word line drive signal φ6 to a word line WLO.

1-transistor Q for word line driving, which serves as a memory cell selection gate for transmitting and non-transmitting to W L . 0I01. and,
Word line ~VL, 1. A bit line pair BL intersects with WL.
, BL and BIT! BL and a sense amplifier 2 for sensing (reading or writing) the signal level on BL. Here, the word lines are WLc, WL, HIRA l-
1! Although two ils are shown for each of BL and E3L, this is for convenience of explanation, and in reality, each is provided in a number corresponding to its storage capacity. word l1l
Each of WLO and WL is provided with an MJ to prevent an unselected word line from being erroneously selected (rising).
Transistors Q, , , Q for keeping unselected word lines at ground potential when the level of the R word line rises
l, is provided. Transistor Q, ,,Q,.

each has its drain connected to word l1WLo, WL, its source connected to ground potential, and its gates both receiving control signal RQ. The control signal RQ is
Transistor Q. An appropriate potential is applied to the gate of l+Ql1 to perform FJJ control of the operations of transistors Q, , , Qll. The circuit that generates signal RQ includes transistors Q7. It consists of Q2. transistor Q,
Its source is connected to the power supply potential Vcc, its drain is connected to the drain of transistor Q2 to serve as an output terminal, and its gate receives an inverted row address strobe signal RA.
Receive S. Transistor Q2 has its drain connected to the drain of transistor Q, its source grounded, and receives at its gate a signal RAS having substantially the same timing as the inverted signal of signal RAS. Further, each of the word lines WLo and WL+ receives the signal RA S + at its gate, and has its drain connected to the word lines WLo and WL+.
A transistor QO21Q+2 is provided which is connected to WL+ and whose source is grounded. This transistor Q.

21Q+2 is the word line W[. when the word hex drive system is inactive. This is to ensure that the potentials of , W and are at L°. Word lines WLo, WL, and bit lines BL
, 8m are each connected to a one-transistor/one-capacitor type memory cell 3.

FIG. 4 is a signal waveform diagram showing the operation timing of the circuit shown in FIG. 3. The operation will be described below with reference to FIGS. 3 and 4. Here, in Fig. 4, RA
S, RQ, WLo, WL+.

RAS, .phi., respectively represent the signals shown in FIG. 3, and BL, B〒 represent potentials of a plurality of bit line pairs crossing the word line. At time t, the signal RAS begins to fall, and an active cycle is accordingly started. In response to the fall of signal RAS, a row address signal is taken in and applied to row address decoder 1.

Row address decoder 1 decodes the given row address and sends its output signal to transistor Q. o * Q
+. Give to the gate. At time t2, when the output potential of the row address decoder 1 becomes stable (only one decoder output is "H", all other decoder outputs are "'L"), the word line drive signal φ is activated.

begins to rise, and the level of the selected word line begins to rise. At this time, signals RAS and RAS are applied to the gates of transistors Q1 and Q2, respectively, and transistor Q1 is turned off.

Q2 is turned on. In response to this, signal RQ changes at time t.
It starts to fall at 2. However, the signal RQ is a signal that gradually falls as shown in FIG. This prevents the potential of unselected word lines from rising slightly and causing malfunction (erroneous selection) when the word line drive signal φ rises before reaching the L'' level. When the level rises and a desired signal potential appears on the bit line pair BL, 8L, at time [, the sense amplifier 2 connected to the bit line pair BL, BL is activated, and only the bit line at the "L" level is activated. brought to ground level. Next, at time t, only the bit line at the "H" level has the power supply voltage ■.

. A restore (recharge) operation is performed to boost the voltage to the same level. At this time, half of the total number of bit lines that intersect with each word line are boosted to H" level, but this is due to the coupling capacitance I!1 (stray coupling capacitance) between the bit line and the word line. Noise (potential change) in the positive direction is applied to the word line.Therefore, as shown in FIG. When the voltage exceeds the threshold voltage of the transistor (composing the transistor), the unselected word line becomes selected, resulting in malfunction.

At time t, the signal RAS rises and the active cycle ends.

[Problems to be Solved by the Invention] The word line drive circuit of the conventional dynamic MO8RAM is configured as described above, and when the bit line is charged at the 11H11 level, the unselected word line becomes the bit line -
There is a problem in that the stray coupling capacitance between the word lines causes the word lines to move in the positive direction and float up, resulting in an incorrect selection state.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a semiconductor memory device equipped with a word line drive circuit that eliminates the above-mentioned problems and prevents unselected word lines from floating by simple means.

[Means for Solving the Problems 1] The semiconductor memory device according to the present invention provides a negative potential change only to unselected word lines when charging a bit line at "H" level in a word line drive circuit. The device is configured to include means.

Preferably, the means for applying a negative potential change is a MOS
This capacitance is made up of an i-transistor and is coupled to each word line, thereby canceling the positive coupling noise that unselected word lines receive during recharging.

[Function] In the single-conductor memory device equipped with the word line drive circuit according to the present invention, by applying a negative potential change only to unselected word lines at the time of recharging, the unselected word lines are charged with the bit line potential. This prevents it from floating up.

[Embodiments of the invention] An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing the configuration of a word line driving section of a semiconductor memory device including a word line driving circuit according to an embodiment of the present invention. In FIG. 1, unlike the conventional word line drive system shown in FIG. 3, the word lines WLo, WL,
MOS capacitors C0 and C+, each of which is controlled by the IIIIII signal φ, are newly provided. M
The OS capacitors C0 and C9 are composed of enhancement type n-channel MOS transistors, and their sources and drains are connected to each other, and the words aWLo,
WL, respectively, and receives a 1lilJ control signal φ at its gate.

FIG. 2 is a signal waveform diagram showing the operation timing of the circuit of FIG. 1. As can be seen from FIG. 2, the new control signal φ is ``L'' at the start of the beam charging cycle (at time 4).
This is a signal that falls to a high level and then rises to a high level at the time when the recharge ends.The operation will be described below with reference to FIGS. 1 and 2.

Now, at time t3, the word line WL is in the selected state, and the other word lines WL, . Suppose there is. The operation up to time ta is the same as the conventional one. At this time, the gates of the MOS capacitors C! I! The electrodes (source and drain, ie, substrate side electrodes) remain at the "H" level, and the other electrodes facing the gate of the MOS capacitor C1 are at the ground potential.

The signal φ is at the "H" level until time t4, and falls to the "L" level at time t4 when charging is started.The function of the ~10S capacitors C8 and C4 at this time will be explained.

MOS capacitor is enhancement type n-channel MO
It is composed of S transistors. That is, when the voltage to the drain and source (opposite electrodes) of the gate is below a positive value (for example, about 1V), it is in an "off state", that is, the capacitance is 0 and there is no effect, and above this value, it is in an "on state". In other words, it operates with a large capacitance. When the control signal φ falls at time t, before that, the signal φ
Considering that 1 is the "H" level (bit line precharge level), the following operation can be performed as follows.
G- and C+ do it.

(2) The capacitor C8 is in the "off state!9" and has no effect on the selected word line WLc, and does not provide coupling in the negative direction (direction of lowering the potential of the word line).

■ Capacitor C connected to unselected word It W L +
1 is in the "on state" and the non-selected word # W L +
receives coupling in the negative direction (in the direction of lowering the word line potential).

Therefore, during recharging (time t, ~ji), negative coupling is applied only to unselected word lines, and the positive coupling noise caused by the bit line potential rising during recharging is canceled. Ru. Head, selected word #1! No negative coupling is applied to W L , , and the selected word line level does not fall. Therefore, as shown in FIG. 2, the potential of the unselected word Ill W L + will not rise, and the memory cells connected to this word line will not be erroneously selected.

(Effects of the Invention) As described above, according to the present invention, the MO
Since it is constructed using a capacitor made of an S transistor, it is possible to prevent an unselected word line from floating when bit line potential is recharged by a simple means, and a semiconductor memory device that operates stably can be obtained.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the configuration of a word line drive system of a semiconductor memory device according to an embodiment of the present invention. FIG. 2 is a signal waveform diagram showing the operation timing of the circuit of FIG. 1. FIG. 3 is a diagram showing the configuration of a word line drive system in a conventional semiconductor memory device. FIG. 4 is a signal waveform diagram showing the operation timing of the conventional semiconductor memory device shown in FIG. In the figure, 1 is a row address decoder, WL, , WL
, are word lines, BL and BL are bit lines, and C, , C, are capacitors formed by enhancement type n-channel MOS transistors. In addition, in the figures, the same reference numerals do not indicate the same or equivalent parts. Agent Masu Oiwa Yugu 4 figure procedure correction belt (voluntary) Showa 6iJJ1 condolence 6B Sono

Claims (1)

[Scope of Claims] (1) A word line connected to a memory cell selection gate that turns on and off in response to a signal from a row address decoder, a bit line that intersects the word line, and a word line that intersects the word line and the word line. A semiconductor memory device comprising a memory cell connected to a line, wherein the semiconductor memory device performs a bit line potential recharge cycle to make the bit line potential at "H" level sufficiently high after reading data on the bit line. A semiconductor memory device comprising: bias means for applying a negative potential change to only unselected word lines during the bit line potential recharge cycle period. (2) The semiconductor memory device according to claim 1, wherein the bias means is a capacitor formed of a MOS transistor connected to each of the word lines. (3) The MOS transistor constituting the capacitor is an enhancement type n-channel MOS transistor,
Claim 2, wherein the two conductive terminals are connected to each other and to the word line, and the gate thereof receives as a control signal a clock signal that changes from a positive potential to a ground potential during the bit line potential recharge cycle. The semiconductor storage device described in 1.