JPS62128331A - Information processor - Google Patents

Abstract

PURPOSE:To perform the decision of sizes among floating point data at a high speed by deciding the sizes among normalized data without performing a digit aligning operation. CONSTITUTION:In an information processor which handles the floating point data consisting of an index part, a mantissa part, and the code of a mantissa, the titled device is constituted with a means which compares two index parts, the means which decides whether the highest order digit of the mantissa part is zero or not, and the means which decides, when the sizes between two floating point data are decided, the sizes between two data based on the sizes of index parts, and the code of the mantissa corresponding to the larger index part regardless of a comparison result after the digit alignment of the mantissa part, in a case that the index parts of two data are different and also, the most significant digit of the mantissa part corresponding to the larger index part is not zero. Thereby, the comparison operation of floating point data can be performed at a high speed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an information processing device, and particularly to a means for comparing floating point data.

[Conventional technology]

In many information processing devices, floating point data is defined and four arithmetic operations can be performed on it. Figure 2 shows an example of the format of floating point data.
ζ, the mantissa is a 6-digit 1 with a decimal point to the left of the most significant +11
A hexadecimal decimal number, the exponent part is an unsigned integer of 7 bits, and the sign bit indicates the sign of the mantissa.

Let the numbers represented by the mantissa part, 9 exponent part, and the sign bit be M, respectively.
When E and S are used, the numerical values represented by this floating point data are as follows.

M ``Normalized display'' is defined in order to maintain and unambiguously display the result of an operation.In other words, if the mantissa is not zero and the most significant digit is zero, the mantissa The mantissa is shifted to the left until the most significant digit is no longer zero, and the shifted arithmetic number or exponent remains in a slightly truncated display, which is called a "normalized display."Also, if the mantissa is zero, , a display in which the exponent part and the sign bit are zero is referred to as a "normalized zero display." Note that displaying the result of an operation in such a normalized display is called post-operation normalization.

Addition and subtraction of floating point data is performed as follows.

l) In the case of subtraction, reverse the sign of the subtracted number.

2) Compare the exponent parts of two numbers.

3) If there is a difference in the exponent parts of the two numbers, move the mantissa part corresponding to the smaller exponent part to the right and at the same time increase the exponent part,
Make the exponent parts of the two numbers equal (the lower significant 11i may be lost by shifting the mantissa part, but one digit is placed in the guard digit, and the guard 1j is truncated after normalization after ljJ calculation).

4) Perform addition and subtraction of the mantissa parts taking the sign into account, and use the sign of the summand/minuend as the sign of the result.

5) If a digit error occurs due to addition of the mantissa, shift the mantissa by one digit to the right and increase the exponent by l.

If the result is negative due to subtraction of the mantissa, the complement of the mantissa is found and the sign of the result is inverted. Furthermore, if necessary, normalization is performed after the calculation.

The magnitude relationship between two floating point data is determined by the sign of the result of their subtraction, so the comparison operations include subtraction, handling of mantissa digit smearing, complementation processing when the mantissa becomes negative, and so on. and excluding post-operation normalization processing.

[Problems that the invention attempts to solve]

However, if the exponent parts of the data to be compared are different and the most significant digit of the mantissa part of the data with a large exponent part is not zero, it is clear that its absolute value is greater than the absolute value of the other data, and the digit Regardless of the comparison result of the mantissa parts after matching, the magnitude relationship between the two numbers can be immediately determined based on the sign of the mantissa parts. That is, floating 4. Digit matching is necessary when comparing several data points because the exponent parts of the two numbers are different.
and the most significant digit of the mantissa corresponding to the larger exponent is zero, and the normalized exponent of zero is never greater than the exponent of the other data, so the normalized No digit alignment operation is required when comparing data. However, in the past, as mentioned above, the magnitude relationship between two numbers is uniformly determined from the comparison result of the mantissa part after digit adjustment, which has the disadvantage that high-speed processing cannot be performed.

The present invention solves these conventional drawbacks, and its purpose is to enable high-speed determination of the magnitude of floating-point data.

[Means for solving problems]

In order to achieve the above object, the present invention provides an information processing device that handles floating point data consisting of an exponent part, a mantissa part, and a sign of the mantissa, and includes means for comparing two exponent parts, and the most significant part of the mantissa part. A means for determining whether a digit is zero or not, and a means for determining the magnitude relationship between two floating point data, if the exponents of the two data are different and the most significant digit of the mantissa corresponding to the larger exponent is If it is not zero, the method determines the magnitude relationship between the two data based on the magnitude relationship of the exponent part and the sign of the mantissa corresponding to the larger exponent part, regardless of the comparison result after digit adjustment of the mantissa part. configured.

[Effect]

In the information processing device of the present invention, when determining the magnitude relationship between two floating point data, the exponent parts of the two are different,
And if the data with a large exponent part is a normalized display, that is, if the most significant digit of its mantissa part is not zero, the magnitude relationship is determined directly by the sign of the mantissa part, and in other cases Since the magnitude relationship is determined by the comparison result of the mantissa after digit alignment, floating-point data comparison operations can be performed at high speed.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 shows a floating point data calculation circuit of an information processing device that is an embodiment of the present invention, and is controlled by a microprogram (circuits used only for multiplication and division are omitted because they are not related to the present invention. The data register 10 connects a floating point data register and a main memory data register (not shown) to this floating point data calculation circuit. S input register 21 and S[3
The registers 22 are 1-bit registers each, and the SΔ input register I is the output of the sign calculator 20, and the SB register 22
takes the sign bit on the data bus 10 as an input, and the outputs of both disks 21 and 22 serve as inputs to the sign calculator 20. Also, the contents of the S input register 21 are the data bus 1
It can be output as 0 and can also be determined by a microprogram in a microprogram branch determination circuit (not shown). The EA input register 1 and the EB register 32 are each 8-bit registers, and the EA input register 1 receives the output of the exponent operator 30, the EB register 32 receives the exponent part on the data lotus 10, and both registers 31. The output of 32 serves as an input to an exponent operator 30. In addition, the contents of EA input register 1 can be output to data bus 10, and EΔ
The Z signal 33 to E indicating that the contents of the input register 1 are zero and the EASli signal 34 indicating that the contents are negative can be determined by a microprogram. M△in register 1 and M
The B registers 42 are 32-bit registers each, and the M
The A input register 1 receives the output of the mantissa/3ii calculator 40, and the MB register 42 receives the mantissa part on the data lotus 10 as input.
The outputs of both registers 41 and 42 serve as inputs to the mantissa calculator 40. In addition, the contents of MA input register 1 can be output to data bus 10, and MAN signal 43 and MBN signal indicating that the third digit from the left (9th bit to 12th bit) of both registers 41 and 42 are not zero. 44 can be determined by a microprogram. The digit shift circuit 50 shifts the contents of the MA input register 1 or the MB register 42 by 1 to the left and right.
It is possible to shift by digit (4 bits). The condition code circuit 60 receives the contents of the SB register 22 and the MFZ signal 45 indicating that the output of the mantissa calculator 40 is zero;
Using the MFS signal 46 that indicates that the output is negative, a 2-bit condition code (
CC).

The second property indicates the format of floating point data handled by the information processing device of the embodiment. The operation of a comparison instruction regarding such floating-point data is to determine the magnitude relationship between both operands based on the result of subtracting the second operand from the first operand, and to calculate this using a 2-bit condition code (
CC) as follows.

(1st operand) = (2nd operand)... CC
-00 (1st operand) < (2nd operand)... CC
←O1 (1st operand)> (2nd operand)...CC
-10 FIG. 3 is a flowchart of a microprogram that executes a floating-point data comparison instruction in the information processing device of the embodiment. In the figure, a=h, j to n correspond to each step of the microprogram, The upper row of the frame representing each step shows the operation performed in that microstep, and the lower row shows the signal that is tested when the next microstep 2 is conditionally selected (the lower row signal shows the effect of the upper row operation). (If the above action is accepted, the state before the operation in the upper row is executed is tested.)
.

In addition, in FIG. 3 and the following description, Si.

I': i and Mi indicate the sign bit exponent part and mantissa part of the first operand, respectively. The operation of this embodiment will be explained below.

l) Comparison of exponents/step a Data bus lO to first operand sign picks 1-3
1. The exponent part EI and the mantissa part Ml are stored in the SB register 22. E [
3 register 32. Loaded into the MB register 42 (right justified, with leading zeros).

-Step b SB register 22. EB register 32. MB register 4
The contents of 2 are sent to SA input register 1.2 via arithmetic units 20, 30, and 40. EA input register 1. The data is transferred to the MA input register 1, and the sign of the second operand, the sign of the second operand, and the exponent part E2. The mantissa part M2 is stored in the SB register 22, the E B register 32. Loaded into MB register 42. However, the sign bit S2 is inverted upon loading from the data bus IO (S2).

- Step C The sign bit comparison result (ie, exclusive OR of Sl and g7) is loaded into the SA input register 1, and the exponent part comparison result (ie, El-E2) is loaded into the E input register 31.

- Step d' The EAZ signal and the EAS signal (ie, the magnitude relationship between El and E2) are tested.

2) In the case of El>E2 - Step e[', In the case of I>E2, this step is executed after step d. The sign bit Sl and exponent part El of the first operand are transferred from the data bus 10 to the SB register 2.
2.2B register 32 is loaded and the MAN signal (ie, the signal indicating that the first operand is normalized) is tested.

Furthermore, in preparation for the next possible digit alignment operation, EA input register 1 is decremented by 1.

・Step f If El>E2 and the first operand is normalized, this step is executed after step e, and the condition code CC is changed as follows according to the contents of the SB register 22 (Zunawara Sl). Set.

1st bit of CC ← 513 2nd bit of CC 1-5r3 ・Step g [', If I>E2 and the first operand is not normalized, then this step is executed after step e. Ru. The contents of the M input register 41 (that is, Ml) are shifted to the left by one digit (relatively, the MB register 42 is shifted to the right, and the lowest digit of the MB register 2 is protected. The two EAZ signals (i.e., the 111 match completion signal) are tested and the EA input register 1 is decremented by 0.

・Step h・1. .

If the digit alignment is not completed, this step is executed and
The contents of the MB register 42 (ie, Ml) are shifted one digit to the right. The EAZ signal is tested and the contents of EA input register 1 are decremented, and this step is repeated until the digit alignment is completed.

- Step j When the digit alignment is completed, this step is executed and the contents of the S input register 21 (ie, SlΦ52) are tested.

- Step k This step is executed when S1≠32. The mantissa calculator 40 calculates the contents of the MA input register 1 and the MB register 42.
The condition code CC is set as shown below based on the output (Ml+M2 after Zunawara digit adjustment) and the contents of the SB register 22 (ie, Sl).

1st bit of CC - (Ding■ΦMFS) ・``Ding7CC
(7) 2nd pit) = (Sr3G)MFS) ・MF
Z.Step β This step is executed when 51=32. The mantissa calculator 40 converts the contents of the MA input register 1 into the MB register 4.
A calculation is performed to subtract the contents of 2, and the condition code FCC is set in the same way as in the step based on the output (ie, M1-M1 after digit alignment) and the content of the SB register 22 (ie, Sl).

3) When El<E2, step m When El<E2, this step is executed after step d. The contents of the MB register 42 (Ml) are stored in the arithmetic unit 4.
0 to the old MA register, and is transferred to the MB register 42.
The mantissa of the first operand is again loaded from the data bus IO. The MBN signal (i.e., the signal indicating that the second operand is normalized) is tested, and the contents of EA input register I are updated in preparation for possible next alignment/operation operations. Although it is said that it is anti-Chinese, to E = E2-El-1).

Step r If El<E2 and the second operand is normalized, this step is executed after step m, and a condition code CC is sent according to the contents of the SB register 22 (ie, S2).

- Step B-a If El<E2 and the second operand is not normalized, these steps are executed after step m.

As in the case of El>E2, tfi adjustment is performed by moving M2 to the left in step g and moving M+ to the right in step h.

When Ij adjustment is completed, move to step or press M2
±Ml is executed, and the condition code CC is set according to the result and the contents of the SB register 22 (ie, 7).

4) When E1=E2/Step n When E1=E2, this step is executed after step d. The sign bit St of the first operand is loaded from the data bus 10 and the contents of the SA input register 1 (5tO32) are tested.

- Step k or 1 If E1=E2, this step is executed next to step n. The operation is similar to the operation after completion of digit alignment in the case of E I >E2.

〔Effect of the invention〕

As explained above, the present invention has the effect of speeding up the size determination operation of floating point data by determining the magnitude relationship without digit alignment for normalized data when comparing floating point data. There is.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a floating point data calculation circuit of an information processing device that is an embodiment of the present invention, FIG. 2 is a diagram showing the data format of floating point data, and FIG. 3 is a diagram showing the execution of a floating point data comparison instruction. 2 is a flowchart of a microprogram. In the figure, 10 is a data bus, 20 is a sign calculator,
21 is an S input register, 22 is an SB register, 30 is an exponent operator, 31 is an EA input register, 32 is an EB register,
3 is the EAZ signal, 34 is the EAS signal, 4o is the mantissa operator, 41 is the M input register, 42 is the MB register, 43 is the M
AN signal, 44 is MBN signal, 45 is MFZ signal, 46
is an MFS signal, 50 is a shift circuit, and 60 is a condition code circuit.

Claims (1)

[Scope of Claims] An information processing device that handles floating point data consisting of an exponent part, a mantissa part, and a sign of the mantissa, comprising: means for comparing two exponent parts; and the most significant digit of the mantissa part is zero. In determining the magnitude relationship between two floating point data, if the exponent parts of the two data are different and the most significant digit of the mantissa corresponding to the larger exponent part is not zero, , characterized by comprising means for determining the magnitude relationship between two data based on the magnitude relationship of the exponent part and the sign of the mantissa corresponding to the larger exponent part, regardless of the comparison result after digit alignment of the mantissa part. Information processing equipment.