JPS62125709A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To control a threshold voltage of a FET to a desired value even when the element characteristic changes due to temperature fluctuation by detecting a change in the characteristic of the semiconductor element in operation and feeding back the detected result so as to correct the change of the characteristic. CONSTITUTION:Suppose that a threshold voltage Vt of a FET 1 is higher than a gate voltage Vg, the FET 1 is cut off. Then a voltage Vd is higher, an output voltage Vc of a buffer circuit is higher to apply feedback so as to lower the threshold voltage Vt of the FET 1. When the voltage Vt is lower than the voltage Vg, the FET 1 is conductive conversely. Since the current drive capability of the FET 1 is sufficiently larger than a current Io, the voltages Vd, Vc are lower to apply feedback thereby increasing the voltage Vt. Since FETs 1, 101 and 102 are mounted on one and same chip, the temperature of them is nearly equal to each other and the threshold voltage of each FET is nearly equal. Thus, the threshold voltage of each FET is always nearly equal to the gate voltage Vg.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a semiconductor integrated circuit that can control the characteristics of a semiconductor element, and is particularly applicable to an FET that can compensate for threshold voltage fluctuations caused by temperature changes. The present invention relates to a semiconductor integrated circuit suitable for

[Background of the invention]

As a method of suppressing variations in the threshold voltage of MESFETs on GaAs substrates, for example, the growth method of the substrate crystal may be devised (Proceedings of the 44th Japan Society of Applied Physics Conference, p. 551, p. 25, p. E-3). , 25p-E-4 (19
(September 1983)), lowering the dislocation density of the crystal by doping the substrate with impurities such as Al or In (ibid., 25p-E-5, GaAs IC Symposium, pp. 45-48 (1984)). or by making the channel layer thinner (Society of Applied Physics, Applied Electronics Physics Subcommittee Research Report 19-2)
(Page 4 (May 1983)), moving the high concentration layer in the source/drain region away from the gate (Page 116 (September 1983) of the 1986 National Conference of the Semiconductor and Materials Division of the Institute of Electronics and Communication Engineers)
) is known to suppress the short channel effect. However, all of these methods are control methods during the manufacturing process, and although they are effective in reducing variations in the threshold voltage of FETs under certain operating conditions, It is not possible to compensate for variations in properties due to

Additionally, devices for controlling the threshold voltage after the product is completed are disclosed in Japanese Patent Laid-Open Nos. 57-211783 and 1987-130560. In these devices, a semiconductor layer of a conductivity type opposite to that of the channel region is provided below the channel region of the FET, and the threshold voltage is controlled by controlling the voltage applied to this layer. However, in these devices, no specific means has been proposed for detecting the threshold voltage of the FET during operation or for feeding back the detected results to adjust the voltage applied to the layer below the channel. First, it is still not possible to compensate well for variations in threshold voltage during operation.

[Purpose of the invention]

An object of the present invention is to provide a semiconductor integrated circuit that can control the characteristics of a semiconductor element during operation, and in particular to provide an FET that can control the threshold voltage in response to fluctuations in threshold voltage caused by temperature fluctuations. be.

[Summary of the invention]

In order to achieve the above object, the semiconductor integrated circuit of the present invention includes means for detecting changes in the characteristics of a semiconductor element during operation, and means for feeding back the detected results to correct the changes in the characteristics. In particular, when the present invention is applied to an FET, a fourth electrode is provided in addition to the source, drain, and gate electrodes, as described in the above-mentioned Japanese Patent Laid-Open No. 57-211783. have,
By using a FET whose threshold voltage can be changed and controlled by changing the voltage applied to the fourth electrode,
It has means for controlling the voltage applied to the fourth electrode in accordance with fluctuations in the threshold voltage of the ET.

In other words, FETs in the same semiconductor integrated circuit chip
Based on the characteristic that each threshold voltage of is almost equal,
A dummy FET for threshold voltage monitoring is provided in the chip to form a feedback loop in which the threshold voltage of the dummy FET is always at the desired value. The same voltage is also applied to the fourth electrode of FETs other than the dummy, which are supposed to perform a predetermined circuit function, and as a result, all FETs being controlled
The threshold voltage is set to a desired value.

[Embodiments of the invention]

FIG. 1 shows a basic circuit configuration of an embodiment of the present invention. 1st
In the figure, 100 indicates a circuit network having predetermined logic functions, memory functions, etc. of this integrated circuit, and 101 and 102 indicate FETs (first FETs) used therein. In addition, 1 is a dummy FET (second FET) provided to monitor the threshold voltage of the FET in this integrated circuit.
), and at least these FETI, 101,10
2 shall be manufactured on the same semiconductor chip. In addition,
In addition to the source, drain, and gate electrodes, the FETs 1, 101, and 102 are equipped with fourth electrodes 6, 111, and 112 whose threshold voltages can be changed depending on the applied voltage. Such a FET can be realized, for example, by providing a layer of a conductivity type opposite to that of the channel region to which a voltage is applied by the electrodes 6, 111, 112 below the channel region.

In other words, N-channel (or P-channel) type FE
When a P-type (N-type) layer is provided below the T channel, when the voltage applied to the P-type (N-type) layer is lowered (increased), the channel layer shrinks.

The gate voltage required to cut off that channel will be higher (lower). Therefore, with such a structure, the threshold voltage can be raised (lowered) by lowering (raising) the voltage applied to the P-type (N-type) layer. As one manufacturing method for concretely realizing such a structure, for example, Japanese Patent Laid-Open No. 57-211783 discloses a method of implanting a light element, which becomes a P-type impurity, into an N-channel type GaA sMESFET by ion implantation. is detailed.

Ion implantation allows light elements to penetrate deeply, making it possible to form a P-type layer deeper than the channel. In this case, if the P-type layer is formed at a relatively high concentration near the channel, high sensitivity can be achieved, with the threshold voltage changing by nearly 1 mV for every 1 mV change in the voltage applied to the P-type layer. What you have is also possible. Also, 2 in Figure 1 is FE
It is a load element for supplying a minute current (a sufficiently small current compared to the current drive capability of the FETI) to the TI, and specifically, it is a load element having a resistance value sufficiently higher than the on-resistance of the FETI. 3 is a buffer circuit for applying feedback, 4 is a power supply on the high potential side, and 5 is a terminal that supplies a voltage corresponding to the desired threshold voltage (strictly speaking, a voltage slightly higher than the desired threshold voltage). . In the following explanation, the current flowing through the load element 2 is Io, the voltage applied to the terminal 5 is Vg, and the voltage at the connection point between the FET 1 and the load element 2 is V.
The control voltage applied to the d, ffl poles 6.11] and 112 is expressed as Vc, and the threshold voltage of FET 1 and its value are expressed as Vt, respectively.

Next, the operation of the circuit shown in FIG. 1 will be explained.

Now suppose that the threshold voltage Vt of FETI is the gate voltage vg
If it becomes higher, the FETI will be shut off.

Then, the voltage Vd increases, the output voltage Vc of the buffer circuit also increases, and feedback is applied to lower the threshold voltage Vt of the FET1. Conversely, if Vt becomes lower than Vg, FET1 will be in the 6-pass state. Then, since the current drive capability of FET1- is sufficiently large compared to IQ, Vd and Vc become low, and feedback is applied to raise Vt. Therefore, a steady state is reached when Vt becomes approximately equal to Vg (strictly speaking, when Vt is slightly lower by the amount of minute current Io flowing through FETI). Since Vc at this time is also applied to FETl01.102 by the electrodes 111 and 112, respectively, the threshold voltages of FETl0I and 102 also become equal to the threshold voltage Vt of FET1. Quantitatively, K (Vg - Vt)2 = I.

That is, a steady state occurs when Vt = Vg - I7X. Therefore, in order to suppress the difference between Vt and vg to about 30 mV, for example, IO≦],
If OμA, K≧10mA/V2. That is, FET
The gate width of 1 may be set to about 10 to 100 mm or more.

In the circuit shown in Fig. 1, even if the threshold voltage of the FET changes due to temperature fluctuations, etc., the control voltage Vc always changes due to the feedback operation described above so that the threshold voltage Vt of the FETl is almost equal to the gate voltage Vg. . Also, F
Since E T 1 and FETs 101 and +02 are on the same chip, they have approximately the same temperature, and the threshold voltages of each FET are approximately equal. Therefore, the threshold voltage of each FET is always approximately equal to the gate voltage Vg. Note that, according to the above-described feedback operation, in addition to temperature changes, for example, FET
It is clear that deviations in the threshold voltages of the FETs due to variations in manufacturing conditions can also be corrected. Next, a more specific example will be shown using FIG. 2 and FIGS. 4 to 9. However, in FIG. 2 and FIGS. 4 to 9, a portion corresponding to 100 in FIG. 1 is not shown.

FIG. 2 shows an example in which the buffer circuit is configured with a source follower and a voltage corresponding to a desired threshold voltage is generated by resistance division. 31 is FET for source follower
, 32 is a load F for supplying current to the source follower.
These two FETs constitute a buffer circuit. Further, 51.5z is a resistance element for voltage division. Even if there is a large difference between the designed resistance value and the actual value of the resistance element on an integrated circuit, the variation in the ratio of the resistance values of the two resistance elements can be reduced, so the variation in tA
It is thought that it is almost determined solely by voltage fluctuations. That is,
The value of Vg is the ratio of this resistor 51 to the sum of the resistance values of 51 and 52 multiplied by the voltage of power supply 4, but since the former is almost constant, only the variation of the latter is the 7g variation. will be decided. Therefore, if the design is made so that the absolute value of 7g is small, the variation in Vg can be suppressed to a small value. On the other hand, if a CFL circuit as shown in Fig. 3 is used in the circuit of the main body having predetermined logic functions, memory functions, etc. (the part within 100 in Fig. 1), the threshold voltage of the drive FETl0I becomes Ov. Close positive value (OV~
If it is about 0.1v), it is most convenient; if it is higher than this, the current flowing through the drive FET l0I will be small and the operating speed of the circuit will be slow; if it is lower than this, the current flowing through the drive FE
Since Tl0I is no longer cut off, the operating margin becomes smaller. Therefore, in the circuit of Fig. 2, the DCF is applied to the circuit of the main body.
When L is used, if it is designed so that Vg is close to Ov, the threshold voltage of the FET will always be controlled to the most convenient value regardless of variations in resistance value or power supply voltage. In Fig. 2, a FET whose gate electrode and source electrode are connected is used as the load element 2 that supplies a minute current to the FETI, but the gate width of the load FET 2 is sufficiently larger than the gate width of the FETI. or the gate length of load FET2 is
If it is designed to be sufficiently longer than the gate length of
The above specification (supplying a current sufficiently smaller than the current drive capability of FET 1) can be satisfied.

The circuit in FIG. 4 is a simplified version of the circuit in FIG. 2, in which the gate electrode and source electrode of FET 1 are connected to
g is made to be Ov. As mentioned in the explanation of Fig. 1, the threshold voltage of the FET to be controlled is
Although the value will be slightly lower than the gate voltage Vg, if there is no practical problem even if the threshold voltage of the FETs 101 and 102 in the circuit network 100 of the main body becomes slightly negative, set vg as shown in FIG. It can also be Ov. Alternatively, in the circuit of FIG. 4, the ground potential (FE
The potential connecting the gate electrode and source electrode of TI) is
The ground potential (FE) of the main circuit 100 shown in FIG.
If the voltage applied between the fourth electrode 111, 112 and the source electrode of FET 101, 102 in the main circuit is made slightly lower than the potential connecting the source electrode of TIOI, 102, the voltage applied between the source electrode of The voltage is slightly lower than the voltage applied between the fourth electrode 6 and the source electrode, and therefore the threshold voltage of the FETs 101 and 102 of one main circuit is slightly higher than the threshold voltage Vt of the monitor FET 1. In this way, it is also possible to make the threshold voltages of the FETs 101 and 102 of the main circuit a positive value using the circuit shown in FIG.

The circuit in Figure 5 is also a simplified version of the circuit in Figure 2,
This is an example in which the drain voltage of the FETI is directly supplied to the electrode 6 of the node 4 without passing through a buffer circuit.

The scale of the circuit network 100 (FIG. 1) of the main body is relatively small;
The circuit shown in FIG. 5 can also be used in cases where large noise is not added to Vc.

Further, the control voltage Vc required to set the threshold voltage of FET 1.101.102 to a desired value is a negative value,
If control cannot be achieved using the circuits shown in FIGS. 2, 4, or S, control can be achieved by inserting a level shift diode 35 as shown in FIGS. In addition,
In the figures after FIG. 6, the circuit that supplies 7g is omitted. Also.

A plurality of level shift diodes 35 may be connected in series depending on the level of the control voltage Vc.

Furthermore, it goes without saying that the circuit of FIG. 7 is designed so that the current flowing through the load element 32 is smaller than the current flowing through the load cord 2.

In addition, P provided below the channel of FETl0I, 102
If the mold layer is made too shallow, the parasitic capacitance will increase and the operation speed will be slow, so in reality it is necessary to make the mold layer at a certain depth. In that case, if the sensitivity of changes in the threshold voltage of FETI and 101 and 102 to changes in the control voltage Vc becomes low and the circuits in FIGS. 2, 4, and 5 cannot control it sufficiently, As shown in FIG. 8, it is also possible to compensate for the lack of sensitivity by configuring the buffer circuit with two inverter circuits. In the circuits shown in Figures 2, 4, and 5, the change in Vd is changed to a change in Vc with the same amplitude or with some attenuation, whereas in the circuit shown in Figure 8, it is amplified by the voltage amplification action of the inverter. can do.

Therefore, a slight change in Vd appears as a large change in Vc, which can compensate for the lack of sensitivity of the change in the threshold voltage of the FET with respect to Vc. Further, in the circuit shown in FIG. 8, a level shift circuit (portions 32 and 35) as shown in FIGS. 6 and 7 can be provided as necessary.

In addition, in FIG. 2 and FIGS. 4 to 8, the load elements 2 that supply minute currents are all FETs whose source electrode and gate electrode are connected, but other elements may be used as long as they have a high resistance value. It is also possible to replace it with a resistive element. The same applies to the load element 32 (although 32 does not necessarily have a high resistance value). Further, the method of supplying Vg is not limited to resistance division, and any method that can obtain a desired voltage may be used. Furthermore, by setting Vg to a negative value, it is also possible to control the threshold voltage to a negative value. Also, as shown in Figure 8, as the number of stages in the circuit that makes up the feedback loop increases, the possibility that the voltage on the loop will oscillate increases. This can be dealt with by providing a capacitor 8.

Further, the present invention provides MESFE'r on a GaAs substrate.
By providing a fourth electrode whose threshold voltage changes by changing the applied voltage, any FET can be
It can also be applied to

FIG. 10 shows an example of application to a MOSFET on a Si substrate. Since the threshold voltage of a MOSFET on a Si substrate is also lowered by increasing the substrate or well voltage, the circuit shown in FIG. 1O can be expected to have the same effect as the circuit shown in FIG. Also,
All the explanations so far have been made assuming a type of FET where the threshold voltage decreases when the voltage of the fourth electrode is increased, but conversely, an FET of the type where the threshold voltage increases when the voltage of the fourth electrode is increased. It goes without saying that the present invention can be applied even when FETs are used. In that case, the buffer circuit 3 shown in FIG. 1 is provided with an inverting function. Specifically, one method is to use an odd number of inverter stages in the circuit shown in FIG. 8, for example. Furthermore, although the explanation has been mainly on N-channel type FETs up to this point, it goes without saying that the present invention can also be applied to P-channel type FETs by changing the polarity of the power supply and level shift diode.

In addition, in order to effectively bring out the effects of the present invention, it is necessary to
It is desirable that the source electrodes of FET 1.01.102 used in the main body circuit and FET 1 for monitoring are approximately at the same potential, but it is not necessary that they always be at the same potential. For example, if a circuit as shown in FIG. 11 is provided in 100,
In this circuit, FETl01.102.103.104
The source electrode of FET1.01.102 is connected to the ground potential like the source electrode of FETI, but the source electrode of FET103.104 is not directly connected to the ground potential. This circuit is used as a memory cell of a semiconductor memory device, and FET103.104 is 123.12 when reading.
The electrode on the 4 side operates as a source electrode, and the ffi pole on the 133 or 134 side operates as a source electrode during writing. For this circuit, F E T 10
The variation in the threshold voltage of 3.104 becomes a particular problem when the potential of 123, 124, 133 or 134 is low level (near Ov), and both 123 and 133 or 124 and 134 When both are at high level, there is no need to precisely control the threshold voltage of FET 103 or 104, respectively. Therefore, in this circuit as well, the voltages of the source electrodes of the FETs to be controlled are all approximately Ov when control is required.

Therefore, even when the present invention is applied to such a controlled object, the effects of the present invention are not impaired.

〔Effect of the invention〕

As explained above, the present invention detects changes in the characteristics of a semiconductor element during operation, and feeds back the detected results to correct changes in the characteristics. can be compensated. especially,
If the present invention is applied to an FET, it is possible to control the threshold voltage of the FET to a desired value even if the element characteristics change due to temperature fluctuations or the like.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing the basic configuration of an embodiment of the present invention, FIG. 2 and FIGS. 4 to 9 are circuit diagrams showing more specific embodiments of the present invention, and FIG. FIG. 3 and FIG. 11 are circuit diagrams showing an example of a controlled object to which the present invention is applied. 1... Second FET with a fourth electrode for controlling the threshold voltage 101, 102... Fourth FET for controlling the threshold voltage
1st FET with an electrode 2...Load element with high resistance value 3...Buffer circuit 4...Power source 5 on the high potential side
...Terminal 6 for supplying a voltage corresponding to a desired threshold voltage...Fourth electrode 7, Low potential side power supply 8...Capacitor 31 for preventing oscillation...Source follower FET 32...Load element 33.34...Inverter 3 configuring the buffer circuit
5... Level shift diode 51, 52... Voltage dividing resistor 100... Circuit network having predetermined logic function, memory function, etc.

Claims (9)

[Claims] (1) A semiconductor integrated circuit comprising means for detecting changes in the characteristics of a semiconductor element during operation, and means for feeding back the detected results to correct the changes in the characteristics. (2) Claim 1, wherein the semiconductor element is a FET, and the characteristic is a threshold voltage.
Semiconductor integrated circuit described in Section 1. (3) The FET includes a first and a second FET, each having a source electrode, a drain electrode, a gate electrode, and a fourth electrode, and the threshold voltage can be adjusted by controlling the voltage supplied to the fourth electrode. The semiconductor according to claim 2, wherein a voltage is controllable and a circuit for supplying voltage to the fourth electrode of the first FET includes the second FET. integrated circuit. (4) The circuit for supplying voltage to the fourth electrode of the first FET includes means for applying a voltage approximately equal to a predetermined threshold voltage to the gate electrode of the second FET;
means for supplying a minute current to the drain electrode of the second FET, and feeding back the voltage of the drain electrode of the second FET to the fourth electrode of the second FET.
and means for canceling a change in the threshold voltage of T, so that the voltage applied to the fourth electrode of the second FET is also supplied to the fourth electrode of the first FET. A semiconductor integrated circuit according to claim 3, characterized in that: (5) The voltage approximately equal to the above predetermined threshold voltage is 0V.
Claim 4 characterized in that the voltage is close to
Semiconductor integrated circuit described in Section 1. (6) The first and second FETs are each
T has a structure in which a semiconductor layer of a conductivity type opposite to that of the channel region is provided below the channel region, and the fourth electrode is the semiconductor layer or an electrode electrically connected to the semiconductor layer. Claim 3 or 4
Semiconductor integrated circuit described in Section 1. (7) The source electrodes of the first and second FETs are at the same potential, as described in any one of claims 3, 4, and 6. semiconductor integrated circuits. (8) The first and second FETs are MESFETs formed on a GaAs substrate. The semiconductor integrated circuit according to any one of the items. (9) The first and second FETs are MOSFETs formed on a Si substrate. The semiconductor integrated circuit according to any one of the items.