JPS6212061B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a braking device in which a general-purpose digital computer controls a braking device that can prevent wheels from locking up when sudden braking is applied.

Heretofore, devices for preventing wheels from locking up have been called skid control or anti-skid devices, and these anti-skid devices have been constructed using analog circuits. Therefore, it is difficult to create a large-scale integrated circuit, which increases the number of parts, requires many adjustment points, increases cost, and raises concerns about reliability.

Therefore, by using a general-purpose digital computer, it is possible to provide an anti-skid device that does not require adjustment.

However, in-vehicle digital computers have a limited processing speed, and on the other hand, it is desirable to use digital computers to centrally control control items other than anti-skid control, such as automatic transmission control, constant vehicle speed control, etc. There are also demands. On the other hand, in anti-skid control, it is necessary to detect the skid state of the wheels and control the brake oil pressure and the actuator for release at extremely high speed, and controlling this with a single digital computer is especially complicated. If the machine also controls other control items, the computer load becomes excessive. Furthermore, if the anti-skid control system is malfunctioning, an extremely dangerous situation will occur in which braking becomes impossible or skid occurs during actual braking, so it is necessary to detect this malfunction in advance.

SUMMARY OF THE INVENTION An object of the present invention is to prevent the computer load from becoming excessive, and to detect failures in the anti-skid control system in advance. To provide a braking control device.

The present invention will be explained in detail below with reference to Examples. FIG. 1 shows the timing of solenoid activation and deactivation to disable the brakes for appropriate periods of time to prevent wheels from locking up. 101 shows how the actual wheel rotational speed ω _R changes. On the other hand, 102 indicates the estimated wheel speed ω _I. The control law is as follows: dω _R /dt<-K ₁ (K ₁ : Positive constant) (1) ω _I −ω _R /ω _I >K ₂ <K ₂ : Positive constant) (2) When the following two conditions are satisfied: , the above-mentioned solenoid is turned on to put the brake in a non-braking state, and this time point is designated as B. Also, if dω _R /dt>K ₃ (K ₃ : positive constant) (3) ω _I −ω _R /ω _I <K ₄ (K ₄ : positive constant) (4) holds, turn off the above solenoid. Then, the non-braking state is released, and this time is designated as C. As mentioned above, the solenoid is on for the periods B and C, and thereafter, if the above conditions are met again, the solenoid is turned on and off.

Next, a method for determining the estimated wheel speed ω _I shown at 102 in FIG. 1 will be described. When the solenoid is off and the actual wheel deceleration reaches a predetermined value as at point A, the wheel speed 102 decreases to a predetermined deceleration G from that point. However, while the solenoid is on, the estimated wheel speed value at the time the solenoid was turned on is held. Then, from the time the solenoid is turned off, the wheel speed 102 decreases again with the deceleration G.

FIG. 2 is a block diagram of a system in which a digital computer directly controls the solenoid. That is,
The digital computer 202 obtains the acceleration from the difference from the signal from the speed sensor 201, calculates the estimated speed, and determines the above conditions. The result is output to the solenoid 204 through the drive circuit 203. Then, the drive circuit measures the period during which the solenoid is on, and outputs a signal 205 to the computer 202 if the solenoid is on for a predetermined period or more. Further, if the solenoid is turned on while the brake pedal actuation signal 206 is off, the failure signal 205 is also output. Therefore, the computer also performs failure detection using the signal 205.

The calculation/judgment function of a computer will be described using the circuit shown in FIG. 3 as a representative example. In this example, if the signal 301 from the wheel speed sensor is a serial signal, it is counted by a counter 302 to obtain a parallel wheel speed signal. On the other hand, the output 314 of this counter 302 is stored in latch 303 with a delay. Adder 304 subtracts the past vehicle speed from the current vehicle speed. This output is therefore the difference in wheel speed, resulting in acceleration. Therefore, if this acceleration and the constant are determined by the comparator 305, it becomes one of the on/off conditions for the sonoid (1). However, as mentioned above, it is necessary to calculate the acceleration in (3) and the deceleration in (1), so the exclusive OR element 309
Invert the sign as appropriate.

On the other hand, the estimated wheel speed is calculated using the actual wheel speed 314.
This is done after presetting the down counter 306. A multiplier 307 is added to the output of this counter 306.
Multiply by a constant using . This output and the actual wheel speed are compared by a comparator 308, and conditional determination expressions (2) and (4) are executed. However, the output of comparator 308 is also (2)
As is clear from (4), the sign is inverted as appropriate. In this way, the above-mentioned determinations (1) to (4) are performed by appropriately changing the constants and signs as shown in FIG.

The output of the sign inverter is used to set and reset the flip-flop 311 by taking the AND conditions of (1) and (2) or (3) and (4) using an AND element. This output 3
12 is a signal that drives the solenoid. By the way, in order to obtain the estimated vehicle speed, the counter 306 counts down, but when the clock input 313 corresponding to the gradient G is applied to the counter 306 by means of a gate when the solenoid output 312 is off and the wheel acceleration is negative. do.

Next, we will discuss failure diagnosis. In addition to the drive circuit, the solenoid drive circuit 203 shown in FIG. 2 includes a circuit for checking the ON period of the solenoid.

This is shown in FIG. 4. A counter 401 counts a solenoid ON signal 404 using a clock 403. If the ON period is long, an overflow occurs and the signal 402 is used as an interrupt request signal 205. Also, if the brake pedal actuation signal 405 is turned off and the solenoid signal 404 is turned on, this is also treated as the interrupt request signal 205 because there is a circuit failure. When the computer receives this interrupt signal, it disables the solenoid drive circuit to prevent it from going into a non-braking state. In addition, the above detection function can be applied to the computer 20.
It is clear that it is also possible to have 2 itself have it.

Above, we have described an example in which the computer performs all the functions of acceleration calculation, solenoid on/off condition determination, and monitoring. This example does not require much external circuitry and has a simple device structure. On the other hand, the response speed of the anti-skid device is required to be quite high. If other vehicle control items also require high-speed computers, centralized computer control requires a high-speed computer, resulting in high costs. Therefore, if the required speed of other vehicle controls is high, it is more advantageous in terms of cost to use another dedicated computer to perform the anti-skid high-speed calculation section. Here, it is assumed that a dedicated peripheral processing unit determines the wheel acceleration, and that the central processing unit is responsible for other functions as before.

FIG. 5 is a diagram showing the configuration of the wheel speed detector 5.
05, the peripheral processing device 502 generates a wheel speed signal 506 and a wheel acceleration signal 507. The central processing unit 501 receives the signals 506, 50
7, the conditions (1) to (4) above are determined. The resulting solenoid on/off signal 508 is sent to the peripheral processing device. The solenoid drive circuit 503 drives the solenoid 504 by the drive circuit, and has the function described in FIG. 4 based on the brake operation signal 509 from the brake operation switch 510 and the like. Then, an interrupt request signal 511 indicating a failure is returned to the central processing unit 501. At this time, the central processing outputs a solenoid drive circuit invalidation signal 512. Therefore, the interior of the peripheral processing unit consists of the counter 302 and latch 303 shown in FIG. 3, and their control circuits, and the functions of the central processing unit can be expressed by the parts excluding 302 and 303 in FIG. Note that, as described above, the failure detection function shown in FIG. 4 may be provided in the central processing unit.

The above is an example of the division of functions between the central processing unit and peripheral processing units from a cost perspective. Next, an example of the division of functions from the perspective of reliability assurance is shown. As long as the central processing unit determines the on/off conditions of the solenoid, it is difficult for the central processing unit to detect an error in the determination. Therefore, in the embodiment of the present invention shown in FIG. 6, the arithmetic and judgment functions of the central processing unit are transferred to peripheral processing units, and the central processing unit specializes in failure detection.

When the configuration diagram is shown in FIG. 6, the wheel speed detector 60
From the signal No. 1, the peripheral processing device 604 outputs a solenoid on/off signal to the solenoid 605.
The central processing unit outputs a pseudo wheel speed signal 606 that can turn on and off the solenoid before driving, and confirms with a signal 609 that the solenoid is turned on. If the solenoid does not turn on at this time, there is a failure in the peripheral processing device 604, so a signal 608 is sent so that the peripheral processing device 604 does not operate in a fail-safe manner.
This means, for example, turning off the power of 604. Further, the peripheral processing unit performs the logic processing described in FIG. 4 from the signal from the brake (actuation) switch 602 and sends an interrupt request signal to the central processing unit. Note that, as described above, this function may be provided in the central processing unit.

Therefore, the peripheral processing device here includes the circuits shown in FIGS. 3 and 4 and the solenoid drive circuit. On the other hand, the functions of the central processing unit are shown in FIG. A clock 706 with a certain period is counted by a counter 701.
Count at . The output is decoded by a decoder 702 and used as an address of a storage element 703. The output of memory element 703 is preset into counter 704. The counter 704 is the clock 706
A clock 707 with a shorter predetermined synchronization is counted, and when the contents become all "1" or "0", a pulse is output to the output 705. When this pulse is again used as a preset signal 708, a pulse train with a period determined by the contents read from the storage element is outputted to 705. Therefore, if an appropriate number is written in the memory element, the frequency f of the pulse train of the output 705 will change every time the clock 706 is issued. In this embodiment, the memory element 70 is arranged so as to obtain a pulse train whose frequency f changes like the step-like waveform shown in FIG.
3, write a suitable value to the wheel speed detector 601, and write a pulse train of frequency changes like the curved waveform in FIG.
A condensed wheel speed signal 60 simulating a pulse train obtained from
Set it to 6.

FIG. 9 shows the configuration of the central processing unit 603 of FIG. 6. Control/computation unit 901, memory 90
6 and an input/output device 907 are connected by a data bus 902 and an address bus 903. The memory 906 also includes the storage element 703 shown in FIG. 7, and stores therein, in addition to values for obtaining the pseudo wheel speed signal, the program to be executed at 603 and the data used therein. First, when the interrupt request signal 904 is issued, the pre-running failure detection process described above is executed. That is, the control/arithmetic unit 901 includes a timer 905 (including the counter 704 in FIG. 7).
generates the pseudo wheel speed signal 606 shown in FIG. 8 using Execute the processing to be performed. Clock generators 908 and 909 generate clocks 706 and 707, respectively. The wheel speed signal 606 is supplied to the peripheral processing device, and as a result, if the signal 609 turns on within a predetermined period, it is determined that there is no failure and the failure detection process is terminated.
If 609 is not turned on within a predetermined period of time, the peripheral processing device 604 is abnormal, and a code 608 is sent to invalidate it. Furthermore, it is even better if the failure is indicated by the signal 608.

If a code indicating that a key switch (not shown) is turned on is used as the above-mentioned interrupt request signal 904, failure detection is automatically executed when the engine is started. In addition, a separate switch is provided to start failure detection, and the interrupt request signal 90 is activated by the driver's operation.
4 may be emitted. Once the pre-driving failure detection process described above is completed, the control/calculation unit performs other processes, such as controlling the automatic transmission's hydraulic valve on/off based on the engine throttle valve closing degree and vehicle speed. Execute processing such as An input 910 and an output 911 to the input/output device 907 indicate input/output for such other controls.

Furthermore, when an interrupt request signal 609 is input from the peripheral processing unit 604, the self-check of 604 indicates that an abnormality has occurred, so in this case as well, the peripheral processing unit is disabled and a signal 608 is issued to indicate a failure. Process.

As described above, according to the configuration of the present invention represented by the embodiment shown in FIG. 6, anti-skid control processing that requires high-speed processing is performed by a dedicated peripheral processing device, so that other controls can be performed intensively. This reduces the load on the central processing unit that operates the vehicle, and it is also possible to detect a failure in the anti-skid control function, which is extremely dangerous to vehicle operation, before the vehicle is driven, making it possible to obtain an extremely safe brake control system. .

[Brief explanation of the drawing]

Figure 1 is an explanatory diagram of the anti-skid control law.
FIG. 2 is a block diagram of a system in which a computer performs skid control and fault detection. FIG. 3 is a functional explanatory diagram of the computer, and FIG. 4 is a failure signal output circuit diagram in the solenoid drive circuit. FIG. 5 is a block diagram of an anti-skid device in which a peripheral processing device is provided with a differential function. FIG. 6 is a block diagram of a system in which the central processing unit performs only failure detection, FIG. 7 is an explanatory diagram of the pre-vehicle error detection function of the central processing unit, and FIG.
This figure is a function diagram of an error detection signal before the vehicle runs, and FIG. 9 is a diagram showing an example of the configuration of the central processing unit of FIG. 6. 101...Actual vehicle transport speed ω _R , 102...Estimated vehicle transport speed _ωI , 201...Vehicle transport speed detector, 202
... General-purpose digital computer, 203 ... Solenoid drive circuit, 204 ... Solenoid, 205 ...
Failure notification interrupt request signal, 206...brake activation signal, 301...signal from vehicle speed detector,
302...Counter, 303...Latch, 304
... Adder, 305 ... Comparator, 306 ... Down counter, 307 ... Multiplier, 308 ... Comparator, 309 ... Exclusive OR element, 310 ... Exclusive OR
Element, 311...Flip-flop, 312...
...Signal to solenoid, 313...Clock, 3
14...Vehicle transport speed signal, 315...Count signal, 401...Counter, 402...Interrupt request signal, 403...Clock, 404...Solenoid on/off signal, 405...Brake pedal operation signal, 501... ...Central processing signal, 502...
Peripheral processing signal, 503...Solenoid drive circuit,
504...Solenoid, 505...Vehicle speed detector, 506...Vehicle speed signal, 507...Vehicle acceleration signal, 508...Solenoid on/off signal, 509...Brake pedal operation signal, 51
0...Brake switch, 511...Interrupt request signal, 512...Solenoid drive circuit disabling signal, 601...Vehicle transport speed detector, 602...Brake switch, 603...Central processing unit, 60
4... Peripheral processing device, 605... Solenoid, 6
06... Pre-travel failure detection signal, 607... Interrupt request signal, 608... Solenoid drive circuit disabling signal, 609... Solenoid on/off signal,
701...Counter, 702...Decoder, 70
3...Storage element, 704...Breset possible counter, 705...Pre-travel failure detection signal, 706
...Clock, 707...Clock.

Claims (1)

[Claims] 1. A first digital computer programmed to output intermittent operation according to the amount of wheel slippage based on the actual wheel speed signal detected by the wheel speed detector, and a wheel failure detection system before the vehicle starts running. A speed signal is supplied to the first digital computer, and based on the braking signal at that time, it is determined whether or not there is a failure in the first digital computer, and if there is a failure, the intermittent operation is applied to the braking system of the vehicle. 1. A braking control device for a vehicle, comprising a second digital computer programmed to stop the control to be performed, and a second digital computer programmed to also perform other controls necessary for vehicle operation.