JPS62115554A - Storage protection system in multi-processor system - Google Patents

Abstract

PURPOSE:To detect a storage protection exception at an earlier point of time without requiring excess hardware by providing information for identifying each processor in a conversion table for dynamic address conversion. CONSTITUTION:In accessing a main storage device MSU, an address conversion buffer TLB is indexed at first, and when corresponding paired addresses exist, the device is accessed by using its real address. When no paired addresses exist in the TLB, a DAT table for dynamic address conversion is accessed to obtain a real address. In this case, processor identification information CPU-ID in the DAT table is read together with the real address in this case and compared with the information ID in the processor of an access sender. When dissident, it is discriminated as a storage protection exception or address conversion exception, an interruption is caused to apply proper processing. The CPU-ID is provided in the DAT table in this way, then the storage protection exception is detected at an earlier point of time without requiring excess hardware.

Description

[Detailed Description of the Invention] [Summary of the Invention] The present invention provides a multiprocessor system in which a plurality of processors commonly access a main memory device, and when the main memory device adopts a virtual memory method, an address The present invention relates to a storage protection method that uses a conversion table to prevent a virtual storage area specific to each processor from being undesirably changed by other processors.

[Prior art]

Traditionally, specific notes i! There are various methods for permitting access to an area only when specific conditions are met. However, in a commonly used storage protection method, a protection key is set for each real storage area, and permission/disapproval of access is determined based on the relationship with the key held by the access source. Therefore, if a virtual memory method is adopted, it is only after converting the virtual address to a real address and accessing the protection key memory based on the real address that it becomes clear whether or not it is accessible. This has the disadvantage that the time at which a memory protection exception is detected is delayed.

[Purpose of the invention]

The present invention aims to provide a storage protection scheme that allows detection of storage protection exceptions at an earlier point in time and does not require extra hardware for this purpose.

[Embodiments of the invention]

The figure is a block diagram showing one embodiment of the present invention, in which the CPU
#O and #1 are respective processors, MSU is a main memory commonly accessed by both processors, LAR is a register that holds virtual addresses, ID is a register that holds information that identifies each processor, COMP is a comparison circuit,
The TLB is an address translation buffer in which translation pairs of address translation results are registered, and the DAT table is a translation table for dynamic address translation, and corresponds to a so-called page table or segment table.

The improvement ID is originally provided in general for various purposes, and COMP can also be used as a general-purpose arithmetic unit, so there is virtually no need to add hardware.

The feature of the present invention is that each processor CPU#0. #1 is provided with an ID for identifying each, and CPU-ID information is also included in each storage location in the DAT table.

Generally, address translation pairs obtained twice are registered in the TLB,
Thereafter, the real address is obtained directly from the TLB. Also in the present invention, when accessing the main storage device,
First, the TLB is indexed, and if the address pair exists, the real address is used to access it. If, T.L.B.
If the access pair does not exist within the address range, the DAT table is accessed to obtain the real address. At this time, the CPU-ID is also read out along with the real address, and compared with the ID of the accessing processor. If they match, the corresponding real address is sent to the TLB.
All you have to do is register at , and access using that real address. If rD does not match, an interrupt is generated as a memory protection exception or an address translation exception, and appropriate processing is performed. Therefore, the address translation pair once registered in the TLB may be used as is.

The format of the CPU-ID is arbitrary, but if one only allows access exclusively to one processor,
°ζlog2N bits of information is sufficient for N processors, but a larger number of bits is required if it is necessary to permit an arbitrary number of processors.

Also, access permission/denial is determined by CPU-10.
It is not only possible to decide based on disagreement, but also based on size, etc.

Furthermore, it is also possible to apply the storage protection according to the present invention only to a specific virtual address range, and to employ storage protection using a normal protection key in other virtual address ranges.

〔effect〕

As described above, according to the present invention, the CPU is stored in the DAT table.
-10 is provided to permit access only to a specific processor, so memory protection exceptions can be detected at the time of address translation, making exception handling more efficient, and providing flexibility in the form of memory protection. It becomes possible.

[Brief explanation of drawings]

The figure is a block diagram of an embodiment of the present invention, in which CPU#,
0. #1 is a processor, MSU is a main memory commonly accessed by both processors, LAR is a register that holds virtual addresses, ID is a register that holds information that identifies each processor, COMP is a comparison circuit, T
LB is an address translation buffer for registering translation pairs of address translation results, and DA and T tables are translation tables for dynamic address translation.

Claims (1)

[Claims] In a multiprocessor system in which a plurality of processors share a virtual memory type main memory, access to the virtual address is permitted for each storage location in an address translation table that converts a virtual address to a real address. At the same time, each processor is made to hold information that identifies the processor concerned, and in address translation when accessing the main memory, the processor instruction information indicated by the address conversion table and the access 1. A storage protection method for a multiprocessor system, characterized in that access to a corresponding real address is permitted only when identification information of a processor that has generated the error has a predetermined relationship.