JPS6211387A - Digital convergence device - Google Patents

Abstract

PURPOSE:To decrease the capacity of a frame memory by storing the differential between a synchronizing signal's frequency and the convergence correction amount of a reference synchronizing signal when the said synchronizing signal of different frequency is inputted. CONSTITUTION:The frequency of the reference synchronizing signal is detected by a frequency detector circuit 24, and the detected frequency is stored. A switching circuit 28 is turned to side A and at the same time the output of a second frame memory 27 of an adder circuit 26 i stopped to let only the output of a first frame memory 10 pass, and the convergence correction amount is adjusted. When the detector circuit 24 detects a different synchronizing signal, the circuit 28 is set in side B, and the output of the second frame memory is set to be supplied to the circuit 26. Then the convergence correction amount at the specified adjusting point is read out from the memory 10 and inputted to a subtractor circuit 25. To another input terminal of the circuit 25, the output from a data reversible counter 11 via the switching circuit 28. Thereafter the content of the counter 11 is manually controlled from the control panel 12 through watching the screen, and is added to the subtractor circuit 25, where the differential from the data of the memory 10 is obtained, and it is written in a memory 27.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a device for correcting the convergence of a color television receiver, and is a low-cost device that can be adjusted with high precision and can sufficiently cope with input synchronization signals having different frequencies. This invention relates to a digital convergence device.

Conventional technology Generally, color television receivers have red and green.

An image is created by combining the three colors of blue on a fluorescent surface or a projected screen, but in this case, accurate alignment of the three colors and convergence adjustment affect the image quality. This is an important issue. Here, we will explain the convergence shift using a projection color television receiver as an example.

In FIG. 2, numeral 1 indicates a projection screen for projecting an image, and numerals 2, 3, and 4 are projection type cathode ray tubes each equipped with an optical lens for forming an image obtained on a fluorescent surface onto the projection screen 1. Fireflies, Tamer, and Appetizers! /7-1 Tode
If these cathode ray tubes are arranged horizontally as shown in the figure, their projection angles with respect to the projection screen 1 will be different, so the projected raster will be A positional shift as shown in FIG. 3 occurs for each color.

In FIG. 3, a solid line 31 shows a raster projected by the cathode ray tube 3 for green light, a broken line 4g shows a raster projected by the cathode ray tube 4 for blue light, and a dashed line 21 shows a raster projected by the cathode ray tube 2 for red light.

To correct this positional deviation, the projection type cathode ray tubes 2 and 3 must be
．． 4 is provided with a convergence adjustment coil separate from the main deflection coil, the amplitude of the sawtooth wave current in the horizontal scanning period is modulated in the vertical period, and the amplitude is adjusted independently for each color.

However, the amount of color shift varies due to variations in the mounting position of each cathode ray tube, variations in the configuration of the optical lens system, variations in the projection screen position, etc., so in order to perform high-precision convergence adjustment, a simple sawtooth shape is required. This is not possible with combinations of wave currents or parabolic currents.

As a method for realizing such convergence adjustment, a convergence circuit having a digital correction waveform forming section has been considered.

The conventional digital convergence device will be explained in detail below with reference to FIG.

Horizontal and vertical period pulses synchronized with the deflection current period are added as synchronization signals, thereby driving the read address control section 5. The pulses from the read address control section 6 are used to drive the crosshatch pattern generator 6 to project a crosshatch pattern onto the projection screen. Figure 2 shows a crosshatch pattern. On the other hand, use the address key on the control panel 12 to select the cross point at the position where convergence correction is required (for example, A in FIG. 4).
, and set the position address in the write address control unit 8. Next, using the data write key of the color to be corrected, for example, red provided on the control panel 12, write the correction amount into the one frame memory 10 through the data reversible counter 11 while looking at the screen. Normally, this one-frame memory writing is controlled by switching by the multiplexer 9 so that it is performed during the blanking period of the video signal. Therefore, reading is not impaired.

Similar operations are performed at each adjustment point as described above. Next, the readout of the one frame memory 10 is performed by the readout address control unit 5 for the cross position of each crosshatch on the screen, and then through the register 18 driven by the readout control unit 5, At step 13, correction amount processing in the vertical scanning direction between crosshatches is performed.

Next, the operation of this correction process will be explained with reference to FIGS. 5 and 6. The amount of correction for each scanning line between A and 8 or between C and 0 in FIG. 5 can be determined using the formula (A-B)K+A.

Here, K indicates a value obtained by linear approximation and is written in the ROM. Therefore, it is clear that K can be determined from the number N of scanning lines between A and 8. Further, the number of scanning lines N is determined from the number of scanning lines M in one field and the number of horizontal lines in the crosshatch.

Next, the correction amount processing between A and B in FIG. 5 will be explained with reference to FIG. The read address control unit 5 registers the υ1 deviation amount in registers 1 and 18 and registers 2 and 19. The output signals of registers 1 and 2 are converted to (A-B) by subtracter 2o.
is sent to the multiplier, multiplied by the coefficient for each scanning line to obtain (A-B)K, and the adder 23 calculates (A
-B) K+A is sent. In this way, the correction amount for the scanning line for which the correction amount is not stored is determined. Next, the output signal is converted into an analog quantity by the D/A converter 14. Next, it passes through the low-pass filter 15 and is applied to the output amplification circuit section 1θ, supplying a correction current to the convergence coil 17. Convergence adjustment at each adjustment point is performed as described above.

Problems to be Solved by the Invention However, in the above-mentioned configuration, when the input synchronization signals are different (for example, different models of personal computers, or NTSC and high-definition televisions), the input synchronization signals are different. The convergence correction amount was stored in the frame memory according to the frequency.

Therefore, the frame memory capacity increases and the cost increases by I+1.
This becomes an important problem when considering the diversification of signal sources.

In view of this, the present invention detects input synchronization signals, stores one of them as a reference synchronization signal, stores the convergence correction amount in the first frame memory, and when another synchronization signal is input. The convergence correction amount is stored in a second frame memory that stores the difference from the convergence correction amount of the reference synchronization signal, and the purpose is to reduce the capacity of the frame memory and provide a low-cost digital convergence device. shall be.

Means for Solving the Problems The present invention provides means for generating and displaying a plurality of convergence adjustment points in the horizontal and vertical directions on the screen of a color TV receiver, and an input means for inputting position information of the adjustment points. detection means for detecting the frequency of the synchronization signal input to the receiver;
a first storage means for storing a convergence correction amount at each adjustment point in a first frame memory using one of the synchronization signals detected from the output of the frequency detection means as a reference; and a first storage means for storing a convergence correction amount in the other synchronization signals as a reference. a subtraction means for subtracting the convergence correction amount of the synchronization signal, a storage means for storing the output in a second frame memory, and a first and a second frame memory.
This is a digital convergence device that is provided with an adding means for adding frame memory outputs.

Effects According to the present invention, when a different synchronization signal is input, the capacity of the frame memory can be reduced by storing the difference between the reference synchronization signal and the convergence correction amount.

Embodiment FIG. 1 shows a configuration diagram of a digital convergence device in an embodiment of the present invention. In FIG. 1, components that operate in the same manner as in the conventional example are designated by the same numbers, and explanations thereof will be omitted.

24 is a frequency detection circuit that detects the frequency of the synchronization signal;
6 is a subtraction circuit that calculates the difference between the convergence correction amount of the reference synchronization signal and the convergence correction amount of a different synchronization signal, 2θ is an addition circuit that adds the outputs of the first and second frame memories, and 27 is a subtraction circuit 26 28 is a switching circuit.

The operation of the convergence device having the above configuration will be explained below.

First, the convergence correction amount of the reference synchronization signal will be explained. The input synchronization signal is sent to frequency detection circuit 2.
4, the frequency of the reference synchronizing signal is stored, the switching circuit 28 is set to the A side, and at the same time, the output of the second frame memory 2 of the adder circuit 26 is stopped, and only the output of the first frame memory 10 is output. Let them understand, and then adjust the convergence correction amount in the same way as before. Next, the adjustment of the convergence correction amount when another synchronization signal is input will be explained.

First, when another synchronizing signal is detected by the frequency detection circuit 24, the switching circuit 28 is set to the front side, and the output of the second frame memory is further set to be added to the addition circuit 26. Next, the convergence correction amount at the adjustment point specified on the control panel is read out from the first frame memory and inputted into one leg of the subtraction circuit 25. For the other one, the output of the data reversible counter 11 is inputted via the switching circuit 28. Initially, if the data in the second frame memory 27 is 0, the contents of the data reversible counter 11 are set to the data in the first frame memory 10. Next, while looking at the screen as in the past, the contents of the data reversible counter 11 are controlled by the control panel 12, and are sequentially increased or decreased. Write to frame memory 27. Next, the second frame memory 27 is read out simultaneously with the first frame memory 10 by the read address control 5, and is supplied to the convergence coil 17 via the register 18, the adder amplifier circuit 16, and the convergence coil 17. As described above, convergence adjustment is performed by performing the same operation at each adjustment point.As described above, according to the present invention, the frequency of the input synchronization signal is detected by the frequency detection circuit 24, and the frequency of the input synchronization signal is detected. The difference between the data in the first frame memory 10 that stores the signal convergence correction amount and the convergence correction amount for other synchronization signals is calculated by the subtraction circuit 25 and stored in the second frame memory 27. However, for reading, by providing an adding circuit 26 that adds the outputs of the first and second frame memories 27 and sends the result, the capacity of the second frame memory 27 can be reduced, which has a great practical effect.

As described in detail, according to the present invention, it is possible to reduce the number of 7-frame memories, reduce costs, and shorten the adjustment time.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of a digital convergence device according to an embodiment of the present invention, Fig. 2 is a principle diagram of a projection type color TV receiver, Fig. 3 is a diagram for explaining the convergence deviation, and Fig. 4 is FIG. 5 is a block diagram of a conventional digital convergence device, FIG. 5 is a pattern diagram for explaining the device, and FIG. 6 is a block diagram of a part of the device for explaining the operation of the device. 5... Read address control section, 6...
・Crosshatch generator, 7... Video circuit, 8.
...Write address control unit, 9...Multiplexer, 10...First frame memory,
11... Data reversible counter, 12...
・Control channel, 18...Register, 2
4... Frequency detection circuit, 26... Subtraction circuit, 26... Addition circuit, 27... Second frame memory, 28... switching circuit. Name of agent: Patent attorney Toshio Nakao and 1 other person 2nd
Figure 3

Claims (1)

[Claims] Display means for displaying a plurality of convergence adjustment points horizontally and vertically on the screen of a color television receiver; input means for inputting position information of the adjustment points; and a frequency of a synchronization signal input to the receiver. a first storage means for storing a convergence correction amount corresponding to the adjustment point based on at least one of the synchronization signals detected by the detection means; a subtraction means for subtracting the convergence correction amount from the convergence correction amount of the reference synchronization signal; a second storage means for storing the output of the subtraction means; reading out the first storage means and the second storage means; A digital convergence device characterized in that it is provided with an addition means.