JPS62108282A - Image display unit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention is directed to sequentially extracting data signals of image information such as computer graphics from an image frame memory through a shift register, and transmitting the data signals to the image receiving surface of an image display element such as a picture tube. The present invention relates to an image display device that displays the image information.

BACKGROUND ART As shown in FIG. 5, image information such as characters and figures is generally displayed on a fluorescent screen 2 of an image display element 1 consisting of a picture tube with a pixel configuration of m horizontal columns and n vertical rows. ing. In this case, as shown in FIG. 6, the image information data signals stored in the image frame memory 3 at predetermined addresses are taken out one by one and applied to the shift register 4 in parallel. This data signal taken out in series is applied to the video amplifier 5, and the image display element 1 is moved once to display the image information on the fluorescent screen 2. However, the transfer of the data signal from the image frame memory 3 to the shift register 4 is performed by a load pulse, and the extraction of the data signal from the shift register 4 is synchronized with the clock pulse shown in FIG. 7(a). It is done. .

FIG. 7(b) schematically shows the output of the shift register 4, where the data signal is 1, which takes either a high level or a low level state, and Dl indicates the data signal at the AbiLevu address 1.

Problems to be Solved by the Invention The image display capability (number of pixels mxn) of the image display device configured as described above depends on the data processing speed of the shift register 4. Since the display of image information tends to handle increasingly complex figures in the future, it is expected that the number of required pixels will increase dramatically in the future. Therefore, various efforts have been made to increase the processing speed of shift registers, but these have not yet fully met the requirements.

Therefore, an object of the present invention is to provide an image display device capable of displaying an image with a large number of pixels while using a conventional shift register. , distributes and supplies image information data signals in predetermined units taken out in parallel from the image frame memory to a plurality of shift registers, shifts these shift registers using clock pulses of different phases, and serially outputs data from the plurality of shift registers. The signals taken out are synthesized in time series to obtain a signal for driving one image display element.

Effect With this configuration, the signal retrieval process from the image frame memory is shared by multiple shift registers, and even if the signal processing speed of each shift register is the same as before, the processing speed will be significantly reduced. It becomes possible to display images using the number of pixels.

Embodiment An embodiment of the present invention is shown in FIG. A large number of signal output terminals of the image frame memory 6 are alternately connected to the first and second shift registers 7.8, so that odd-numbered image information data signals are transmitted from the image frame memory 6 to the first shift register 7. Riji J.

D5 . . . Dl-1, and the second shift register 8 receives even-numbered image information data signals D2 . D4.
D6...Dl are respectively input. on the other hand,
The clock pulse shown in FIG. 2(a) is input to the phase inversion circuit 9, and the phase-inverted clock pulse shown in FIG. 2(b) is taken out from the phase inversion circuit 9. These two types of clock pulses (IL) and (b) are applied to the first and second shift registers 7.8 as shift pulse signals, respectively, and are triggered at the falling edge of these pulse signals. However, in order to stably transfer the data signal, the pulse signal width is shifted during the latter half of the period.

The outputs of both soft registers 7.8 are shown in FIG. 2(C).

f(1), which is the complement of the image information data signal, and each NOR
The signal is applied to one signal input terminal of each of the gate circuits 9 and 1o. The clock pulse shown in (2L) in FIG. 3 is input to the other signal input terminal of the first NOR gate circuit 9, and the clock pulse shown in (2L) of FIG. 3 is input to the other signal input terminal of the second NOR gate circuit 1o. A clock pulse shown in FIG. 3(b) is input. As a result, the image information data signal shown in (6) of FIG. 3 is output from the first NOR gate circuit 9, D5...
... are taken out with a duty of 1/2 in response to the clock pulse, and the image information data signal D2. D4
・River... is taken out with a duty of 1/2 in response to the relevant clock pulse.

And both image information data signals (6), <f) are
By bending the OR gate circuit 11, a complete image information data signal as shown in FIG. 3(g)K is obtained by chronologically synthesizing the data signal (g), Odd-order and even-order data signals are alternately intermingled every half period of the clock pulse (a).

The present inventors have determined that m=1664°n=1 on the fluorescent screen of the picture tube.
To display image information with 248 pixels, 128 pieces of 16 bits are used as the image frame memory 6, and eight pieces of 4 bits each (cascaded) are used as the first and second shift registers 7.8. connection) was used. In this case, data signals can be taken out in series from the OR gate circuit 11 in units of 1 = 64, and high-resolution images with a large pixel configuration of 1664 x 124 B dots can be produced without flickering at a frame frequency of 60 H2 using 190 MHz pulses. I was able to display it.

Note that it goes without saying that a liquid crystal type or the like can be used as the image display element.

Another embodiment of the invention is shown in FIG. In this case, the first to fourth shift registers 12, 13,
14.15 is used, and from the phase shift circuit 16 (&
) and the clock pulse (C) shown in FIG. The clock pulses shown in (b) and (d) are respectively taken out. When the load pulse and the clock pulse are applied to the first to fourth shift registers 12 to 15, the image information data signals D1 to Di from the image frame memory 19 are transferred to the first to fourth shift registers 12 to 15.
16, and from the first to fourth shift registers 12 to 16, (+5) to (
An image information data signal schematically shown in 1L) is extracted. However, the trigger is performed at the falling edge of the clock pulse, and the data signal is shifted during the last 1/4 period of the clock pulse.

Therefore, the first to fourth NOR gate circuits 20 to 2
From 3? The data signals shown in (1) to () in FIG. , OR gate circuit 2
4, a complete image information data signal shown in FIG. 4(m) is taken out, and the apparent data processing speed of the shift register is increased four times that of the conventional one.

Effects of the Invention Since the present invention is configured as described above, although it requires a plurality of shift registers, the apparent data processing speed of the shift registers can be increased, so high resolution images can be displayed with a large number of pixels. becomes.

[Brief explanation of drawings]

FIG. 1 is a block diagram of main parts of an image display device embodying the present invention, (8L) to (g) in FIG. 2 are signal waveform diagrams in each part of the device, and FIG. 3 is another embodiment of the present invention. A block diagram of the main parts of the example, (a) to fm) of FIG. 4 are signal waveform diagrams of each part in the same example, and FIG. Fig. 6 is a block diagram of a conventional image display device, and Fig. 7 fa), (
b) is a signal waveform diagram of each part of the device. 6.19...Image frame memo IJ, 7, 8
．． 12゜13.14.15・・・Shift register,
9, 17゜18... Phase inversion circuit. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 2 (3) Dr 02 1'J
D4 Figure 3 Figure 4 [d,) (yyt2v, D2 ρ,
D, D. Figure 5

Claims (1)

[Claims] The image information data signals taken out in parallel from the image frame memory in predetermined units are distributed and supplied to a plurality of shift registers, and the shift registers are operated by clock pulses of different phases, and the data signals are read in series from the plurality of shift registers. An image display device characterized in that a signal for driving an image display element is obtained by chronologically synthesizing the output signals.