JPS6199354A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS6199354A JPS6199354A JP59199561A JP19956184A JPS6199354A JP S6199354 A JPS6199354 A JP S6199354A JP 59199561 A JP59199561 A JP 59199561A JP 19956184 A JP19956184 A JP 19956184A JP S6199354 A JPS6199354 A JP S6199354A
- Authority
- JP
- Japan
- Prior art keywords
- pellet
- upper edge
- resin
- collet
- angle
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 24
- 239000008188 pellet Substances 0.000 claims abstract description 49
- 239000011347 resin Substances 0.000 claims abstract description 24
- 229920005989 resin Polymers 0.000 claims abstract description 24
- 238000004806 packaging method and process Methods 0.000 claims abstract 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 5
- 229910052710 silicon Inorganic materials 0.000 abstract description 5
- 239000010703 silicon Substances 0.000 abstract description 5
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical group [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 abstract description 3
- 229910052737 gold Inorganic materials 0.000 abstract description 3
- 239000010931 gold Substances 0.000 abstract description 3
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 abstract description 3
- 230000005496 eutectics Effects 0.000 abstract description 2
- 238000010438 heat treatment Methods 0.000 abstract 1
- 239000011800 void material Substances 0.000 abstract 1
- 238000000034 method Methods 0.000 description 6
- 230000035882 stress Effects 0.000 description 4
- 230000007547 defect Effects 0.000 description 3
- OFLYIWITHZJFLS-UHFFFAOYSA-N [Si].[Au] Chemical compound [Si].[Au] OFLYIWITHZJFLS-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 230000001154 acute effect Effects 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 230000008646 thermal stress Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/1015—Shape
- H01L2924/10155—Shape being other than a cuboid
- H01L2924/10156—Shape being other than a cuboid at the periphery
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/1015—Shape
- H01L2924/10155—Shape being other than a cuboid
- H01L2924/10157—Shape being other than a cuboid at the active surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔技術分野〕
本発明は半導体装置に関し、特に半導体素子ベレットの
形状を改善して信頼性の向上を図った半導体装置に関す
るものである。DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a semiconductor device, and more particularly to a semiconductor device whose reliability is improved by improving the shape of a semiconductor element pellet.
半導体装置を構成する素子ペレットは、一般に半導体ウ
ェーハに多数個の素子を形成し、所定の検査後にこれを
各素子毎に切断（ダイシング）すＺ）ことにより得られ
ている。ところで、このダイシングに際してはダイシン
グブレードを用いて半導体ウェーハを全厚さにわたって
切断する方法、或いはウェーハの表面部にのみこのブレ
ードで切込みを入れた上で残りの部分を剪断させる方法
等が利用されているが、いずれの方法でもウェーハの表
面部ではブレードによる切断が行なわれるため、略方形
に切断された各素子ペレットの上縁部は直角又はこれに
近い鋭利な角状に形成される。Device pellets constituting a semiconductor device are generally obtained by forming a large number of devices on a semiconductor wafer, and dicing each device after a predetermined inspection. By the way, when performing this dicing, a method is used in which a dicing blade is used to cut the semiconductor wafer over its entire thickness, or a method in which the blade is used to cut only the surface portion of the wafer and the remaining portion is sheared. However, in either method, the surface of the wafer is cut with a blade, so the upper edge of each element pellet cut into a substantially rectangular shape is formed into a right angle or a sharp angle close to this.
このため、このような素子ペレットをパッケージベース
にボンディング丁べ（コレットにて握持すると、第１１
図に示すようにコレットＣのテーバ状（角すい状）内面
Ｃａとペレッ）Ｐの上縁Ｐａとが当接した際にペレット
上縁Ｐａに極めて容易に欠けが生じ易い。そして、この
欠けたシリコン片カハッケージペースの金めつきされた
リードＬ上に付着するとここで金シリコン共晶などを生
じ、次の工程であるワイヤポンディングにおいてリード
上へのワイヤの接続不良を生じ、信頼性を低下させるこ
とになる。Therefore, when gripping such an element pellet with a bonding knife (collet) on the package base, the 11th
As shown in the figure, when the tapered (pyramidal) inner surface Ca of the collet C comes into contact with the upper edge Pa of the pellet P, the upper edge Pa of the pellet is very easily chipped. When this chipped piece of silicon adheres to the gold-plated lead L of the cage paste, gold-silicon eutectic etc. are generated, which may cause a poor connection of the wire to the lead in the next process of wire bonding. This will reduce reliability.
また、上縁Ｐａの鋭いベレットＰを第１２図のようにレ
ジンＲ材にてモールドパッケージすると、レジンＲの熱
履歴時にレジンＲとベレットＰとの熱膨張率差に伴なう
熱応力がこの上縁Ｐ’ａ近傍に作用し、レジンＲにクラ
ックＣＬが発生してベレットＰへの水の浸透を容易にし
、耐湿性を低下させることにもなる。In addition, when a pellet P with a sharp upper edge Pa is molded and packaged with a resin R material as shown in Fig. 12, thermal stress due to the difference in thermal expansion coefficient between the resin R and the pellet P during the thermal history of the resin R is caused by this material. This acts near the upper edge P'a, causing cracks CL to occur in the resin R, making it easier for water to penetrate into the pellet P, and reducing moisture resistance.
なお、特開昭４９−１０５４６７号公報にメサ型半導体
装置が開示されているが、この構成においても前述の問
題を回避することは難かしい。Although a mesa-type semiconductor device is disclosed in Japanese Patent Application Laid-Open No. 49-105467, it is difficult to avoid the above-mentioned problems even in this configuration.
１ 本発明の目的は素子ベレットにおける
欠けを未然に防止してワイヤボンディング等の不良防止
を図ると共に、レジンモールドにおけるレジンクラック
の発生を防止し、これによりポンディングおよび耐湿性
等の信頼性の向上を達成することのできる半導体装置を
提供することにある。1. The purpose of the present invention is to prevent defects in wire bonding and the like by preventing chipping in element pellets, and also to prevent resin cracks from occurring in resin molds, thereby improving reliability in terms of bonding and moisture resistance. An object of the present invention is to provide a semiconductor device that can achieve the following.
本発明の前記ならびにそのほかの目的と新規な特徴は、
本明細書の記述および添付図面からあきらかになるであ
ろう。The above and other objects and novel features of the present invention include:
It will become clear from the description of this specification and the accompanying drawings.
本願において開示される発明のうち代表的なものの概要
を簡単に観明すれば、下記のとおりである。A brief overview of typical inventions disclosed in this application is as follows.
すなわち、半導体素子ベレットの上縁部を平面テーパ状
ないし上方に向って緩やかな凸状に形成しており、更に
好ましくは平面テーパ状の角度をコレットの内面角度に
一致させ、また上方に向かう曲面状に形成すること属よ
り、コレットとベレットとの当接によってもベレット欠
けが生じることなく、ワイヤポンディング不良の防止を
図る一方で、レジンモールドにおけろレジンクラックを
防止して耐湿性の向上を図ることができ、これにより半
導体装置の信頼性を向上できる。That is, the upper edge of the semiconductor element pellet is formed into a planar taper shape or a gently upwardly convex shape, and more preferably, the angle of the planar taper shape matches the inner surface angle of the collet, and the upwardly curved surface is formed. Since it is formed into a shape, there will be no pellet chipping due to contact between collets and pellets, preventing wire bonding defects, and improving moisture resistance by preventing resin cracks in resin molds. This makes it possible to improve the reliability of the semiconductor device.
〔実施例１〕
第１図は本発明の一実施例における素子ペレットを示し
ており、シリコンウェーハ上に多数の素子を桝目状に形
成した上でこれをダイシングブレードにより夫々方形に
切断して形成している。そして、この素子ペレット１は
上面に所要の回路パターン２を形成しているが、その周
辺の上縁部３は図示のように平坦なテーパ状の面となる
ように形成している。このようなベレット１を形成する
ための方法としては、例えば第２図のように、ブレード
４の断面形状なテーパ状の厚刃５と、その外周面中央に
外方に向って突出された薄刃６とで構成し、厚刃５がウ
ェーハ７の主面よりも若干くい込むような深さで切断を
行なえばよい。あるいは、第３図囚のように楔状の厚刃
８を有するブレード９でウェーハ７に浅く切込みを入れ
た上で、同図［Ｆ］）のように薄刃１０のブレード１１
で完全切断してもよい。[Example 1] Figure 1 shows an element pellet in one example of the present invention, which is formed by forming a large number of elements in a square shape on a silicon wafer and then cutting each element into squares with a dicing blade. are doing. The element pellet 1 has a required circuit pattern 2 formed on its upper surface, and the upper edge 3 around the circuit pattern 2 is formed into a flat tapered surface as shown in the figure. For example, as shown in FIG. 2, a method for forming such a pellet 1 is to use a tapered thick blade 5 having a cross-sectional shape of the blade 4, and a thin blade protruding outward at the center of the outer peripheral surface of the blade 4. 6, and the cutting may be performed at a depth such that the thick blade 5 penetrates slightly deeper than the main surface of the wafer 7. Alternatively, after making a shallow incision in the wafer 7 with a blade 9 having a wedge-shaped thick blade 8 as shown in FIG.
You can cut it completely.
したがって、このベレットｌのテーパ面３０角度をコレ
ットの角錐状内面の角度（例えば４５°）に設定してお
けば、第４図のように、パッケージペースとしてのリー
ドフレーム１２のタブ１３上にベレットｌを固着（ペレ
ットボンディング）する際にコレット１４でベレット１
を握持しても、コレット内面１５とベレットテーパ面３
とは正対して面接触状態とされるため、ベレット１の上
縁部において欠けが生じることはない。これにより、ベ
レット１をリードフレーム１２に固着してもシリコン片
がリード１６の金めつき上に付着して金シリコン共品を
作ることもなく、第５図のように良好なワイヤ１７の接
続を施し、かつレジン１８によりてモールド１９を完成
できる。そして、この状態にあっても、ベレット１とレ
ジン１８の界面に鋭角部が存在しないので、熱履歴を受
けてレジン１８とベレット１の間に熱膨張率差に伴なう
応力が生じてもこれが上縁部に集中することはなく、し
たがってレジンクラックの発生が防止できる。クラック
の発生を防止することにより、クラックを通しての水の
浸透を防止でき、耐湿性の向上が達成できる。Therefore, if the angle of the tapered surface 30 of the pellet L is set to the angle of the pyramidal inner surface of the collet (for example, 45 degrees), the pellet can be placed on the tab 13 of the lead frame 12 as a package paste, as shown in FIG. When bonding (pellet bonding) L, collet 14 is used to attach pellet 1.
Even if you grip it, the collet inner surface 15 and the bullet tapered surface 3
Since the upper edge of the pellet 1 is in face-to-face contact with the upper edge of the pellet 1, no chipping occurs at the upper edge of the pellet 1. As a result, even if the bullet 1 is fixed to the lead frame 12, silicon pieces will not adhere to the gold plating of the leads 16 and create a gold-silicon product, and the wire 17 can be connected well as shown in FIG. The mold 19 can be completed using the resin 18. Even in this state, there is no acute angle at the interface between the pellet 1 and the resin 18, so even if stress due to the difference in thermal expansion coefficient occurs between the resin 18 and the pellet 1 due to thermal history, This does not concentrate on the upper edge, thus preventing resin cracks from occurring. By preventing the occurrence of cracks, water penetration through the cracks can be prevented and moisture resistance can be improved.
なお、コレット内面角が垂直又は水平に近いときには、
第６図のベレットｌＡのように２段のテーバ面３Ａ、３
Ｂの構造としてもよい。但し、この場合にはペレッ）Ｉ
Ａの上縁部は全体として上方に向かりて凸状にすること
が肝要である。In addition, when the collet inner surface angle is close to vertical or horizontal,
Two stages of taber surfaces 3A, 3 like the bellet lA in Fig. 6
Structure B may also be used. However, in this case, Peret) I
It is important that the upper edge of A is convex upward as a whole.
〔実施例２〕
第７図は本発明の他の実施例を示しており、前例と同じ
ように半導体ウェーハを切断して略方形に形成した素子
ベレット２１の上縁部を、ここでは上方に向かって緩や
かに突出した曲面２３に形成している。すなわち、第８
図のように、曲面２３の曲率半径Ｒをペレットサイズと
回路パターン２２面サイズとに照らして可及的に太き（
なるように構成している。このベレット２１の製造には
前例の第２図、第３図と同様の方法が採用でき、ブレー
ド４．９の厚刃５．８の両側面形状を曲面に形成してお
けばよい。[Embodiment 2] FIG. 7 shows another embodiment of the present invention, in which the upper edge of the element pellet 21, which is formed into a substantially rectangular shape by cutting a semiconductor wafer in the same way as in the previous example, is cut upward. It is formed into a curved surface 23 that gently protrudes toward the surface. That is, the eighth
As shown in the figure, the radius of curvature R of the curved surface 23 is set as thick as possible (
It is configured so that This pellet 21 can be manufactured by a method similar to that shown in FIGS. 2 and 3 of the previous example, and it is sufficient to form both side surfaces of the thick edge 5.8 of the blade 4.9 into curved surfaces.
このベレット２１によれば、第８図のようにリードフレ
ーム２４のタブ２５への固着に際し、コレット２６の内
面２７０角度が異なっていても曲面２３の接線状態でこ
れに当接するので容易に追従（適合）でき、ベレット欠
けを有効に防止できる。これにより、第９図のようにリ
ードフレーム２４上に素子ペレット２１を固着しかつり
−ド２８との間にワイヤ２９の接続を行なえば、信頼性
の高いワイヤ接続構造が得られる。また、レジン３０に
てモールドした場合にも、同図のようにベレット２１の
上縁部が曲面であることから応力集中は生ぜず、クラッ
クが生ずることもない。According to this bellet 21, when the lead frame 24 is fixed to the tab 25 as shown in FIG. 8, even if the angle of the inner surface 270 of the collet 26 is different, the collet 26 contacts the curved surface 23 in a tangential state, so it can easily follow ( ) and can effectively prevent beret chipping. Thereby, by fixing the element pellet 21 on the lead frame 24 and connecting the wire 29 to the lead frame 28 as shown in FIG. 9, a highly reliable wire connection structure can be obtained. Furthermore, even when molded with the resin 30, since the upper edge of the pellet 21 is a curved surface as shown in the figure, no stress concentration occurs and no cracks occur.
なお、本例では、第１Ｏ図に一部を拡大して示すように
、プレス成形したリードフレーム２４の各端部、特にプ
レス抜きしたときに生ずるパリ部（図に鎖線で示す）２
４ａが形成される端縁部２４ｂに面取りを施している。In this example, as shown in FIG. 1O in a partially enlarged manner, each end of the press-formed lead frame 24, especially the paring part (shown by a chain line in the figure) 2 that occurs when punched out, is shown in FIG.
The edge portion 24b where the ridge 4a is formed is chamfered.
この面取りによって前述と同様に応力の集中を防止し、
レジン３０のクラックの発生を防止できる。This chamfer prevents stress concentration as mentioned above,
Cracks in the resin 30 can be prevented from occurring.
（１） 素子ペレットの上縁部をテーパ状に形成して
いるので、コレット内面との当接が面接触に近（なり、
ベレットの欠けを防止でき、この欠けがリード部に付着
することによって生ずるワイヤボンディング不良を未然
に防止できる。(1) Since the upper edge of the element pellet is tapered, the contact with the inner surface of the collet is close to surface contact.
It is possible to prevent the bullet from chipping, and it is possible to prevent wire bonding defects caused by the chipping from adhering to the lead portion.
（２）前記テーバ状の面の角度をコレット内面の角度に
一致させているので完全な面接触となり、欠けの防止効
果を向上できる。(2) Since the angle of the tapered surface is made to match the angle of the inner surface of the collet, complete surface contact is achieved and the effect of preventing chipping can be improved.
（３）ペレットの上縁部を２個のテーパ面ないし曲面で
構成してこの部位を上方に緩やかに突出した形状として
いるので、コレットの内面の角度が異なる場合にも面に
近い状態で当接でき、欠けを有効に防止できる。(3) The upper edge of the pellet is composed of two tapered or curved surfaces, and this part is shaped to gently protrude upward, so even if the angle of the inner surface of the collet is different, the collet can still be hit close to the surface. It is possible to effectively prevent chipping.
（４）ベレットの上縁部をテーパ状２曲面状等と、上方
に向った緩やかな突状に形成しているのでベレットに鋭
角部は存在しなくなり、したがってレジン等にてそ−ル
ドを施した場合にも応力の集中は防止できレジンクラッ
クを防止できる。(4) Since the upper edge of the pellet is formed into a tapered bicurved shape, etc., and a gentle upward protrusion, there is no sharp corner on the pellet, and therefore it can be shielded with resin, etc. Even in such cases, stress concentration can be prevented and resin cracks can be prevented.
（５）前記（１）〜（５）によりワイヤボンディングの
信頼性を向上すると共にクラック防止に伴なう耐湿性を
向上でき、半導体装置全体の信頼性を向上できる。(5) With the above (1) to (5), it is possible to improve the reliability of wire bonding, and also improve the moisture resistance associated with crack prevention, and improve the reliability of the entire semiconductor device.
以上本発明者によってなされた発明を実施例にもとづき
具体的に説明したが、本発明は上記実施例に限定される
ものではな（、その要旨を逸脱しない範囲で種々変更可
能であることはいうまでもない。たとえば、上縁部は３
個以上のテーパ面で構成してもよ（、また曲面は円弧面
以外の断面形状であってもよい。Although the invention made by the present inventor has been specifically explained above based on examples, the present invention is not limited to the above-mentioned examples (although it is possible to make various changes without departing from the gist of the invention). For example, the top edge is 3
(Also, the curved surface may have a cross-sectional shape other than a circular arc surface.)
以上の説明では主として本発明者によりてなされた発明
をその背景となった利用分野であるレジンモールド型の
半導体装置に適用した場合について説明したが、それに
限定されろものではな（、セラミックパッケージ型半導
体装置やその外のワイヤボンディングを施す半導体装置
に適用できる。In the above explanation, the invention made by the present inventor was mainly applied to a resin mold type semiconductor device, which is the background field of application, but it is not limited thereto (ceramic package type, etc.). It can be applied to semiconductor devices and other semiconductor devices that undergo wire bonding.
第１図は本発明の一実施例のベレットの斜視図、第２図
は製造方法の一例の断面図、
第３図囚、 ＣＢ）は他の製造方法の断面図、第４図は
ペレット固着状態の断面図、
第５図は完成状態の断面図、
第６図は変形例の断面図。
第７図は他の実施例のベレットの斜視図、第８図はペレ
ット固着状態の断面図、
第９図は完成状態の断面図、
第１０図は一部の拡大図、
第１１図および第１２図は従来の不具合を説明するため
の図であり、第１１図はペレット固着状態、第１２図は
完成状態を示す各断面図である。
１・・・ペレット、３．３Ａ、３Ｂ・・・テーパ面、４
゜９．１１・・・ブレード、１２・・・リードフレーム
、１４・・・コレット、１５・・・コレット内面、１７
・・・ワイヤ、１８・・・レジン、２１・・・ペレット
、２３・・・曲面、２４・・・リードフレーム、２６・
・・コレット、２７・・・コレット内面、２９・・・ワ
イヤ、３０・・・レジン、Ｐ・・・ペレット、Ｃ・・・
コレット、Ｌ・・・リード、ＣＬ・・・クラック、Ｒ・
・・レジン。
第 １ 図
第 ２ 図
第 ３ 図
ｉ、に、、０
第 ４ 図
第 ６ 図
Ｉ／Ａ
第 ７ 図
第 ８ 図Fig. 1 is a perspective view of a pellet according to an embodiment of the present invention, Fig. 2 is a cross-sectional view of an example of the manufacturing method, Fig. 3 is a cross-sectional view of another manufacturing method, and Fig. 4 is a pellet fixation. 5 is a sectional view of the completed state, and FIG. 6 is a sectional view of a modified example. Fig. 7 is a perspective view of a pellet of another embodiment, Fig. 8 is a sectional view of the pellet in a fixed state, Fig. 9 is a sectional view of the completed state, Fig. 10 is a partially enlarged view, Fig. 11 and FIG. 12 is a diagram for explaining conventional problems, FIG. 11 is a sectional view showing a pellet fixed state, and FIG. 12 is a sectional view showing a completed state. 1... Pellet, 3.3A, 3B... Tapered surface, 4
゜9.11...Blade, 12...Lead frame, 14...Collet, 15...Collet inner surface, 17
... wire, 18 ... resin, 21 ... pellet, 23 ... curved surface, 24 ... lead frame, 26 ...
...Collet, 27...Collet inner surface, 29...Wire, 30...Resin, P...Pellet, C...
Collet, L... lead, CL... crack, R...
...Resin. Figure 1 Figure 2 Figure 3 Figure i...0 Figure 4 Figure 6 I/A Figure 7 Figure 8
Claims (1)
に向かって緩やかな凸状に形成し、この素子ペレットに
ワイヤボンディングを施しかつパッケージしたことを特
徴とする半導体装置。 ２、テーパ面の角度は、コレットの内面の角に一致せて
なる特許請求の範囲第１項記載の半導体装置。 ３、上縁部を上方に突出した曲面に構成してなる特許請
求の範囲第１項又は第２項記載の半導体装置。 ４、素子ペレットをレジンモールドでパッケージしてな
る特許請求の範囲第１項ないし第３項のいずれかに記載
の半導体装置。[Scope of Claims] 1. A semiconductor device characterized in that the upper edge of a semiconductor element pellet is formed into a tapered surface or gently convex upward, and the element pellet is wire-bonded and packaged. 2. The semiconductor device according to claim 1, wherein the angle of the tapered surface matches the angle of the inner surface of the collet. 3. The semiconductor device according to claim 1 or 2, wherein the upper edge portion is formed into a curved surface projecting upward. 4. A semiconductor device according to any one of claims 1 to 3, which is formed by packaging an element pellet with a resin mold.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59199561A JPS6199354A (en) | 1984-09-26 | 1984-09-26 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59199561A JPS6199354A (en) | 1984-09-26 | 1984-09-26 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6199354A true JPS6199354A (en) | 1986-05-17 |
Family
ID=16409871
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59199561A Pending JPS6199354A (en) | 1984-09-26 | 1984-09-26 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6199354A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63262834A (en) * | 1987-04-20 | 1988-10-31 | Nec Corp | Ic pellet |
| JP2005101673A (en) * | 2005-01-11 | 2005-04-14 | Matsushita Electric Ind Co Ltd | Semiconductor device |
| KR100559649B1 (en) * | 2000-12-26 | 2006-03-10 | 마츠시타 덴끼 산교 가부시키가이샤 | Semiconductor device |
-
1984
- 1984-09-26 JP JP59199561A patent/JPS6199354A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63262834A (en) * | 1987-04-20 | 1988-10-31 | Nec Corp | Ic pellet |
| KR100559649B1 (en) * | 2000-12-26 | 2006-03-10 | 마츠시타 덴끼 산교 가부시키가이샤 | Semiconductor device |
| JP2005101673A (en) * | 2005-01-11 | 2005-04-14 | Matsushita Electric Ind Co Ltd | Semiconductor device |
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