JPS6199190A - Video memory unit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] This invention is applicable to, for example, a 256-bit dynamic RA.
The present invention relates to a video memory device suitable for constructing a frame memory using M.

[Conventional technology]

Frame memory has conventionally been comprised of 64 64-bit dynamic RAMs.

For example, if the sampling period of the digital video signal is 70
At the time of n5ec, it was not possible to write and read digital video signals in real time due to the access time constraints of dynamic RAM, so the input digital video signal could not be read or written in real time. It was configured to parallelize each Jj W & sample data.

By the way, due to advances in semiconductor technology, 256
Dynamic RAM is becoming relatively easy to obtain. However, the access time is still insufficient, and it is necessary to perform parallelization processing at the time of writing and serialization processing at the time of reading.

[Problem that the invention seeks to solve]

When a large number of dynamic RAMs are used in the past, and input digital video signals are written in parallel and read out in serial, the scale of the hardware becomes large.
This has the disadvantage that timing control becomes troublesome and furthermore, it becomes difficult to check the circuit.

For example, the present invention provides a dynamic RA of 256 bits.
To provide a video memory device capable of writing one frame of a video signal as serial data without changing the time axis using M.

[Means for solving problems]

The video memory device of the present invention has a dynamic RAM divided into two groups, and a column address strobe signal CAS of opposite phase to each group is supplied to each group in a page mode in order to alternately write or read video information into the groups. and refresh means for refreshing each group by supplying burst-like address information and a row address strobe signal RAS synchronized with this address-like information to each group for each blanking section of the video signal.

This configuration eliminates the need to write video data in parallel, and since refresh is performed during the blanking period when there is no valid data, writing/reading can be performed on the real time axis without being restricted by refresh operations. becomes possible.

〔Example〕

An embodiment in which the present invention is applied to a frame memory will be described below with reference to the drawings.

In FIG. 1, 1 and 2 indicate memory blocks, respectively. One memory block 1 is eight 256-bit dynamic RAMIAs.

Consisting of IB, IC, LD, IE, IF, IC, and IH, the other memory block 2 also has eight 256
It is composed of dynamic RAMs 2A to 2H. Reference numeral 3 denotes an input terminal to which, for example, a still image color video signal for one frame is supplied. This input color video signal is supplied to an A/D converter 5 via a low pass filter 4.

The A/D converter 5 has a sampling frequency of 4 fsc (fsc is a color subcarrier frequency),
A digital color video signal of 1 sample and 8 bits is generated, and this digital color video signal is supplied to memory blocks 1 and 2. Memory blocks 1 and 2
The digital color video signal read from the D/D is supplied to the selector 6, and the read outputs of memory blocks 1 and 2 are alternately selected by the control signal from the terminal 7.
The signal is supplied to the A converter 8, converted into an analog signal, and taken out to the output terminal 10 via the low-pass filter 9.

Reference numeral 11 indicates an address counter that generates a 9-bit column address, and 12 indicates an address counter that generates a 9-bit/7-bit row address. The outputs of these address counters 11 and 12 are supplied to an address selector 16.

Dynamic RAMIA to IH of memory block 1 and dynamic RAM 2A to 2H of memory block 2
A column address or a row address is commonly supplied to the address selector 16 and a selector 26, which will be described later.

The row address and column address on the same address bus are individually taken into the address decoder in each RAM by a row address strobe signal RAS and a column address strobe signal CAS.

Note that the address counter 11 is supplied with a sampling clock SC synchronized with the input still image color video signal as a clock input, and also supplied with a horizontal synchronization pulse (2) as a clear pulse.

The address counter 12 is supplied with a horizontal synchronizing pulse (2) as a clock input and a vertical synchronizing pulse (V) as a clear pulse. In other words, dynamic R
The row addresses (O~511) of AMIA~IH, 2A~2H are taken as line addresses, and these (O~511)
The column address of is taken as the sample address within the line.

When an NTSC 2 color video signal is sampled at a frequency of 4 fsc, the ■ frame has 525 lines, and the l line contains 910 samples. but,
Valid data in one frame fits within 512 lines.

In this embodiment, each of memory blocks 1 and 2 is operated in the page mode. FIG. 2 is a time chart of this page mode write/read operation. In the page mode, the row address is fixed for a certain period of time, and the open address is changed multiple times during that period to perform writing or reading.

FIG. 6A shows a horizontal synchronization pulse (3) synchronized with the digital color video signal from the A/D converter 5. FIG. This horizontal synchronizing pulse 100 is supplied to the address counter 12,
A row address that changes every horizontal period is formed, and is passed through the inverter 17 to generate the row address strobe signal RAS shown in FIG. and is supplied to memory blocks 1 and 2. Further, from the row address strobe signal RAS, the delay circuit 18 generates a control signal shown in FIG. This row address is then supplied to memory blocks 1 and 2 through selector 26. As shown in FIG. 2F, in the illustrated example, the row address is set to O.

The address counter 11 is cleared by the horizontal synchronization pulse ■, and when this cleared state is released, the address counter 11 starts counting operation by the sampling clock SC, and the column address increments as shown in FIG. 2F. .

A column address strobe signal CAS1 shown in the second diagram is formed from the least significant bit of this column address. This one
Column address strobe signal CAS with a period of 40 nsec
1 is supplied to the memory block l via a delay circuit 19 for timing adjustment and a selector. Also 70ns
The delay circuit 20 of the ec generates a reverse phase column address strobe signal CAS2 shown in FIG. 2, and supplies it to the memory block 2. This allows memory block 1
and 2 are addressed alternately in the sampling period.

Furthermore, the write enable signal 1 shown in FIG. 2G is supplied to the memory block 1, the write enable signal 2 shown in FIG.
Input data Din shown in FIG. 1 is alternately written into memory block 1 and memory block 2 one sample at a time. This results in a write cycle of 140nse.
c, which satisfies the minimum access time of 120 nsec of the DRAM used in the embodiment and enables real-time writing.

■When the first sample data of the horizontal period is written to the dynamic RAMIA to IH of memory block 1,
The next sample data is written to dynamic RAMs 2A to 2H of memory block 2. When this operation is repeated and the next horizontal synchronizing pulse (2) is supplied, the address counter 11 is cleared, the column address returns to its initial value, and the row address is incremented by +1. The column address of the dynamic RAM of 256 bits is (0' to 5).
11), and therefore, a maximum of 1024 sample data can be written within one horizontal period.

A refresh is required to retain written data within each dynamic RAM.

In this embodiment, a refresh counter 30 that operates during the blanking period of the video signal is provided to generate a refresh address.

The DRAM used in the example needs to be refreshed completely within 4 m5ec. Therefore, row addresses for 256 rows are generated in bursts by distributing them over a video blanking interval of 4 m5ec, and each row address is given to the DRAM by RAS, 256 times/4 m5ec.
Performing 5ec RAS only refresh.

Note that if one frame period is 33 m5ec, it is necessary to perform RAS only refresh of 33/4 #8 cycles in one frame period. Assuming that there are 512 lines of valid data in one frame, 512/8=64
Since it is a line, it is necessary to change the row address from 0 to 255 with 64 lines as one cycle. In other words, the row address is incremented at least 256/64=4 times in the blanking section of one line, and refresh is performed by 256/4 m5ec.

The refresh counter 30 is, for example, an 8-bin counter that counts the sampling clock SC from 0 to 255, and its output address is given to the address input of each memory block 1, 2 through the selector 26.

Note that the selector 26 is switched to the output side of the refresh counter 30 during the blanking interval BLK (horizontal and vertical blanking intervals). The refresh counter 30 starts counting, for example, every horizontal synchronizing pulse (2) in each horizontal blanking interval, and stops counting after counting four sampling clocks SC and generating four consecutive row addresses.

On the other hand, the sampling clock SC passes through a delay circuit 21 for timing adjustment and is applied to the memory block 1.2 via a selector 27 as a row address strobe signal RAS for refreshing.

As a result, row addresses that are incremented four times in each horizontal blanking section are sequentially given to the dynamic RAM, and row addresses from 0 to 255 are set in 64 lines (approximately 4 m5ec). Note that the selector 27 is the blanking section BL.
At K, it is switched to the refresh RAS side. Also, at this time, a high level voltage is selected by the selector 27 as the column side address strobe signal CAS,
The CAS input of each dynamic RAM is fixed at high level.

In this way, necessary refresh is performed distributed over the blanking period of the video signal, so that writing/reading of valid video data is not disturbed by the refresh operation, and writing/reading can be performed in real time.

FIG. 3 is a specific circuit diagram of the refresh counter 30.
4-bit serial counter 30a.

30b. As a clock, a pulse 25C having a period twice the sampling clock SC (140 m5ec) is used, and 8-bit (0 to 255) counting is performed. In this case, address increments are performed 16 times in the horizontal blanking section of one line. Therefore, 256 cycles of refresh are completed in 16 lines. This is a rate of 256 times/1m5ec, and the already mentioned 256
times/4 m5ec conditions are fully satisfied. Pulse 2 with a period of 140 m5ec is used as refresh RAS.
SC is used.

The horizontal synchronizing pulse H (the inverted pulse in FIG. 2A) is applied to the enable input E of the first stage counter 30a in FIG.
1-30c, and a counting operation is started on each horizontal sync pulse. When there is a 4-bit (hexadecimal) count, a carry output is output from the first stage counter 30a,
It is derived to the next stage counter 30b. Also, at this time, the carry output is given to the clock input of the D flip-flop, so "1" of the D input is read, and the flip-flop 30d is inverted to the cent state. As a result, the output of the flip-flop 30d becomes "0", the AND gate 30c closes, and the counter 30a stops. Then, the counters 30a, 30
b is in a standby state. In this way, 1G addresses are generated in bursts at each horizontal blanking interval and refreshed.

Note that if the condition of 256 times/4 m5ec is satisfied, the freshness may be performed 8 times in the horizontal blanking section of one line. As mentioned above, if this is done at least four times per line, the memory contents will not be lost. Furthermore, if necessary, a refresh operation can be performed in each horizontal blanking section within the vertical blanking section. In this case, composite sync is given as horizontal synchronization pulse H in FIG. In addition, 16 times/in Figure 3
In the case of line refresh, even if the refresh cycle is not repeated within the vertical blanking interval of approximately 9H,
256/4m5ec glue fresh condition ゛ is satisfied.

As described above, one frame of digital color and video signals written in memory blocks 1 and 2 is read out using the same address control as when writing. At the time of reading, the data shown in FIG. 2 J is stored in memory block 1.
The data shown in FIG. 2K is output from the memory block 2. Then, the selector 6 alternately selects the output data of the memory blocks Q and 2, and as shown in FIG. 20, a continuous digital color video signal can be read out.

〔Effect of the invention〕

According to the present invention, as described above, video information can be directly written as serial data, and refresh is performed in the blanking section of valid data so that writing of valid data is not interfered with by the refresh operation. Therefore, peripheral circuits can be simplified and signal processing can be performed in real time.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a frame memory device showing an embodiment of the present invention, FIG. 1 is a time chart showing the operation of the frame memory device of FIG. 1, and FIG. FIG. 2 is a circuit diagram showing an example. In addition, in the symbols used in the drawings, 1.2・---
---1・-Memory block 5-・---m-・・
・---111----A/D converter 8~...
...--------D/A converter 11.12
−・・・−1111～・Address counter 30−−−
---------------This is a refresh counter.

Claims (1)

[Claims] The dynamic RAM is divided into two groups, and column address strobe signals @C with opposite phases are used in the page mode to perform video information writing or reading operations alternately in the groups.
Address means for supplying AS@ to each group, and refreshing by supplying burst-like address information and a row address strobe signal @RAS@ synchronized with this address-like information to each group for each blanking section of the video signal. A video memory device comprising a refresh means.