JPS6184735A - Effective length expanding device of general-use register - Google Patents

Abstract

PURPOSE:To minimize a change of an instruction system and to expand effective length by changing length of respective pieces of information read from a general-use register and written in the register and length of information which is an object of operation, in accordance with the indicated value of effective length of the stored general-use register. CONSTITUTION:When an instruction is executed by an instruction executing part 200 at an instruction analyzing control part 100 and transferred through a memory control 300 to a main memory device 400, a general-use register control part 10, an address calculating part 20, an operation processing pat 30 and in addition, a mode register control part 40 are installed, at the executing part 200 and a mode register 41 is installed at the control part 40. The main instruction 1 in the control part 100 is an instruction, in which three added values of a value of the general-use register 11 indicated by X2 and B2 and a value of 12 bits of D2, set the data as the address of a memory to the prescribed register, and mode bits are respectively '1' and '0' corresponding to B2 and X2 in the register 41, and the length of the general-use register corresponding respectively is handled as 64 and 32 bits.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to an information processing device based on general-purpose registers, and particularly to an information processing device that can handle addresses and data whose length exceeds the conventional length of general-purpose registers. The present invention relates to a device for extending the effective length of a general-purpose register, which is suitable for extending the effective length of a general-purpose register without making any major changes to the instruction system.

[Background of the invention]

2. Description of the Related Art As the amount of data processed by information processing devices increases, a demand arises to increase the information processing capacity. Part 1
One of the demands is to expand the upper limit of addresses, that is, to increase the amount of data that can be accessed by programs (referred to as address expansion). Another is an increase in the number of processing units (referred to as data expansion), which is a request to increase the number of processing units of information processed by one instruction.

There are two ways to create an information processing device that satisfies these demands. One method is to create an information processing device with a new command system, and the other method is to add some functionality to a conventional information processing device. By the way, when a large number of programs have already been created under one instruction system, it is also required that they can operate as they are on new information processing devices. Considering this point, we prefer the latter method, that is, information processing that makes slight modifications to the conventional command system and allows conventional programs to operate without any changes, while also allowing new programs to operate. It is better to make a device.

IBM's rIB is a method that allows conventional programs to run as is and achieves address expansion.
M System/370 ExtendedArch
item Pvinciples of 0p
erationsJ (S A-22-7085-0)
There is a method as shown in There, the program state word (PSW) is used to control program execution.
), and when the value is 0, the upper limit value of the address is 224-1, and when the value is 1, the upper limit value of the address is 231-1. The one-line method will be explained in more detail below. FIG. 1 shows the classification of instruction formats for information processing devices. In the figure, Rs
, R2, Rs, +3t, Bz, Xi are all
It is used to indicate the number of 16 32-bit general-purpose registers. This instruction system uses 4 bits to indicate the number of a general-purpose register, making it suitable for pointing to any one of the 16 general-purpose registers. The value of a general-purpose register may be an address, a number, or a character code, but there is no distinction between what the general-purpose register represents, and what position in the instruction word it represents. Its use is determined by whether it is instructed to do so. That is, in FIG. 1, B1BS is used as a base register, and B1.BS is used as a base register. The value of the general-purpose register pointed to by B2 and Dl, D,
The value obtained by adding the 12-bit contents of is used to point to an address on memory. In the RX format, x2 is used as an index register, and the sum of the value of the general-purpose register pointed to by X2, the value of the general-purpose register pointed to by B2, and the contents of D□ points to an address in memory. used for. R1, R2°R1 uses the value of the general-purpose register pointed to by it as an address or as data other than an address, but the way it is used is uniquely determined by the instruction word. By the way, the size of a general-purpose register is 32 bits, and the conventional address
When in mode, the lower 24 bits were valid and the upper 8 bits were ignored.

Addresses can be set to general-purpose registers using the LOAD command, which sets the 32-bit data in the memory to the general-purpose register, or by setting the data in the 32-bit general-purpose register and the 32-bit data in the memory.
This is done using the ADD command, which adds 2-bit data and sets it in a general-purpose register. That is, 32
An instruction system based on bit data is used to set, calculate, and calculate addresses, and when used as an address, the upper 8 bits are ignored.

Consider the case of extending an address under such an instruction system. One is when extending to a certain length within 32 bits, and the other is when extending to a length exceeding 32 bits. The aforementioned IBM System/370 Ex
In tandet Architecture, the address is extended to 31 bits, but as mentioned above, the upper 8 bits of the 32-bit general-purpose register are ignored according to the value of the extended address bit, which indicates whether or not the extended address mode is in effect, but the upper 1 bit is ignored. By switching whether or not to ignore the program, it becomes possible to execute both the conventional program and the extended program on one information processing device.

However, one other extension (for example, to 64 bits) cannot be implemented using the above method. As an example of an expanded application of the above method, a method can be considered in which the length of a general-purpose register is expanded to 64 bits, and when a base register or the like is used as an address, a 64-bit calculation is performed. However, under the above instruction system, the number of operations is 32.
Because of the bit size, it is not possible to set or calculate 64-bit address data. Therefore, a new set of instructions for setting and calculating 4-bit address data is required, but this requires a major change in the instruction system, which is not desirable. In addition, as a method that makes it possible to set and calculate extended addresses under the conventional instruction system,
It is also conceivable that a 32-bit operation is performed in the conventional case, and a 64-bit operation is performed in the extended case, depending on the bit value.

However, when this method is applied, a problem arises in that conventional 32-bit data operations cannot be performed in extended address mode.

The problems encountered when extending the length of an address beyond the length of a conventional general-purpose register have been described above.

Along with address extension, the extension of the unit of data operation (data extension) is also required, and the length of the general-purpose register is 3.
Under the conventional 2-bit instruction system, there were no instructions that performed operations on more than 32 bits (for example, 64 bits). Traditionally, for floating point registers, 32 bits, 64
It was possible to perform 128-bit and 128-bit operations by providing separate instructions, but for operations that use general-purpose registers (fixed-point data operations), sequentially numbered registers must be transferred from/to memory at the same time. Currently, 64-bit fixed-point arithmetic operations are performed using a large number of 32-bit arithmetic instructions. For example, in high-level languages such as FERTRAN, as the amount of data to be processed increases,
There is a requirement to handle 4-bit fixed-point data (for example, an array with a thickness exceeding 2" is required), but for 64-bit operations, the compiler has to translate it into a large number of instruction words. This complicates processing and causes deterioration of processing performance.

The problems encountered when address extension and data extension are extended beyond the length of conventional general-purpose registers have been described above.

[Purpose of the invention]

The purpose of the present invention is to expand the effective length of general-purpose registers and handle addresses and data that are larger than the conventional data length, while making few changes to the conventional device. The purpose of the present invention is to provide an information processing device.

[Summary of the invention]

In order to perform address expansion and data expansion under an instruction system based on general-purpose registers, it is necessary to increase the length of general-purpose registers. Conventional programs can be executed as is, and new extended programs use extended general-purpose registers only when handling extended addresses and data, and perform calculations on extended addresses and extended data; operations on non-extended data are It is necessary to carry out the same length as before.

For this purpose, it is preferable to provide a mode bit corresponding to each general-purpose register to indicate whether or not it performs extended address calculations and data operations. Then, an address calculation circuit and arithmetic processing circuit are provided that can switch the effective length of address calculations and operations according to the value of the mode bit, and perform calculations and operations according to the length of information held in the general-purpose register. It can be so.

Also, the number of general-purpose registers is finite, and the contents of each general-purpose register change as the program is executed.For example, a general-purpose register initially holds conventional length data and is used for 32-bit operations. is then used to hold the extended length address and access data within the extended memory range, which in turn is used to perform operations on the extended length data. That is possible. It is necessary to be able to change the extension bit so that the usage method can be changed in the middle of execution within a program.

In addition, under an operating system that performs multitasking processing, it is common to switch processing between multiple programs, and the state of general-purpose registers is saved and restored when switching. - It is necessary to enable evacuation and recovery by the system.

Note that since this mode bit needs to be changed by a conventional instruction, it is preferable to provide it separately outside the general-purpose register.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to FIGS. 2 to 9.

FIG. 2 shows the configuration of an information processing unit 33 to which the present invention is applied. It consists of:

(1) Command analysis/control unit 100 Decodes command words and controls other parts of processing.

(2) Command Execution Unit 200 This is a unit in charge of executing command words, and is a unit to which the present invention is applied.

(3) Memory control unit 300 Controls data transfer with the main storage device (MS) 400.

The above configuration is a common one.

Next, the configuration inside the instruction execution unit 200 to which the present invention is applied will be described.

(1) General-purpose register control unit 1 This is a part that controls reading from and writing to the 16 general-purpose registers 11.

(2) Address calculation section 2゜ This is the part that calculates memory addresses.

(3) Arithmetic processing unit 3° This is a part that executes arithmetic operations on data read from memory and data read from general-purpose registers.

(4) Mode register control unit 40 Mode register 41 that indicates the effective length of general-purpose registers
This is the part that controls the

Among the above, general-purpose register control unit 10. Address calculation section 20. The arithmetic control section 3o is a conventionally provided section, but the mode register control section 40 is a new section. The details of these four parts will be described later, and here an outline of the operation of each part will be explained. for that,
The processing flow of a LOAD command and an ADD command as typical commands will be explained with reference to FIG. Execution of an instruction is usually
The event is divided into time intervals called stages.

Although a case where the process is divided into four stages will be described here, the present invention is not limited to this. Each stage is processed as follows.

(1) Instruction decode stage (D) Deciphers the operation code in the instruction word.

It recognizes LOAD commands, ADD commands, etc., and extracts each part within the command word. This processing is executed by the instruction analysis/control unit 100, but the circuit configuration for this is well known and will not be described here.

(2) Address calculation stage (A) The address of the second operand is calculated based on parts B, , X, and D in the instruction word. Specifically, the calculation is performed by the instruction execution section 200 under the control of the instruction analysis/control section 100. That is, the following processing is performed.

(a) The contents of the B2 part in the instruction word are transmitted to the general-purpose register control unit 10 and the mode register control unit, and the general-purpose register and mode bit indicated by B2 are read respectively, and the 82 register in the address calculation unit 20 is - Set data 26 and B2 mode bit 124.

(b) Same as (a), corresponding to x2 part.

x2 register data 27. and x2 mode
Set a value to bit 125.

(c) The contents of the D2 part in the instruction word are set in the D2 data register 28 in the address calculation section 20.

(d) B2 register data 26. X, register data 27. Addition is performed by the address adder 25 which receives three inputs: D and data register 28, and the result is set in the address register 123. At this time, B
2 mode bit 124. X, mode bit 125.

It is used to control the effective length, and the details will be described later.

(3) At stage (L), the data of the second operand is fetched from the memory. Specifically, the contents of the memory register 123 are stored in the memory control unit 300.
and a fetch request is issued to the MA 400. When a fetch is performed from the 6 MA 400, data is set in the fetch data register 302. In this process, if there is a virtual address mechanism, the contents of the address register 123 represent a virtual address, and a circuit that converts it into a real address operates. Furthermore, if a high-speed buffer storage device BS is provided to store a copy of the data on the main storage device MS, a circuit for accessing the BS operates. Although the description of these circuits is omitted in this embodiment, the presence or absence of these circuits is irrelevant in application of the present invention.

(4) Instruction execution stage (D) In the case of a LOAD instruction, the fetched data is set in the general-purpose register pointed to by the R1 part.

In the case of an ADD instruction, the contents of the R1 register and the fetched data are added, and the result is set in the R register. This process is performed as follows.

(a) The contents of the R1 part extracted by the instruction analysis/control unit 100 are transmitted to the general-purpose register control unit 10 and the mode/register control unit 40.

(b) In the mode register control section 40, the mode bit is read out according to the value of the R□ part.

(c) Memory fetch data in the arithmetic processing unit 30
The contents of the fetched data 302 are transferred to the register 31. In the case of a LOAD instruction, data is transferred to the result register 137, bypassing the arithmetic unit 32. A
In the case of a DD instruction, the contents of the general-purpose register pointed to by the R1 part are read in the general-purpose register control unit 10.

It is transferred to the register output data register 131, becomes an input to the ALU 32 together with the fetch data register 31, and is added. The addition result is in result register 13
Set to 7. The R1 mode bit 136 read in (b) is used to control the effective length of the result register 137, which will be described later.

(d) When a LOAD instruction or an ADD instruction is used, the contents of the result register 137 are transferred to the general-purpose register control unit 10 and set in the general-purpose register specified by the value of the R□ part via the register input register 12.

As described above, one or more operations performed by the LOAD and ADD instructions are known, except for descriptions related to mode bits.

Next, the operation when the present invention is applied will be explained in detail with respect to the circuit therefor. First, the details of the operation of this embodiment will be explained in the fourth section.
The LOAD command will be explained using figures.

This instruction 1 reads data by using the sum of the value of the general-purpose register pointed to by R2, the value of the general-purpose register pointed to by B2, and the 12-bit value of B2 as a memory address, and
This is an instruction to set the data in the general-purpose register pointed to by R□. In the conventional mode, the length of address and data is 4 bytes (=32 bits) or less. When the present invention is practiced, the mode bit corresponding to 82 in mode register 41 is 1. When the mode bit corresponding to R2 is set to O, the general-purpose register pointed to by B2 uses a 64-bit value, and the general-purpose register pointed to by R2 uses a value in which the lower 32 bits and upper 32 bits are assumed to be 0. That is, when the mode bit is 1, the length of the corresponding general-purpose register is treated as 64 bits, and when the mode bit is 0, the length of the corresponding general-purpose register is treated as 32 bits. In this embodiment, the length in extended mode is 64 bits, but it should be noted that any bit length may be used. However, the unit of access to memory is byte (=
8 bits), it is preferable to set it to a multiple of 8.

It is also noted that the configuration of the mode register is such that address extension and data extension are separate mode bits, and two bits correspond to each general-purpose register. here,
As mentioned in the explanation of the request for data expansion, the address was set to 64 bits in order to perform address expansion in conjunction with realizing 8-byte fixed-point data. It should also be noted that as a data extension, a 64-bit address extension (such as a 24-bit address system) in which a part of the address (for example, the lower 48 bits) is used as an address can also be implemented in the same manner.

In FIG. 4, B2, 3. X,,4. The sum of the three numbers B2.5 is used as a 64-bit address 6 for accessing data on the memory. The length of the data read from memory depends on the mode bit corresponding to R. When the mode bit is 1, 8 bytes of data (■, ■) are read and set in 64 bits of the general-purpose register pointed to by R□. When the mode bit is O, 4 bytes of data (■ part) are read, and when the value of the most significant bit When is 7, the value to which 1 is added is set in the general-purpose register 7, respectively.

Next, a detailed explanation of this embodiment will be given. First, the operation of the general-purpose register control section 10 will be explained with reference to FIG. There are 16 general-purpose registers (11), and input/output to and from them is selected and executed by the register number designation register 14. In other words, 1 according to the contents of the register number designation register 14.
One of the six general-purpose registers 11 is selected, and for writing, it goes through register input data register 12, and for reading, it goes through register output data register 1.
Writing/reading is performed in units of 64 bits via 3.

Next, the operation of the address calculation section 20 will be explained using FIG. 6. An example of the LOAD instruction 1 shown in FIG. 4 will be explained. The contents of the register x2 specified by the instruction word are read out from the general-purpose register control unit 10 in FIG.
Set in register data register 21.

Also, the mode bit 125 corresponding to the x2 register
is read out from the mode register control unit 4o (details will be described later). When the value of X2 mode bit 125 is 0,
The contents of the constant register 22 holding O is the address.
The first 32 bits of the x2 manual register 26 of the adder 25
Set. When the value of X2 mode bit 125 is 1, the first half 3 of x2 register data register 21
2 bits are set in the first 32 bits of the X2 manual register 26. In both cases, the latter 32 bits are X2.
The value of the latter 32 bits of the register data register 21 is set as is. The above-described processing for x2 is also performed for B2 in the same manner, and it is set in the 82 manual register 27. The D2 part of instruction word 1 is set in the D2 manual register 28 as is. x2 manual register 26. B, input register 27, D, and input register 28 are made up of three people including address adder 25, and addition of the three is performed and the result is set in output register 121. The selector 122 sets the contents of the constant register 22 in the first half 32 bits of the address register 123 when the X2 mode bit 125 and the B2 mode bit 124 are both 0; Used to set the contents of the first 32 bits of the output register. In either case, the latter 32 bits of the address register 123 are used as the output register 121.
The latter 32 bits are set as is. As a result of the above, when both the x2 register, B, and the register are in the conventional mode, an address with an effective length of 32 bits is generated, and when at least one is in the extended mode, an address with an effective length of 64 bits is generated. According to the generated address, the memory
The request is executed, but its operational circuit is well known and will therefore be omitted.

Next, the arithmetic control section 30 will be explained using FIG. 7. First, the continuation of the processing of the LOAD command will be explained.

As a result of the memory request described above, the memory fetch data register 31 is set with data read from memory. Its contents are 64-bit AL
It is set in the input register 33 of U32 and becomes an input to the selector 34.

In the case of a LOAD instruction, the memory fetch data is directly input to the mode selector 35 by the selector 34. The first half of the memory fetch data register 31 is further provided with an input register 37 of the 32-bit ALU 36.
and also serves as an input to the selector 38. L
In the case of an OAD instruction, the memory fetch data is directly input to the data expander 39 as described above, and is further expanded by the data expander 39 to 64-bit data. That is, when the value of the most significant bit of 32-bit data is 1, 32-bit data with all 1's is added, and when it is 0, 32-bit data with all 0's is added. Since the circuit for this purpose is also known, its explanation will be omitted here. The output of the data expander 39 is the mode selector 3 described above.
5 input. In the mode selector 35, the mode bit corresponding to the register pointed to by R1 of the instruction word is transmitted from the mode register control unit 40, and when the value is 1, 64-bit data is transferred to the mode bit when the value is 0. sometimes 3
The 2-bit data is selected, and the result 137 is transferred to the general-purpose register control unit 10 as register input data. The general-purpose register control unit 10 sets the information in the general-purpose register 11 as described above.

As described above, the processing of the LOAD command (the processing described in FIG. 4) is completed. Next, the data is A as an example of expansion.
The processing of the DD command will be explained using this figure.

This instruction has the same RX format as LOAD instruction 1, and fetches the data on the memory indicated by This is an instruction to set the general-purpose register pointed to. The data fetched from memory is set in the memory fetch data register 31 by the same processing as in the LOAD instruction.

In the case of an ADD instruction, 64-bit ALU 32 and 32-bit ALU 36 operations are performed. Data read by the general-purpose register control unit 10 is set in the register data register 131 at the input of both ALTJs.

The entire 64 bits are set in the input register 132 of the 64-bit ALU, and the lower 32 bits are set in the input register 133 of the 32-bit ALU. In the case of an ADD command,
Unlike the LOAD command, the selector 34.38 selects A.
LU outputs 134 and 135 are selected. The latter is expanded to 64-bit data by a data expander 39. The output of the selector 34 and the output of the data expander 39 are input to the mode selector 35, and one of them is selected according to the value of the R□ mode bit.

This becomes register input data 137. This value 137 is set in the general-purpose register pointed to by R1 in the general-purpose register control unit 10. In this way, the ADD instruction is executed. Although the 64-bit ALU 32 is newly provided in the present invention, it can be realized by easily expanding the 32-bit ALU, so the details will be omitted, but the length of the operation is 3.
The number of bits has changed from 2 bits to 64 bits, and the circuit for generating interrupt factors such as overflow can be implemented by detecting overflow from the first bit in the same way as the 32-bit ALU. Further, it is also possible to easily create an ALU having the same functions by integrating the 64-bit ALU, 32-bit ALU, data extender, etc. shown in this figure.

Next, the operation of the mode register control section is performed using FIG. Register part 1o7 of instruction word 1 is set to register number 44, and becomes a selector signal for selector 42.

The mode register (MR) 41 becomes an input to the selector 42, and a portion corresponding to the designated register number is output as a mode bit 110, and is transmitted to the address calculation section 2o and the arithmetic processing section 30 described above.

Next, FIG. 8 shows instructions provided for setting, changing, and transferring the mode register 41 to the memory.

This will be explained using FIG. 9. It would be better to create four new commands. All four instructions are of the S format in FIG. The S format address specification section (B2゜B2) is the memory
It is used as data for SR operation and AND operation, which will be described later.

(1) ORMode Register (OMR
) Instruction An OR operation is performed between the information of the lower 16 bits of the operand address specified by the instruction word and each bit of the information of the mode register 41 (step 20 in FIG. 9).
1) The result is set in the mode register (step 2)
02), that is, in FIG. 8, the NMR command signal 141 is turned off by the decoder 43. By the way, MR
The contents of 41 are sent to the AND circuit 14 via the register 142.
3. It becomes an input to the OR circuit 144. Also, the operand
The address becomes an input to both circuits via a register 145, and an AND operation and an OR operation are performed on both circuits, and the results are set in registers 145 and 146, respectively. As described above, in the case of the OMR command, one of the NMR command command signals is OFF, and the output 146 of the OR circuit is selected.

Further, the LMR command signal line 147 is turned off, the MR write signal ti 148 is decoded to be turned on, and the output 146 of the OR circuit is set to MR41.

(2) AND Mode Register (N
M R) Instruction The OMR instruction is the same except that the OR operation becomes an AND operation, and the NMR instruction signal line 141 is decoded to be on, and the AND result 145 is the M
Set to R41.

(3) Load Mode Register (L
MR) Command Read 2 bytes of data at the address specified by the command word from memory (step 205), and set the mode.
It is set in the register 41 (step 206).

That is, memory fetch data register 149
The upper 16 bits of the data are written to MR41.

In the decoder 43, the LMR command signal line 147 is turned on to select the input of the memory fetch data register 149, and the MR write signal Mc148 is turned on to be written to the MR 41.

(4) 5tore Mode Register (
STMR) The contents of the instruction mode register 41 are stored at the address indicated by this instruction word. In the case of this order,
The STMR command signal line 150 is turned on by the decoder 43, and the memory request is executed via the memory store data register 151.

The operations of the four instructions related to the mode register 41 have been described above, but these instructions are preferably non-privileged instructions. That is, since the contents of the general-purpose register change for each program and change from time to time within a program, the above-mentioned instructions can be used even in non-privileged programs. Further, it is preferable that all the initial values of the mode registers be set to O.

The present embodiment has been described above. According to this embodiment, the following effects are achieved.

(1) Conventional programs can be executed as they are without any changes. Since the initial value of the mode register is 0, it is treated as the conventional effective length, so there is no need to change the conventional program at all.

(2) To change a conventional program so that only the data address accesses the extended address part, before accessing the extended address part, set the mode corresponding to the general-purpose register used as the register for the extended address. - Set the bit to 1, perform memory access, and change the mode bit to 0 when it is no longer used as an extended address register, that is, add two instructions, making it easy to access the address. Expansion is possible.

(3) Even when a conventional program is stored and operated in the extended address part, the base of the program part
All you need to do is make the same changes to the general-purpose registers used as addresses.

(4) Expanding the processing unit of fixed-point data from the conventional 32 bits to 64 bits is also possible by setting the mode bit of the general-purpose register to 1 before using it for extended data, as described above.
64-bit fixed-point operations can be performed using the same command system as before by simply 6. (5) Create a new program that operates with extended addresses or that can handle extended data. Even when doing so, conventional software technologies such as compilers can be used almost unchanged.

Note that when storing the contents of general-purpose registers used in extended mode in memory or setting values from memory, the size of the storage area for this purpose must be changed from the conventional 4 bytes to 8 bytes. However, its operation is easy.

〔Effect of the invention〕

According to the present invention, address expansion and data expansion can be realized without changing the instruction system.

This has the effect of making it easier to reuse conventional programs and software such as conventional compilers. In other words, (1) the instruction system remains almost the same, and (2) address extension is possible by adding an instruction that changes the corresponding mode bit only when a general-purpose register is used as an extended address or extended data. In addition, since data expansion can be realized, it is possible not only to run a huge amount of programs accumulated in the past as is, but also to operate with extended addresses and handle extended data with only slight modifications. As a result of the above, there is an effect that the number of software development steps required for address expansion and data expansion can be greatly reduced.

[Brief explanation of drawings]

FIG. 1 is an explanatory diagram of the instruction format of an information processing device, FIG. 2 is a configuration diagram of an embodiment of the present invention, and FIG. 3 is a LOAD instruction, an ADD instruction
Instruction operation overview diagram, Figure 4 is a detailed operation diagram of the LOAD instruction, Figure 5 is a circuit diagram of the general-purpose register control unit, Figure 6 is a circuit diagram of the address calculation unit, and Figure 7 is the arithmetic processing unit. FIG. 8 is a circuit diagram of the mode register control section, and FIG. 9 is an explanatory diagram of the operation of the mode register operation instruction. 10... General-purpose register control unit, 11... General-purpose register, 2o... Address calculation unit, 25... Address...
Adder, 30... Arithmetic processing unit, 32, 36... ALU
, 40...Mode register control unit, 41...Mode register, 23, 24, 134.38...Selector, 35...Mode selector, 39...Data extender, 143...・AND circuit, 144...OR circuit, 1
00... Instruction analysis control unit, 200... Instruction execution unit,
300...Memory depth 1 ″ Sn-/Tofu 9 (Ehζ()

Claims (1)

[Claims] In an information processing device having an instruction system based on general-purpose registers, an effective length instruction mode storage means for specifying the effective length of each general-purpose register, a length of information read from the general-purpose register when an instruction that handles the general-purpose register is operated, It is characterized by comprising means for changing the length of information to be written into the general-purpose register or the length of information to be subjected to an operation using the general-purpose register, according to the value stored in the mode storage means. Effective length extender for general purpose registers.