JPS6183376U

JPS6183376U -

Info

Publication number: JPS6183376U
Application number: JP16684984U
Authority: JP
Priority date: 1984-11-02
Filing date: 1984-11-02
Publication date: 1986-06-02

Description

[Brief explanation of drawings]

第１図は本考案の同期信号分離回路のブロツク
図、第２図は複合映像信号の模式的波形図である
。１……バツフアアンプ、２，４……クランプ回
路、３……フイルタ、５，１４……分離回路、６
，７……サンプリングパルス発生回路、８……ク
ランプパルス発生回路、９，１０……サンプリン
グ回路、１１，１２……記憶回路、１３……演算
回路。 FIG. 1 is a block diagram of a synchronization signal separation circuit according to the present invention, and FIG. 2 is a schematic waveform diagram of a composite video signal. 1... Buffer amplifier, 2, 4... Clamp circuit, 3... Filter, 5, 14... Separation circuit, 6
, 7...Sampling pulse generation circuit, 8...Clamp pulse generation circuit, 9, 10...Sampling circuit, 11, 12...Storage circuit, 13...Arithmetic circuit.

Claims

[Claims for Utility Model Registration] (1) A first detection means for detecting the level of the sync chip of the composite video signal, a second detection means for detecting the level of the pedestal of the composite video signal, and the first detection means for detecting the level of the sync chip of the composite video signal. an arithmetic circuit that calculates a predetermined level between the detected sync chip level and the pedestal level from the output of the detection means and the output of the second detection means; and the predetermined level calculated by the arithmetic circuit. A sync signal separation circuit comprising: a separation circuit that separates a sync signal from the composite video signal based on . (2) The synchronizing signal separation circuit according to claim 1, wherein the predetermined level is an average value of the level of the sync chip and the level of the pedestal. (3) The synchronization signal separation circuit includes a first clamp circuit that clamps one of the sync chip or pedestal and outputs the composite video signal as a first signal, and a second clamp circuit that clamps the other and outputs the composite video signal as a first signal. a second clamp circuit outputting as a signal, the first and second detection means generate a signal with a timing synchronized with the synchronization signal from the first signal,
3. The sync signal separation circuit according to claim 1, wherein the sync chip and pedestal levels of the second signal are detected at the timing of the generated signal. (4) The synchronizing signal separation circuit according to claim 3, wherein the first clamp circuit clamps the sync chip, and the second clamp circuit clamps the pedestal. (5) The first detection means and the second detection means are
Utility model registration claim 3, characterized in that each circuit includes a circuit that generates a sampling pulse synchronized with the synchronization signal separated from the first signal, and samples and holds the second signal using the sampling pulse. The synchronizing signal separation circuit according to item 1 or 4.