JPS6180919A - Error correction controlling circuit - Google Patents

Abstract

PURPOSE:To simplify an error correcting state detecting circuit by reading out a syndrome data by one bit unit, and detecting a correcting state by its variation. CONSTITUTION:A data which has been written in a RAM30 is read out to a shift register by a prescribed bit unit. The read-out data is accumulated through a switch 90 to a syndrome register 50, to, whether a wrong bit exists or not is counted several times, and whether an error exists or not is determined by a majority circuit 60. If an error exists, the data of the shift register 40 is corrected by a correcting circuit 70, inputted to a shift register 80, and written in the RAM30. Also, the correcting circuit 70 resets the syndrome register 50. A correcting state detecting circuit 120 reads a syndrome data S held by the syndrome register 50, by 1 bit each after having corrected an error, holds its state as a signal SD in the shift register 80 and writes it in an address of the RAM30. The number by which the error has not been corrected normally is detected by the number of '1' of this written signal SD.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an error correction control circuit, and more particularly to an error correction control circuit that detects an error correction state to determine whether error correction has been performed normally.

[Technical background of the invention and its problems]

A teletext system has been developed in which a digital signal is superimposed and transmitted during the horizontal scanning period, which until now was a no-signal portion, within the vertical retrace period of a television signal. Transmission methods for teletext include a pattern transmission method in which character-graphic information is divided into pixels and transmitted, and a coded transmission method in which the information is encoded and transmitted. A major feature of the coded transmission method is that it can transmit a large amount of information per unit time compared to the pattern transmission method, but code errors that occur during transmission in the form of digital signals can lead to typos and omissions. There is a problem that is displayed.

Therefore, in a teletext broadcasting system using a coded transmission method, error correction is performed on errors in the digital signal.
It has been proposed to improve the reliability of digital signal processing. In order to perform this error correction, (272
, 190) A correction method using a shortened difference set cyclic code was developed. For example, II Wave Technology Council Report, Part 4, No. 17
This correction method is described on pages 1 to 190, and will be described below with reference to one drawing.

In FIG. 7 showing the format of a teletext signal, one data packet of one teletext signal is a synchronization section.

It consists of an information section and an error correction section. 16-pin clock run-in signal (CRI) that constitutes the synchronization section above
is a rounding method that synchronizes the phase of the rounding sampling clock that samples the data of one teletext signal, and a byte synchronization method that uses an 8-bit framing code (FC) to capture data in units of 8 bits (1 byte). is taking. Information Department Service Identification Code (SI/
IN)) 6D code indicating 18-bit transmission method, etc.
The packet control code (PC) is a 6-bit code that indicates the continuity of data packets. Furthermore, the information section is constituted by the n-byte data section following this PC.

In order to correct errors occurring in this 190-bit information section, an 82-bit error correction section is added after the information section. By adding an error correction section consisting of check codes P0 to P, 1, it is possible to correct a code error in 8 bits) 1 that occurs in the 272 bits including the information section and the error correction section.

Next, a conventional error correction control circuit for correcting errors in a teletext signal having the above-described configuration is shown in FIG. 8 and will be described.

In the figure, RAM 11 stores a total of 272 bits of data, including the information part and the error correction part, in one data packet of the received teletext signal, and after the correction operation is completed, the corrected data is stored. Ru.

All data input/output to this R/Mll is done by CPU1.
2 and program ROM 13. The uncorrected parallel data in 8-bit units read from the RAM 11 is converted into serial data D in 1-bit units by the parallel-to-serial conversion shift register 14.

272-bit shift register. at the same time.

Serial data D is also given to the syndrome register 16. This syndrome register 16 performs syndrome calculations on 272-bit data. Depending on the result of this syndrome calculation, the majority circuit 17 determines whether or not to perform correction. Based on this judgment output, the correction circuit 1
8, the serial data D output from the shift register 15 is corrected. Here, the 272-bit shift register 15 operates as a delay circuit for synchronizing the data and the operation result, since the output of the operation result from the syndrome register 16 is delayed by 272 bits. The serial/parallel conversion shift register 19 converts the corrected data CD output from the correction circuit 18 into 8-bit parallel data. This parallel data is sent to R via the CPU 13.
It is stored again in AM11. Note that the timing generation circuit 20 generates the registers 14.15.1 based on the clock CK.
6°19 shift clock 5CLK is generated.

This error correction method can detect errors occurring in 8 bits out of 272 bits of data as described above, but cannot correct any more errors in the data. Therefore, error detection is performed to detect whether the error has been correctly corrected. This can be done by looking at the contents of all 82 registers of the syndrome register 16 after error correction has been performed. In other words, if all 272 bits are correctly corrected, their contents will be all 0'' and 1.
If it has not been performed, there will be one or more ``1''.

Therefore, the OR circuit performs an OR operation on the wing bit syndrome data held in the register 16, and the CPU 13 reads the result through the l1022.

Next, the operation of the conventional error correction control circuit having the above configuration will be explained.

First, the CPU 13 uses a write pulse W of a, vv 11.
Set E to @H” to read state, R/, M 11
The uncorrected data stored in
Output and write this data. This load pulse L
Using D as a reference, the timing generation circuit 20 generates a shift clock 5CLK from the supplied clock CK and outputs it to the shift register. This shift clock 5CLK
The data D converted into serial data is supplied to a 272-bit shift register 15 and a synchronized ROM register. Note that the syndrome register 16 performs a head-order syndrome calculation on the supplied data D. The above operations are repeated and when all 34 bits (272 bits) of data are supplied to the register, error correction is performed thereafter.

At the time of wA9 correction, the CPU 13 sets the 4-write pulse WE of R, AMII to @L'', puts the RAM 11 into the writing state, and writes the corrected data again to R, Ilu'vi.
Make it possible to write to ll. The 272-bit shift register 15 and syndrome register 16 are shifted by υ1 bit by shift clock 5CLK. At this time, syndrome register 16fd syndrome performance xt
- At the same time, the syndrome is supplied to the majority circuit 17K. The majority decision of this syndrome is determined by the majority decision circuit 17, and it is determined whether the data D should be corrected or not.

The timing of this judgment, that is, the timing of transmitting the error correction signal, is delayed by the shift register 15, so that it is synchronized with the data to be corrected, and the correction circuit 18 performs the correction operation. , 1: is performed. The correction data CD is converted into 8-bit parallel data by a serial-parallel conversion shift register 19. The CPU 13 reads this parallel data from the shift register 19 using a read pulse RI) and writes it into the RAMH.

Below are the above correction actions and correction day! The storage operation is repeated, and one packet of data is corrected and stored in the RAM 11.

Thereafter, the OR circuit 4 performs an OR operation on the contents of the 82 registers in the syndrome register 18 to detect whether the above-described correction operation was performed correctly. This detection result is read by the CPU 13 by providing a quad pulse LD.

As described above, it is possible to detect whether error correction has been performed normally based on the output from l1022.

As mentioned above, there is an error in the royal system, and in the control circuit.

To detect the state of correction, each registration output of the syndrome register 18 is subjected to an OR operation in an OR circuit 21. However, since the OR circuit 21 requires 82 people to perform the OR operation, the scale of the circuit and its wiring length are enormous. Special K: When converting this error correction control circuit into an IC, there will be a significant problem.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide an error correction control circuit that can detect the state of error correction to determine whether error correction has been performed normally without increasing the circuit size.

[Summary of the invention]

In the present invention, for example, as shown in FIG. 1, a correction state detection circuit 120 reads out 82 bits of syndrome data held in a syndrome register one bit at a time. This correction state detection circuit 120 detects that the error correction operation has not been performed normally by holding that the syndrome data has changed from 0" to "1", and writes this detection result to the RAM 30. The above objectives have been achieved.

Embodiment of the Invention] Hereinafter, an embodiment in which the error correction control circuit of the present invention is applied to a teletext receiving apparatus using a coded transmission system will be described with reference to the drawings.

First, the outline of this embodiment will be explained with reference to the circuit diagram shown in FIG. In Figure 1, the AM30 stores a total of 272 bits of data, including the information part and the correction part, in one data packet of the received teletext signal as described above, and after the correction operation is completed, the data is corrected. The data will be stored. In addition.

The input of data to this RAM 30 when receiving a teletext signal and the input/output of data from the RAM 30 after the completion of the correction operation are performed by a CPU and a program RO (not shown).
The CPU and ROM are not involved in data input/output from the AM 30 during the correction operation. The parallel-to-serial conversion shift register 40 converts the 8-bit parallel data read from the RAM 30 into serial data D.
Convert and output. This serial data D is stored in a syndrome register consisting of an 82-bit shift register.

The majority circuit ω determines whether or not to correct the data D based on the result of this calculation. This majority circuit ω divides the syndrome data supplied from the syndrome register father into 17 predetermined groups.

Exclusive OR operation is performed within each group.

Then, if the number of operation results @1'' of the 17 groups is 10 or more, it is determined that there is an error υ, and a 1 determination output C is supplied. This determination output C is a correction circuit composed of an exclusive OR gate. 70 K is supplied and data D output from the shift register 40 is corrected.Also.

The above judgment output C is also supplied to the syndrome register I as a syndrome reset pulse.

Clear the Jindrome Regis Mecha.

The corrected data CD outputted from the correction circuit 70 is converted into 8-bit parallel data by a serial/parallel conversion shift register and stored in the RAM 30 again. Then, by switching the switch K, the destination of the data D output from the shift register 40 is switched, and the output of the error correction signal and the data to be corrected are synchronized. Note that the timing generation circuit 100 operates based on the clock CK.
It controls the timing of the correction operation of each of the above circuits.

Furthermore, a correction state detection circuit 120 that detects whether or not error correction has been performed normally, which is a feature of this embodiment, is as follows:
After error correction, the syndrome data held in the syndrome register group is read 5t-i bits at a time, and if 11' is detected, that state is maintained. The syndrome data S and data indicating the detection state are stored as data 8D in the RAM 30 by a serial/parallel conversion shift register via a switch 130.

Next, an overview of the operation of the embodiment having the above configuration will be explained with reference to FIGS. 2 and 3.

In this embodiment, as described above, the correction operation is performed without depending on the CPU. Further, this error υ correction operation can be roughly divided into three types.

First, the 272-bit data stored in the RAM 30 is written to the syndrome register mechanism via the shift register 40, and a syndrome operation is performed. The second is based on the calculation result data stored in the syndrome register.

The majority circuit ω determines whether or not to perform the correction, and the data before correction is read again from the AM30! This is an operation in which the corrected data is output, corrected by the correction circuit 70, and then stored in the RAM 30. The third operation is to supply the syndrome data S held in the syndrome register mechanism, which is a feature of this embodiment, to the correction state detection circuit 120, detect the correction state, and write the detection result to the RAM 30.

The above correction operation is performed as follows: 1) The CPU (not shown) sends a start signal ST.
The process begins by outputting R to the timing generation circuit 100. That is, in the timing generation circuit 100 shown in FIG. 3, when the start signal STR (FIG. 3a) is applied to the set terminal S of the SR, -7 lip-flop (hereinafter referred to as FF) 1o1, the Q output of the FF 101 (FIG. b) is @H”, and the Q output of D-FF102 (C in Figure 3) is also clock C.
At the rising edge of K (FIG. 3 j), @H'' becomes. The Q output of this @H level is applied to AND gates 103) to 105, and A and C 106 to 108 are rear.

Since the count is released, the clock CK starts counting. The Q1 to Q4 outputs of the counter 106 are decoded by the timing decoder 109, and various pulses LD, 5CLK, WEL(
3 f) and Q as a reset pulse for the counter 106 are generated. Counter 107 counts Q using Q as a clock, and its outputs Q6 to Qu are input to timing decoder 110 to detect whether control for 34 bytes has been completed. This timing decoder 11
From 0, Q+t a , ! to define the first action and the second and third actions. :Q+tb is output and becomes the clock for the counter 108 at the next stage. These Q and □ are calculated by the counter 107 in order to specify the first operation consisting of U byte units.
The count value of is output at that time, while Qttb is 46
It is output when the count value is 46 to define the second and third operations in byte units.

Counter 10 using this Q1□+Qttb as a clock
8 counts, and when the QCs output of the counter 108 is "L", the first operation is performed, and when it is 'H#, the second and third operations are performed.This output Q1. is used as the switch signal SW (Fig. 3 e). At the same time as changing the switch (a), the above Qtta
+Qxzb is also switched to use as the clock for the counter 108. Further, the timing decoder 110 outputs a gate signal GATE (FIG. 3d) in order to distinguish between the second operation and the third operation. 9, this gate signal GATEi is the switch 13
0 switching is performed. After the second and third operations are completed, Q
+4 output (Fig. 3 f) becomes °H”, FF 10
1.

102 is reset and the correction operation ends.

Next, the first correction operation will be explained by enlarging the period T1 in FIG. 3. This operation is started by a start signal 5Tn (FIG. 3k), and various pulses are generated from the timing decoder 109 that controls the operation of one byte. This 1-byte operation is performed in 11 clocks CK (FIG. 3j). first.

One byte of data is stored in the shift register 40 via the data bus by the load pulse LD (n in FIG. 3). The address at this time (Fig. 3 r) is.

Q, ~Qu of the counter 107 that controls a byte
It is given as output B0. Then shift clock 5C
Eight LKs (G in Figure 3) are output, and the shift register 40
Serial data D is output from. At this time, counter 1
Qts output of 08, that is, switch signal SW (Fig. 3 e)
is @L″, so the switch (a) is 41 on the a side.
It has become. Therefore, the serial data D is input to the syndrome operation register 50, and syndrome operation is performed.

Here, at a timing between the sixth shift clock 5CLK and the seventh shift clock, the write pulse W is sent from the decoder 109.
EI is output, but since it is gated by the Nantes gate 111 (by the switch signal SW), the light pulse WE
is not output. Therefore.

No writing is performed to RAM 30. and.

■Q and output of decoder 109 at the clock point (Fig. 3 q)
is performed, the counter 107 is counted up, and the Ql output is sent to the counter 1 via the inverter 112.
Since the voltage is applied to the reset terminal R of the counter 10
6 is reset.

Writing of 1 byte of data consisting of the above U clock units is performed U times, and the shift is made to the -m register 50 by 34
When a byte (272 bits) of data is input, the decoder 110 also outputs Qll.

At this time, the switch 115 is on the a side because the Q4 output of the color/return 108 is 1L'', and the above output Qtt
m is given to the counter 108 as Qtt.

As a result, the counter 108 is counted up and the counter 107 is reset by the output of Qsz via the inverter 113, so that the Q11 output (
When e) in FIG. 3 becomes @H'', the switch 115 is turned to the b side to complete the first correction operation and move on to the second correction operation.

In the second correction operation, as shown in an enlarged view of period T2 in FIG. is corrected and stored in the RAM 30 again. First, as in the first correction operation, a quad pulse LD (n in FIG. 3) is applied to the RAM 30 and shift register 40.
%R, AM 30 address Be (Figure 3 r
) The data/1 byte stored in shift register 4
Written to 0.

The written 1-byte parallel data is output as serial data D based on the shift clock 5CLK (O in FIG. 3). At this time, the switch signal 8W (FIG. 3, 5) is +wH@ in the second correction operation as described above, so the switch (a) is connected to the b side, and the serial data D is sent to the correction circuit 70. At the same time, the calculation result of the syndrome register father is judged by the above-mentioned majority circuit ω, and the serial data D is corrected by the correction circuit 70 based on the judgment output C output in units of 1 bit. The data CD is stored one bit at a time in a serial/parallel conversion shift register based on a shift clock 5CLK.

Now, the above corrected data according to this embodiment is RA
The characteristics when writing to M30 will be explained.

The RAM 30 stores a total of 272 bits of the received teletext signal, including the information part and the error correction part, and the storage method is as shown in FIG.

This is done one byte at a time in the order of transmission, that is, at a transmission unit. However, as explained with reference to FIG.
Since /IN is 8 bits and PC is 6 bits, 1 byte of data in the data section is stored over 2 bytes. For example, the first byte of the data part is D14 to D! as shown in FIG. 1 and '), it straddles Bs and B. Therefore, when processing the data in this data section, the data in the transmission unit must be converted once into the data in the processing unit.

Therefore, in this embodiment, when the uncorrected data stored in the RAM 30 is corrected and stored in the RAM 30 again,
The data in units of transmission described above is converted into data in units of processing and stored. The data conversion will be explained below.

The 6-bit data D is corrected by the 6-clock shift clock 8CLK, and the shift register (capital)
When stored, the timing decoder 109 outputs a write pulse WE1. At this time, since the switch signal SW (Fig. 3e) is @H'', the Nant gate 1
A light pulse WE (Fig. 3 p) is output from 11,
The nine correction data stored in the shift register is written to the RAM 30 shown in FIG. 6 as processing unit data. The write address at this time (Fig. 3 r) is the Q, ~Q□ output of the counter 107 and the Q output of the counter 106.
It is given as address B0, which is a combination of four outputs (S in FIG. 3) ``H''.

After that, two shift clocks 5CLK are output.

The 2 bits of data remaining in shift register 20 are transferred to shift register (9). Then, the counter 107 is counted up by the parrot output (FIG. 3q) of the decoder 109, and the Ql output is applied to the reset terminal R of the counter 106 via the inverter 112, so that the counter 106 is reset. This is K
Then, the data conversion operation for one byte of the primary order begins.

The correction operation for 1 byte of data consisting of 11 clock units is performed u times, and as shown in FIG.
Data D0 to I)fisl are stored in 0. Here s
Since the Qss output (Fig. 3 e) is @H2, the switch 115 of the tie generation circuit 100 is turned to the b side, so Qtzb, which is output when the count value of the counter 107 is weak, is output as Ql. be done. Therefore, at this point, since Qu is not yet output, the counter 108 does not count up and %Q14 is not output.

After that, when two shift clocks 5CLK are output, the remaining data D, + D! ? 1 is also corrected and stored in the shift register. And the counter
When the count value of counter 1107 reaches 3, the gate signal GATF) (Fig. 3 d) becomes @
After that, the count value of the counter 107 is held until it reaches 46. As a result, the switch 130 is turned to the a side, and the third operation, that is, the correction is performed during the period indicated by T1 in FIG. A state detection operation is performed.

Next, this third operation will be explained with reference to FIGS. 4 and 5.

In FIG. 4 showing details of the correction state detection circuit 120,
Q of the FF 121 outputs 1H'' during the period when the gate signal GATE is ``L'', that is, during periods other than the third operation.

Nando Game) 122. The FF 123 detects the state of the syndrome data S, and the FF 121 maintains the state. The Nant gate 124 supplies this holding result to the shift register as 8D.

The operation of the correction state detection circuit 120 will be explained with reference to a time chart of each part of the correction state detection circuit 120 shown in FIG.

First, the signal GATE (Figure 5a) becomes "H" and F
F Release the set state of 121. Nantes Gate 12
2 gates the syndrome data S (FIG. 5C) supplied from the syndrome register by the signal GATE to generate syndrome data S indicating error information.
Output only t (ms figure d). FF this data S
123 is latched by the shift clock 5CLK (FIG. 5f) and outputs Q (FIG. 5e). Here, if the syndrome data S is @O$1, the Q output of the FF 123 maintains ``H2'', so the FF 121 continues to output @H'' without being reset. Therefore, the correction status signal 8D of 10" is output from the Nant gate 124.
(FIG. 5f) is output.

The correction state detection circuit 120 is provided with syndrome data S.
When '1' is inputted as '1', the data Si becomes L', which is latched by the FF 123. For this reason, FF
Since the Q output of FF 123 becomes @L", the FF 121 is reset, and the Q output of FF 121 becomes "L". From then on, the Q output is maintained regardless of the value of the syndrome data S. Therefore, the correction state Signal 8D continues to output @H'''.

The correction state signal 8D is supplied to the shift register 80 via the switch 130, and is stored in addresses B to B44 of the RAM 30 in the same manner as in the second operation described above. This storage situation is shown in WI6 Figure CK.

Even after the 82-bit syndrome data S is supplied to the correction state detection circuit 120, the shift clock 5CLK for 1 byte is further supplied to transfer the correction state signal SD to the RAM.
(Capital) address B41. At this time, as described above, if there is even one bit of @1'' data in the 82-bit syndrome data, the correction state signal SD becomes "H". Therefore, in the structure shown in FIG. 6d,
If it is not corrected correctly, 1 of address B4;
All bytes are stored as "1" (@FF in hexadecimal), if the correction was successful.

10'' is stored in the block. Therefore, this address Bu
By referring to , it is possible to detect whether or not the correction was performed normally.

When the storage of 46 bytes of data is completed, the decoder 110 outputs Qt*b. This Ql! b is Ql! Since the counter 108 is counted up as , Q,4 (FIG. 3f) is output. This Q! 4
The output is FFl0I, 102 via the inverter 114.
Since it is supplied to the reset terminal of %FFLOI,
102 is reset. Therefore, counters 106-1
08 is reset and stops the color/color operation, so the error correction operation consisting of the first to third operations is completed.

As explained above, in this embodiment, the correction state detection circuit 120 reads out the 82-bit syndrome data S held in the syndrome register one bit at a time, and this data S is changed from 90'' to @1''. Since it is detected that the error correction operation has not been performed normally by holding that the error correction operation has changed, an 82-person OR circuit is not required and the circuit scale does not increase.

Further, in this embodiment, writing of data to be corrected into the syndrome register and reading of corrected data from the serial/parallel conversion shift register are performed by hardware. Therefore, the time required for inputting and outputting data can be shortened, and error correction operations can be performed at high speed. The judgment output C for determining whether or not to correct an error is synchronized with the data D to be corrected at the timing when the data D is written to the parallel-to-serial conversion shift register, which was previously necessary. A 272-bit shift register is not required, and the circuit scale can be reduced.

This is extremely effective especially when integrating an error correction circuit into an IC.

Furthermore, in this embodiment, the address Bo of the RAM 30 is
Since the data before error correction stored in Bu in transmission units is re-stored in processing units at addresses B0 to Bu after error correction, the CPU can directly process the data.

Note that the present invention is not limited to teletext systems.

〔Effect of the invention〕

According to the present invention, it is possible to detect whether error correction has been performed normally without increasing the size of one circuit.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing one embodiment of the error correction control circuit of the present invention, FIGS. 2 and 4 are circuit diagrams showing details of a part of the embodiment shown in FIG. 1, and FIG. 5 is a meme chart explaining the operation of the embodiment shown in FIG. 1, FIG. 6 is an explanatory diagram explaining the operation of the embodiment, FIG. 7 is a configuration diagram showing the format of the teletext signal, and FIG. The figure is a circuit diagram showing a conventional error correction control circuit. Data...RAM 40...Parallel-serial conversion shift register blade...Syndrome register ω...Majority circuit 70...Correction circuit (capital)...Series-parallel shift register 90.130...Swi 100・
...Timing generation circuit 120...Correction state detection circuit Representative Patent attorney Noriyuki Chika I4-Figure 5, TJ: Chikura diagram

Claims (1)

[Scope of Claims] In an error correction control circuit that corrects errors in data to be corrected stored in a storage means by performing a syndrome operation, a plurality of bits of syndrome data holding that error correction has been completed normally is provided. The present invention is equipped with a syndrome register shown by , and a correction state detection circuit that reads out the syndrome data held in this syndrome register bit by bit after error correction is completed and detects a correction state based on a change in the syndrome data. Features an error correction control circuit.