JPS617956A - Multiple access control system of memory - Google Patents

Abstract

PURPOSE:To transfer a data in large quantities without lowering a through-put even in case of a device controlled by a CPU whose data bus width is small, by making the number of banks which can be brought to access by once variable in accordance with a device for executing an access to a memory. CONSTITUTION:In case a CPU A executes an access to a memory, addresses A2-An are held in memory address register 102 and inputted to each memory bank. At the same time, by addresses A0, A1 and a memory bank selection control signal, a selecting circuit 103 executes an access to the bank corresponding to the address concerned. Also, a data bus 104 connects a data bus of the bank concerned and a data bus of the CPU A so that a memory 1 byte access from the CPU A can be executed. In case an I/O control circuit B executes an access to the memory, the addresses A2-An are held in the register 102, and by the selection control signal, the bank selecting circuit 103 executes an access to all the banks. In this way, the I/O circuit B can read out and write a data of four bytes simultaneously with respect to the memory.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a multiple access control system for memory banks in a memory constituted by a plurality of banks (areas).

[Prior art]

Conventionally, as a memory multiple access method.

There is multi-bank control of memory in converters and the like.

FIG. 3 shows an example of this multi-bank control.

FIG. 4 shows an example of a two-bank configuration.

In FIG. 3, the memory is composed of a lower bank 301a and an upper bank 301b. Addresses are sequentially assigned to each memory bank 301a, 301b alternately. Referring to FIG. 4, address lines A1 to An common to each memory bank 401a and 401b among address buses A□ to An consisting of n+1 address signal lines.
is held in the memory address register 402 and connected to the address line of each bank. lowest address bit A
O is lower memory bank (even address memory) 401
It is used as a selection signal for a. In addition, the processing format (1
If it is necessary to access the upper memory bank (memory at an odd address) 401b by a byte command/2-byte command, etc., an upper bank selection signal is generated and the upper memory bank 401b is accessed at the same time. As a result, data in at least one of the upper/lower memory banks is accessed.

[Problem that the invention seeks to solve]

However, in the nine-line system, the number of memory banks configured is generally limited by the data bus width of the CPU (Central Processing Unit) (CPU data bus width = total data bus width of each bank). Therefore, when transferring data with a large block length from an external control device (channel device 9 peripheral device control device) in a device using a CPU with a narrow data bus width, the number of accesses to the data area of memory increases, and the CPU throughput is significantly reduced.

The present invention aims to solve the above-mentioned drawbacks, and when a large amount of data block transfer request is generated from an external control device etc., the data bus width is reduced by accessing multiple memory banks simultaneously and reducing the number of memory accesses. It is an object of the present invention to provide a method that enables a large amount of data transfer without reducing throughput even in a device using a small CPU.

[Means for solving problems]

In the present invention, memory is divided into a plurality of banks (areas) to which addresses are sequentially assigned, and one or more memory banks are selected and accessed according to the data bus width of the device accessing the memory. a selection circuit; and a memory data bus selection circuit that selects the data bus of the accessed memory bank from among the data buses of each memory bank according to the data bus width of the device that accessed the memory and connects it to the data bus of the corresponding device. By installing this, even in devices with a small CPU data bus width, multiple memory banks can be accessed simultaneously from an external control device, increasing the amount of data that can be accessed at one time, and allowing large amounts of data to be exchanged with external devices. It is characterized by improving throughput by reducing the number of memory accesses during transfer.

〔Example〕

Next, two embodiments of the present invention will be described.

FIG. 1 shows an example of the basic configuration of the present invention.

In FIG. 1, the nine-line system includes a memory made up of four memory banks 101a to 101d to which addresses are sequentially assigned, and a memory address register 102 for holding memory addresses from devices A and B that access this memory.
, memory bank selection control signal and address lines AO to A1
A memory node (link selection circuit 103) that selects a memory bank to be accessed by
When accessing memory, each memory bank 101
A memory data bus selection circuit 104 selects a bus of an accessed memory bank from among a to 101d and connects it to the data bus of device A. Equipment A, B
The address number of the device is n bits, the data bus of device A is 8 bits (1 bit), and the data bus of device B is 32 bits.
It is assumed that the number of bits (4/ite) corresponds to one address in the memory.

First, when device A accesses memory.

Memory addresses A2 to An are memory address register 1
02 and input to each memory node. At the same time, the memory node (link selection circuit 103) In addition to accessing the memory bank corresponding to the corresponding memory address,
The memory data bus selection circuit 104 is controlled to connect the data bus of the corresponding memory node and the data bus of device A to enable memory access (one node) from device A.

Next, if device B accesses the memory.

Memory addresses A2 to An are memory address register 1
02 and a memory bank selection control signal indicating that device B is accessing the memory.
Memory bank selection circuit 103 accesses all memory banks. This allows device B to simultaneously read or write 4 bytes of data to the memory.

FIG. 2 shows a concrete example of this method.

The second embodiment is a CPU 2 with an 8-bit data bus.
05 (corresponding to device A in Figure 1) and l0C (I10 storage control circuit) that controls data transfer between external devices and memory.
206 (corresponding to device B in FIG. 1).

CPU205. a bus control circuit 207 that monitors memory access conflicts between the l0Cs 206 and grants memory access to either one, and at the same time sends a memory bank selection signal to the memory bank selection circuit 203;
Memory data registers 208a-208 that hold read/write data when the C206 accesses memory
d, and a data transfer control circuit 209 .d that transfers data between these memory data registers and the IOC 206 . and a memory address register 20 similar to that shown in FIG.
2. Memory banks 201a to 201d memory data (
and a step selection circuit 204.

The case where the CPU accesses the memory is the same as the case where device A accesses the memory in FIG.

In FIG. 2, when the l0C206 accesses the memory, it accesses all memory banks in one access, similar to when device B accesses the memory in FIG. 1, and when reading data, it accesses all memory banks. A small memory data register installed to correspond to the data node (2)
The data read from 08a to 208d is latched. Next, the l0C 206 transfers the memory data registers 208a to 2 through the data transfer control circuit 209 independently of the memory.
The data held in 08d is transferred to an external device in units of bytes or units of multiple bytes. -! Ta. When writing data, use data input from an external device.

By storing the data in the memory data registers 208a to 208d and accessing the memory via the data transfer control circuit 209, 4 bytes of data can be written to the memory in one memory access.

In this way, even when a request is made to transfer a large amount of data blocks to and from the data area of the memory from an external device, the number of accesses to the memory is reduced to 1/4 compared to when the data bus is 8 bits.

The throughput is significantly improved compared to the conventional method.

〔Effect of the invention〕

As explained above, one aspect of the present invention is that by making the number of links that can be accessed at one time variable depending on the device that accesses the memory, data length When transferring a long data block, the data transfer can be performed without reducing the throughput of the CPH.

[Brief explanation of drawings]

FIG. 1 is a basic block diagram of an embodiment of the present invention.
FIG. 2 is a concrete block configuration diagram using the configuration of FIG. 1, FIG. 3 is a diagram for explaining the principle of conventional multi-bank control, and FIG. 4 is a block configuration diagram of an example of the conventional technique. In the figure, 101a to 101d, 201a to 201
d is a memory bank, 102.202 is a memory address register. 103, 203 are memory bank selection circuits; 104, 2;
04 is a memory data bus selection circuit. v, V,,,:.

Claims (1)

[Claims] 1. A memory bank in which the memory is divided into a plurality of banks (areas) to which addresses are sequentially assigned, and one or more of the memory banks are selected and accessed according to the data bus width of the device accessing the memory. A selection circuit and a memory data bus selection for selecting the data bus of the accessed memory bank from among the data buses of each memory bank according to the data bus width of the device that accessed the memory and connecting it to the data bus of the corresponding device. The memory bank selection circuit and the memory data bus selection circuit are switched according to the data bus width of the device accessing the memory, so that the number of memory banks accessed simultaneously can be varied. Memory multiple access control method.