JPS6175649A - Buffer management system of communication control equipment - Google Patents

Abstract

PURPOSE:To improve the utilizing efficiency of a buffer memory by giving plural buffer address stacks with different buffer length to a buffer management section and providing a frame length in response to a line attribute and reception frame type to a line control section to apply a buffer acquisition request to the buffer management section. CONSTITUTION:A buffer length L in response to the line attribute and the frame type is given to the line control section at frame reception, which applies a buffer acquisition request to the buffer management section. The buffer management section gives a top buffer address among buffer address stacks having a buffer minimum length being L or over to the line control section. The said buffer address is shown in 8 in figure. The line control section writes the reception frame on a buffer area of a buffer memory represented by the said buffer address. In case of I frame reception, the line control section 3 uses the maximum frame length of the line and in case of the reception other than the frame I, the section 3 uses two bytes as a buffer length to give a buffer acquisition request.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a buffer management system for a communication control device having a buffer memory.

[Background of the invention]

The conventional device is described in the Electric and Telecommunications Public Corporation Research and Practical Application Report Vol. 53 No. 1 "Configuration of Dipa v1si Group Communication System" VC
As described in C, the buffer length of the buffer that the buffer management section provides to the line control section 7 in response to the /<7a acquisition request from the line control section is a fixed value. For this reason, it is necessary to allocate a buffer having the fixed buffer length even to a received frame having a short frame length, resulting in a problem of lowering the buffer memory usage efficiency. In addition, when the line control unit receives a frame with a frame length longer than the fixed buffer length, the line control unit issues a buffer acquisition request to the buffer management unit multiple times, and each time the buffer becomes full, the line control unit issues a buffer acquisition request to the buffer management unit. address must be reported to the processor.

Each time the processor receives this report, it creates a chain information of the 7 address, which increases the processing performance load on the processor, which is especially important when accommodating high-speed lines. It is.

[Purpose of the invention]

An object of the present invention is to provide a buffer management method for a communication control device that improves the usage efficiency of backup memory and reduces the processing load on a processor.

[Summary of the invention]

In the buffer management method of the present invention, the line control unit
The necessary frame length is identified for each received frame according to the attributes of each line and the received frame type, and the buffer management unit provides the line control unit with a buffer having a minimum buffer length equal to or greater than the frame length. The line control unit stores the received seven frames in the buffer thus obtained. Therefore, in the case of the HDLC procedure, for example, by allocating a buffer with a large buffer length to an E-frame with a long frame length, and a buffer with a small buffer length to frames other than E-frames with a short frame length, the backup memory can be saved. Can be used effectively. Even if an e-frame is received, the frame length given to the buffer acquisition request can be changed for each line.
In the case of a large line with frames, by increasing the assigned buffer length, it is possible to avoid the line control unit from making multiple requests for acquisition of frames each time the buffer becomes full. (This is done every time the buffer is full.) (The processor receives the address report and accumulates the e-frames in multiple buffers.) Since the processor does not need to process the address chain, it reduces the processing load of Gumimotu. be able to. Reducing the processing load on the processor is particularly advantageous when accommodating high-speed lines.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows the configuration of a communication control device. 2 is a line control unit;
3 is a processor, 4 is a buffer management unit, 5 is a buffer memory, and 10 is an internal node.
610-61k and 6Lo-6Lm are stacked buffer addresses.

These buffer addresses are initialized by instruction 11 in Gumicera-9''3.The buffer length XJO-LL of each buffer address stack 60 to 6L is also set by processor 3.
It is initialized by

When the line control unit receives a frame, it assigns a buffer length according to the line attribute and frame type and requests the buffer management unit to acquire a buffer. The buffer management unit gives the line control sIC the buffer address of the first tuna from among the buffer address stacks having the minimum buffer length of L or more.

The buffer address is 8 in FIG. The line control unit writes the received frame to the buffer area of the backup memory indicated by the buffer address. (12 in Figure 1) 1st
9 in the figure is a report from the line control unit to the processor, such as frame reception.

FIG. 2 shows a frame length identification circuit of the line control unit 2 in which HDLC operators are arranged in a row. A line address register 15 indicates the line address currently being processed by the line control unit. Memory 14, addressed by register 15, stores the maximum frame length 150-151 of each line. 16 is a receiving line, and 19 is a receiving data register. Via in register 19) 2GU frame identification bit is 6,
In the case of HDLC mode, the first of the second octet (control section)
It's bit. In Efrem, the pit is 0. 1
This circuit is a 7c1liXCLCr8IV10R circuit, which compares pit 15 with a fixed value 0, and outputs Q if it is an Eframe, and outputs 1 if it is not an Eframe. Reference numeral 18 denotes a selector circuit which outputs buffer acquisition request information 7, and selects the maximum Eframe length of the line in the case of an Eframe, and selects a fixed value of 2 in the case of a non-Eframe.

As explained above, the line control unit 3 can issue a buffer acquisition request by setting the maximum frame length of the line in the case of receiving an E-frame and 2 bytes as the length in the case of receiving a frame other than an E-frame. This can be realized not only in HDLC procedures but also in the transmission control procedure of each building by determining the received frame length in the line control unit and issuing a buffer acquisition request by assigning the buffer length.

〔Effect of the invention〕

As described above, according to the present invention, there is no need to allocate a buffer with a large buffer length to a received frame with a short frame length, and the buffer usage efficiency is excellent. Furthermore, since there is no need for the processor to allocate buffers multiple times for one frame and store the chain of buffers in the processor, the processing load on the processor is reduced and the throughput of the communication control device is improved.

[Brief explanation of drawings]

FIG. 1 is a schematic diagram of a communication control device according to an embodiment of the present invention, and FIG. 2 is a frame length identification circuit diagram of a line control section. 1... Communication control device 2... Line control unit 5... Processor 4... Buffer management unit 5... Pack memory 8... Acquisition hack 7
Address 9...Report of 7th frame reception, etc. 10...Internal path 12th...Receive 7th frame storage 16...Receive 1i 18...Selector 19...Receive register 20...Edit Frame identification pit. Figure 1

Claims (1)

[Claims] 1. Stack the line control unit that controls multiple lines, the buffer memory that stores communication data, and the buffer address.
It is equipped with a buffer management unit that manages a buffer management unit and a processor that runs a communication control program, the buffer management unit has a plurality of buffer address stacks with different buffer lengths, and a line control unit that controls frame lengths according to line attributes and received frame types. a buffer acquisition request to a buffer management unit, and the buffer management unit provides a buffer address in a buffer address stack having a minimum buffer length greater than or equal to the frame length to a line control unit. buffer management method.