JPS6173367A - Semiconductor device - Google Patents

Abstract

PURPOSE:To form a capacitor having large capacitance without increasing the size of a chip by forming a diffusion layer to the main surface of a substrate under a wiring and shaping a conductive layer onto the diffusion layer through an insulating film. CONSTITUTION:An N-type diffusion layer 4 is shaped to a wiring region 3 section on the main surface of a semiconductor substrate 1. An oxide film 6 is formed onto the layer 4, and a conductive layer 7 is shaped onto the film 6. An inter-layer insulating film 8 is formed extending over the layer 7 and the upper section of a field oxide film, and signal lines l1-ln and supply lines L1, L2 are shaped onto the film 8. In such constitution, the layer 7 is brought into contact with the supply line L2, and the supply line L1 is brought into contact with the layer 4 through an N<+> region 5. Consequently, capacitance between the layer 7 and the layer 4 is connected between the supply lines L1 and L2. Since the capacitance is considerably large, a comparatively large capacitor is interposed between the supply lines L1 and L2, thus constituting the capacitor having large capacitance without increasing the size of a chip.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to semiconductor technology and to a technology that is particularly effective when used in the formation of wiring, for example, a technology that is effective when used to form a power supply line in a semiconductor integrated circuit device. .

[Background technology] Dynamic RAM (Random Access Memory)
A semiconductor integrated circuit device (hereinafter referred to as IC) such as the above is shifted from a standby state to a data read or write operation by changing a control signal supplied from the outside.

At this time, a large current (peak current) is suddenly passed through the circuit, so if the impedance of the power supply is not zero, the power supply voltage will fluctuate, which will add noise to the power supply voltage and cause circuit malfunction. There is a risk.

Therefore, by attaching an external capacitor to the IC power supply terminal,
By enclosing a discrete capacitor in the IC package and connecting the capacitor to the power supply terminal of the IC chip, the impedance of the external power supply is lowered and fluctuations in the power supply voltage due to peak current are suppressed.

Incidentally, in an IC such as a dynamic RAM, an internal circuit is generally provided in the center of a semiconductor chip, and a cover sofa circuit and a wiring area are provided around the internal circuit. Then, a power supply line is routed along with a signal line using aluminum wiring in a wiring area around this chip.

Moreover, in this case, in order to reduce the stray capacitance of the signal line, as shown in FIG.
y12t...In and power supply lines L1+L2 are provided.

Therefore, the impedance of the power supply lines L1tL2 etc. becomes large, so even if the external power supply is an ideal power supply with zero impedance and a capacitor is connected to the power supply terminal of the IC, the impedance inside the IC increases. It has been found that when a large current is suddenly applied, the power supply voltage fluctuates due to the impedance of the power supply line inside the IC, potentially causing the circuit to malfunction.

However, with conventional semiconductor integrated circuit technology, it is difficult to form a capacitor with a large capacitance inside a chip without increasing the chip size.

[Object of the Invention] An object of the present invention is to provide a semiconductor technology that prevents a circuit from malfunctioning even if a large amount of power is suddenly applied to an IC.

Another object of the present invention is to provide a semiconductor technology that allows a capacitor with a large capacity to be formed inside a semiconductor chip without increasing the chip size.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Summary of the Invention] Representative inventions disclosed in this application will be summarized as follows.

That is, by forming a diffusion layer on the main surface of the substrate under the wiring formed in the wiring area, and forming a conductive layer on this diffusion layer with an insulating film interposed therebetween, the gap between the conductive layer and the diffusion layer is formed. A relatively large capacitance is formed in the conductive layer and the diffusion layer, thereby making it possible to form a capacitor with a large capacitance without increasing the chip size. By connecting the capacitance between the layers and the power supply line to the power supply line and lowering the impedance of the power supply line, the above purpose of suppressing fluctuations in the power supply voltage due to changes in current and preventing malfunction of one circuit is achieved. It is something.

[Embodiment 1] Figure 2 shows the present invention in an MO such as a dynamic RAM.
An example of application to an S integrated circuit is shown.

In this embodiment, a semiconductor substrate 1 such as single crystal silicon is used.
An N-type diffusion layer 4 is formed in a portion to be the wiring region 3 on the main surface of the main surface, and has a width approximately the same as the width of the wiring region 3. An N+ region 5 for making contact is formed. And this N+ area 5
A relatively thick field oxide film 2 called LOGO 3 is formed on the main surface of the substrate on both sides of the N-type diffusion layer 4, that is, the wiring region 3.
It is separated from an active region in which a semiconductor element such as an OSFET is formed.

Further, on the N-type diffusion layer 4, a relatively thin oxide film (
A Si02 film) 6 is formed, and a conductive layer 7 made of polysilicon (polycrystalline silicon) of the same size is formed on this oxide film 6. Further, over the polysilicon layer 7 and the field oxide film 2, PSG
All interlayers like membrane (phosphorus silicate glass membrane)! !
! On this interlayer insulating film 8, signal lines 11+12+...ln and power supply lines L1 . L2 is formed.

In this case, the power supply line L1 is upper Nil! It is arranged so as to be located above the N+ region 5, and the power supply line L2 is arranged so as to be located above the polysilicon layer 7. Although not particularly limited, the power line L1 is connected to a power supply voltage Vcc such as +5V, and the power line L2 is connected to a circuit grounding point (Ov
) is connected to a power supply voltage Vss.

The power lines L1 and L2 are connected to the N through contact holes 9a and 9b formed in the interlayer insulating film 8.
4'' region 5 and polysilicon layer 7, respectively.

According to the above structure, the polysilicon layer 7 under the signal lines 11-in and the N-type diffusion layer 4 on the main surface of the substrate face each other with the thin oxide film 6 interposed therebetween, and the polysilicon layer 7 is The power line L2 is in contact with the power line L2, and the power line L1 is in contact with the N type diffusion layer 4 via the N+ region 5. Therefore, power lines L1 and L
Between 2.

The capacitance between polysilicon layer 7 and N-type diffusion layer 4 is connected. Moreover, since the N-type diffusion layer 4 and the polysilicon layer IM7 are formed continuously under the wiring region occupying a relatively large area, the capacitance between the N-type diffusion layer 4 and the polysilicon layer 7 is quite large. Therefore, if the entire wiring area is used, a capacitor of 1000 pF or more can be easily obtained.

In this way, by inserting a relatively large capacitor between the power supply line and L2, in the dynamic RAM of the embodiment, f6. The impedance of the veins becomes low. As a result, a large current suddenly flows into the chip due to changes in externally supplied control signals such as the RAS signal (row address strobe signal) and CAS signal (column address strobe signal). Therefore, the power supply voltage will not fluctuate greatly even when the power supply voltage is changed.

Moreover, in the above embodiment, the capacitor for lowering the impedance of the power supply line is formed under the wiring area, which is an inactive area where the semiconductor elements constituting one circuit are not formed, resulting in a total increase in chip size. A capacitor with a large capacity as described above can be constructed without this.

Furthermore, in the dynamic RAM of the above embodiment, the N-type diffusion layer 4 and the polysilicon layer 7 constituting the capacitor can be formed without adding any new process in the following manner.

That is, a memory cell structure as shown in FIG. 3 has been proposed for a dynamic RAM consisting of a known 1MO8 type memory cell consisting of a capacitor for storing information charges and a selection switch MOSFET.

In the figure, one electrode of a capacitor for storing information charges is formed from the first polysilicon layer 17 from the field oxide film 2 to the gate oxide film 16. An N-type diffusion layer 14 is previously formed on the main surface of the substrate by ion implantation. The capacitance between the polysilicon layer 17 and the N-type diffusion layer 14 constitutes a capacitor for storing information charges. Thereby, a capacitance is formed even if the potential of the polysilicon electrode is VssC ground.

In addition, in FIG. 1, 15 is an N+ diffusion region which becomes the source and drain region of the selection switch MO5FET constituting the memory cell, 20 is its polysilicon gate electrode,
21 is an oxide film formed on the surface of the polysilicon gate electrode 20, and 22 is an aluminum signal line forming a bit line.

Dynamic RAM with such a memory cell structure
When applying the above embodiment to
Simultaneously with the formation of the N-type diffusion layer 4 and the polysilicon layer 7 under the wiring region. Furthermore, the N+ diffusion region 5 of FIG. 2 is formed at the same time as the N1 diffusion region 15 which becomes the source and drain regions of the third (i!il) selection switch MOSFET.

In this way, the capacitor for reducing power supply line impedance in the above embodiment can be formed under the wiring area without adding any new steps to the dynamic RAM process.

However, in the above case, the polysilicon layer 7 formed under the wiring region may be formed simultaneously with the gate electrode 20 of the MOSFET. Although not shown in FIG. 2, an oxide film may be formed on the surface of the polysilicon layer 7 in order to avoid complicating the process.

[Example 2 A second embodiment of the invention is shown in FIG.

- In this embodiment, the aluminum layer constituting the power supply line LX (or Ll) is placed above the polysilicon layer 7 and the N-type diffusion layer 4 formed under the wiring region with the interlayer insulating film 8 interposed therebetween. It is formed to cover. Polysilicon layer 7 is brought into contact with power supply line Lz (or Ll) at an appropriate location not shown.

Therefore, according to the structure of this embodiment, the power supply line L1 (
A capacitance is also formed between Ll) and the polysilicon layer 7,
This capacitance, together with the capacitance between polysilicon layer 7 and N-type diffusion layer 4, is connected between power supply lines L1 and Ll. As a result, the capacitance of the impedance reducing capacitor connected to the power supply line becomes even larger.

In the above case, the power supply fiL1 (Ll) is formed so as to cover the entire upper part of the polysilicon layer 7, but the power supply line is formed so as to cover a part of the polysilicon layer 7.

(Ll) may also be formed.

[Effects] (1) A diffusion layer is formed on the main surface of the substrate under the wiring formed in the wiring area, and a conductive layer is formed on this diffusion layer with an insulating film interposed therebetween. Due to the effect that a relatively large capacitance is formed between the capacitor and the diffusion layer, a capacitor with a large capacitance can be formed without increasing the chip size.

(2) A diffusion layer is formed on the main surface of the substrate under the wiring formed in the wiring area, and a conductive layer is formed on the diffusion layer with an insulating film interposed therebetween, and a power supply line is connected to the conductive layer and the diffusion layer. Because I made it contact.

The capacitance between the conductive layer and the diffusion layer is connected to the power line and the impedance of the power line is reduced, suppressing fluctuations in the power supply voltage due to changes in current and preventing circuit malfunctions. It has the effect of being able to.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, in the above embodiment, a polysilicon layer is formed on the diffusion layer via a gate oxide film and used as a capacitor, but the electrode of the capacitor is not limited to polysilicon.

In a process using aluminum multilayer wiring technology, it is also possible to use it as the first aluminum layer.

[Field of Application] In the above explanation, the invention made by the present inventor will mainly be explained in terms of the field of application, which is the background of the invention, which is dynamic RAM.
Although the present invention has been described with reference to the application to MOS integrated circuits such as MOS integrated circuits, the present invention is not limited thereto, and can be applied to all semiconductor integrated circuits that require relatively large capacitors.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view showing an example of the structure of a wiring region in a semiconductor integrated circuit, FIG. 2 is a cross-sectional view showing an embodiment of the present invention, and FIG.
FIG. 4 is a cross-sectional view showing an example of the structure of a dynamic RAM memory cell to which the present invention is applied. FIG. 4 is a cross-sectional view showing another embodiment of the present invention. l...Semiconductor substrate, 2...Field oxide film,
3... Wiring region, 4... N-type diffusion layer, 5...
- N1 region, 6... oxide film, 7... conductive layer (polysilicon layer), 8... interlayer insulating film, 9a, 9b...
...Contact hole, 14...N-type diffusion layer, 1
5...N+ diffusion region (source, drain region). 16... Gate oxide film, 17... Polysilicon layer, 20... Polysilicon gate electrode, 21...
・Oxide film, 22...Aluminum signal line, ■1~In・°
°°Signal line, L1. L2...Power line. Figure 1 Figure 3 Figure 4

Claims (1)

[Claims] 1. In a wiring region provided in a semiconductor substrate on which a semiconductor integrated circuit is formed, a diffusion layer is formed on the main surface of the semiconductor substrate under the wiring formed in the wiring region, and this diffusion layer A semiconductor device characterized in that a conductive layer is formed on the conductive layer with an insulating film interposed therebetween, and wiring is formed on the conductive layer with the insulating film interposed therebetween. 2. The diffusion layer or the conductive layer is connected to a power supply line formed on the conductive layer via an insulating film, as set forth in claim 1. Semiconductor equipment. 3. The semiconductor device according to claim 1 or 2, wherein the conductive layer is made of polysilicon. 4. Capacitor for information charge storage and selection switch MO
A patent for a dynamic memory having a memory cell consisting of an SFET, characterized in that the diffusion layer is formed in the same process as a diffusion layer formed under a polysilicon electrode constituting an information charge storage capacitor. A semiconductor device according to claim 1, 2, or 3.