JPS6171715A - Duty cycle discrimination circuit - Google Patents

Abstract

PURPOSE:To discriminate the duty cycle with simple constitution by constituting the title circuit with a capacitor cutting off a DC component of an input pulse, a multi-level comparator having plural comparators and voltage division resistor groups and a discriminating circuit discriminating the duty cycle based on the output of the comparators. CONSTITUTION:An input pulse from an input terminal +4 of the duty cycle discriminating circuit 1 is subjected to DC component cut-off by a capacitor C and the input voltage of the multi-level comparator 2 changes corresponding to the duty cycle of the input pulse. For example, when an input pulse with the same voltage level V and different duty cycle as shown in figures A, B is given to the input terminal 4, it is given to one input terminal + of comparators 3a, 3b... as signals different from voltage levels V', V'' shown respectively in hatched lines in the figures A, B and an output corresponding to the duty cycle of the input pulse is given to the discrimination circuit 3 from the multi-level comparator 2.

Description

DETAILED DESCRIPTION OF THE INVENTION <Field of Industrial Application> The present invention relates to a duty cycle determination circuit for determining the duty cycle of an input pulse.

<Prior art> Generally, when transmitting information, this is done by changing the frequency, amplitude, duty cycle, etc. of a signal. Among these, when the duty cycle is used, It is necessary to obtain information by determining the duty cycle of the pulse signal. Conventionally,
To determine the duty cycle of such a pulse signal, use a microcomputer, counter IC, etc. to determine whether the human pulse is at high level or low level for each clock, and then determine whether the pulse is at high level or low level. Level time intervals etc. are determined digitally according to the program. This makes the configuration complicated and expensive.

<Problems to be Solved by the Invention> The present invention has been made in view of the above-mentioned points, and an object of the present invention is to provide a duty cycle determination circuit having a simple configuration and being inexpensive. .

<Means for Solving the Problems> In order to achieve the above-mentioned object, the present invention includes a duty cycle discrimination circuit that includes a capacitor that cuts the DC component of the input pulse, a plurality of comparators, and a partial voltage (vertical voltage). The multilevel comparator has a multilevel comparator, and a determination circuit that determines the duty cycle based on the output of the multilevel comparator.

<Example> Hereinafter, an example of the present invention will be described in detail with reference to the drawings. FIG. 1 is a circuit diagram of an embodiment of the present invention. The duty cycle determination circuit 1 of this embodiment includes a capacitor C for cutting off the DC component of the input pulse, a diode D for shorting the negative side of the AC needle, and a plurality of comparators 3a.

3 b, 3 c- and voltage dividing resistor group R1, R2, R3
The multilevel comparator 2 has a multilevel comparator 2, and a determination circuit 3 that determines the duty cycle of an input pulse based on the output of the multilevel comparator 2.

Multiple comparators 3a of multilevel comparator 2
, 3b, 3c, each one of the input terminals is connected to a capacitor C.
The other input terminal - is commonly connected to each connection part a of the voltage dividing resistor groups R1, R2, R3.

b, c, . . . individually. Each comparator 3
The other input terminals of a, 3b, and 3c are supplied with different reference voltages obtained by dividing the voltage of the power source REF by a group of voltage dividing resistors. This multilevel comparator 2 provides the determination circuit 3 with an output corresponding to the input terminal provided from each one of the input terminals.

The input pulse from the input terminal +4 of the duty cycle discrimination circuit 1 is supplied to the multilevel comparator 2 after its DC component is cut off by the capacitor C. By cutting the DC component in this way, the input voltage of the multilevel comparator 2 changes in accordance with the duty cycle of the input pulse. For example, when input pulses with the same voltage level and different duty cycles are applied to input terminal 4 as shown in Figure 2 (A , the negative side component of which is outputted by diode D, thereby producing voltage levels v', v''(v'<v'”)
Each comparator 3a, 3b,
It is given to one input terminal of ....

In this way, the input terminal of each one of the plurality of comparators 3a, 3b, 3c, etc. of the multilevel comparator 2 has a voltage corresponding to the duty cycle of the human pulse, so the multilevel comparator 2
From there, an output corresponding to the duty cycle of the input pulse is given to the determination circuit 3.

For example, in the case of the human-powered pulse shown in FIG. 2(A), since its level ■′ is low, only the comparator 3a of the multilevel comparator 2 gives a high-level output to the determination circuit 3, and the pulse shown in FIG. 2(B) In the case of an input pulse, since its level ゛° is higher than the level V'' of the input pulse, not only the comparator 3a of the multilevel comparator 2 but also the multilevel comparators 3b, 3b, . . .
Outputs corresponding to the differences in the duty cycles of the input pulses are given to the decision circuit 3, such as giving a high-level output to the decision circuit 3 from . As a result, the duty cycle of the input pulse is determined by the determination circuit 3.

Furthermore, in the present invention, a voltage corresponding to the duty cycle of the input pulse is applied to the multilevel comparator 2, and the duty cycle of the input pulse is determined based on the output of the multilevel comparator 2. It is not necessary to determine whether the input pulse is at high level or low level for each clock, and also to determine the time interval between high level or low level, and the duty cycle can be determined with a simple configuration.

<Effects of the Invention> As described above, according to the present invention, there is provided a duty cycle determination circuit for determining the duty cycle of an input pulse, which includes a capacitor for cutting the DC component of the input pulse, and a plurality of comparators. and a multilevel comparator having a group of voltage dividing resistors, and a determination circuit that determines a duty cycle based on the output of the multilevel comparator, wherein one corresponding input terminal of each of the summer number comparators is The capacitors are connected in common, and each corresponding other input terminal is individually connected to each connection part of the voltage dividing resistor group, so the configuration is simple and inexpensive. It becomes possible to determine the utility cycle.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of one embodiment of the present invention, FIG. 2 and FIG.
The figure is a waveform diagram of input pulses. 1 Duty cycle discrimination circuit, 2... multi-level comparator, 3 Judgment circuit, 3 a, 3 b
, 3C comparator, R1, R2, R3... voltage dividing resistor group.

Claims (1)

[Claims] (1) A duty cycle determination circuit for determining the duty cycle of an input pulse, the circuit comprising: a capacitor that cuts the DC component of the input pulse; a multilevel comparator having a plurality of comparators and a group of voltage dividing resistors; a determination circuit that determines the duty cycle based on the output of the level comparator, one input terminal of each of the plurality of comparators is commonly connected to the capacitor, and the other input terminal of each of the plurality of comparators is connected in common to the capacitor. A duty cycle discrimination circuit characterized in that it is individually connected to each connection part of a group of voltage dividing resistors.