JPS6168647A - Data processing device - Google Patents

Abstract

PURPOSE:To eliminate a dedicated bus and to reduce a semiconductor chip area by utilizing an inner bus of CPU and connecting an input/output port thereto. CONSTITUTION:An input/output port 23 is connected to an inner bus 18. Also the inner bus 18 is connected to an input side of a multiplexer 31 through a bus 31 so that data from the inner bus 18 and data from a memory 11 area switched by a multiplexer 13 and set at an instruction register 15. Furthermore, a bus 16 is connected to the bus 18 through a bus 32 so that the contents of the instruction register 15 area supplied to the inner bus 18. In case of test, the input/output port 23 is set to input state by the signal sent from a terminal 27, and the test instruction is issued from outside to the inner bus 18 through the input/output 23 by giving timings M5 and M6 other than the instruction execution cycles issued from timing generator from a terminal 37.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a central processing unit with a built-in memory, and particularly to a one-chip microco/pie equipped with a test circuit.

First, a conventional information processing device of this type will be explained with reference to FIG. A program in a read-only memory 11 provided in a central processing unit (hereinafter referred to as CPU) is read, and the read instructions are given to a multiplexer 13 through a bus 12.

The output of the multiplexer 13 is set in the instruction register 15 through the bus 14, and this instruction is given to the decoder 17 through the bus 16, decoded by the decoder 17, and further processed and executed by an arithmetic unit (not shown). It is output to the output boat 19 through the internal bus 18, or the input source.

Data is read into the internal bus 18 through 21.The effective cycle of this instruction is, for example, as shown in FIG. The decryption process is executed in M4. This M...
The timing of M4 is the instruction execution cycle.

In order to test the instruction execution processing operation of the CPU or to test the contents of the memory 11, an input/output board 23 is provided. Data from this input/output port 23 is sent to the multiplexer 13 through a dedicated instruction bus 24 that is not used for purposes other than testing.
given to.

Multiplexer 13 can select data on either bus 12 or 24 by a signal from terminal 25. Also, a bus 16 from the instruction register 15 to the decoder 17
is branched so that the contents of the instruction register 15 are given to the input/output port 23 via the output-only bus 26, which is also not used for purposes other than testing. The input/output port 23 is controlled by a signal from the terminal 27 to be used as an input port or as an output port.

When testing by giving an external command and executing it, the trap sets the input/output port 23 to the input state by the signal from the terminal 27, and synchronizes with the timing Mt and Mt during the command execution cycle shown in FIG. The command is taken in from the test bus 24 and given to the multiplexer 13 through the test dedicated bus 24. At this time, the multiplexer 13 selects the data on the test dedicated bus 2491g based on the signal from the terminal 25 and applies it to the instruction register 15. instruction register 15
The external command set to is decoded by the decoder 17 and executed. Timing Ml.

At M4, the output of the CPH, that is, the execution result of the 9 instructions, is inspected. This tests whether the command was executed correctly.

When testing the memory 11, the input/output port 23 is set to an output state by the signal applied to the terminal 27, and the multiplexer 13 is set so that the read data 12 from the memory 11 is supplied to the instruction register 15 by the signal applied to the terminal 25. Can be switched. Therefore, the nine instructions read from the memory 11 at timings M, , M, are stored in the instruction register 15 through the multiplexer 18, and at timings MS, M
4 through the test dedicated bus 26 at the output port 23
The contents of the memory 11 are tested.

As described above, in the conventional test of a data analysis device using a CPUK having an internal memory, an input/output port 23, a test dedicated bus 24 for command input, and a test dedicated bus 26 for output retrieval are provided.

The use of such a large number of dedicated buses has the disadvantage that the area of the semiconductor chip constituting the CPU increases.

An object of the present invention is to provide a data processing device that utilizes an internal bus that originally exists in a CPU and connects input/output ports to it, thereby eliminating a dedicated bus and reducing the area of a semiconductor chip. It is.

According to this invention, the input/output ports are connected to an internal bus,
The configuration is such that data from the internal bus and data read from the memory can be switched by a multiplexer and set in the instruction register. Also, the configuration is such that data set in the instruction register can be supplied to the input/output port via the internal bus.

For example, in FIG. 3, parts corresponding to those in FIG. 1 are given the same reference numerals, and in this invention, an internal bus IJHC input/output port 23 is connected. Further, the internal bus 18 is connected to the input side of the multiplexer 13 through a bus 31 so that the data on the internal bus 18 and the data from the memory 11 can be switched by the multiplexer 13 and set in the instruction register 15. Furthermore, bus 16 is connected to internal bus 18 via bus 32 so that the contents of instruction register 15 can be provided to internal bus 18.

As shown in FIG. 4, timing M1 of the instruction execution cycle
In addition to ~M4, M6 is generated depending on the timing during testing. For example, as shown in FIG.
The following clock pulses are supplied to a timing generation hexadecimal counter 34 and counted. Normally, the timing M, , M, , M is set sequentially every time the clock pulse is counted.
, , M4 are generated, and when the timing M4 occurs, the counter 34 is reset through the inhibit gate 35. Therefore, timings M1 to M4 occur repeatedly.

However, during the test, a signal indicating that the test is in progress is sent from the terminal 36 to the prohibition gate 35, and the prohibition gate 35 enters the prohibited state. Therefore, the clock pulse from the terminal 33 sequentially generates outputs at timings 1M2, Ms, and Vi4, and further generates timings other than the effective cycle, such as Ms and Ms, and from this point on, the full count is reached again at timing M+9M! 1Ms 1M4.

M, , M, occur repeatedly in sequence.

During testing, timing M other than this instruction execution cycle is used.
Commands are input or output through s and Me. In other words, to test instruction execution, input/output board 2
3 is kept in an input state by a signal from the terminal 27, and timings Ms and Me other than the command execution cycle from the timing generator are given from the terminal 37, and a test command is input from the outside and sent to the internal bus 18 through the ti1 cover 23. . The signal is then sent to the multiplexer 13 via the internal bus.

At timings Mi and Mt, the multiplexer 13 is switched to the internal bus side by the signal at the terminal 25. Therefore, the test command input from the input/output board 23 is set in the command register 15. This instruction is decoded by the decoder 17 and the processing is executed at the same timing M as the normal execution timing.

This is done in M4. This result is inspected, for example, at the output port 19, or at the input port 2, as in the past.
1 will be inspected.

When inspecting the contents of the memory 11, the input/output port 23 is set to an output state by the signal at the terminal 27, and the multiplexer 13 is set by the signal at the terminal 25 so that the output of the memory 11 is supplied to the register 15-. . The instruction in the memory 11 being read at timings M, , M, is set in the instruction register 15 through the multiplexer 13 at a timing lull M4. Timing Ms
, Me, the contents of the instruction register 15 are outputted to the input/output board 23 via the internal bus 18 in response to the signal at the terminal 37, so that the contents of the memory 11 can be tested.

As described above, according to the present invention, the internal bus 18 is used to input and output test data, so the test dedicated bus 24 for command input and the test dedicated bus 26 for output shown in FIG. 1 are not required. The area of the semiconductor chip constituting the CPU can be significantly reduced. In addition, although the internal bus is used in this way, during testing, data can be input and output to and from the external device at timings other than the division execution cycle, using the internal bus at the same timing as normal operation. Can be tested.

[Brief explanation of drawings]

Figure 1 is a block diagram showing a conventional data processing device, Figure 2 is a block diagram showing a conventional data processing device.
3 is a block diagram showing an example of the data processing device according to the present invention; FIG. 4 is a diagram showing the relationship between the instruction effective cycle and other timings in the test state; FIG. FIG. 5 is a diagram showing an example of a timing generator. 11: Built-in memory IJ, 13: Multiplexer, 15: Instruction register, 17: Decoder, 18: Internal bus, 19:
Output port, 21: Input port, 23: Input/output port,
25: multiplexer 130 control input terminal, 27: input/output switching control input terminal of the input/output boat, 37: timing other than the command execution cycle is given to operate the input/output boat. π-su

Claims (1)

[Claims] In a data processing device that has a memory in which instructions are stored, an execution unit that executes processing based on the instructions, and an internal bus used for data transfer during execution on the same chip, the execution unit is provided with test instructions externally. A test instruction is given to the execution unit via the internal bus when the instruction is input from the internal bus, and when an instruction in the memory is checked, the instruction in the memory is read out to the outside via the internal bus. A data processing device characterized by: