JPS616846A - Plug-in package with capacitor - Google Patents
Plug-in package with capacitorInfo
- Publication number
- JPS616846A JPS616846A JP59127869A JP12786984A JPS616846A JP S616846 A JPS616846 A JP S616846A JP 59127869 A JP59127869 A JP 59127869A JP 12786984 A JP12786984 A JP 12786984A JP S616846 A JPS616846 A JP S616846A
- Authority
- JP
- Japan
- Prior art keywords
- capacitor
- chip
- package
- pads
- plug
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
- H01L23/642—Capacitive arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19041—Component type being a capacitor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、プリント配線板に使用するプラグインパッケ
ージに関するもので、特に電源とグランド間のノイズを
有効的に吸収することのできるコンデンサ付プラグイン
パッケージの構造に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a plug-in package used for printed wiring boards, and in particular to a plug-in package with a capacitor that can effectively absorb noise between a power supply and a ground. It is related to the structure of
従来の技術
近年、コンピュータの性能はますます高速度のものが要
求されてきており、そのために電子回路は高速度、高集
積度のＩＣチップおよびこれらのＩＣチップを高密度に
実装したプラグインパッケージが実現するに至っている
。このプラグインノくッケージをプリント配線板に実装
して使用した場合、電源とグランド間で発生するノイズ
を吸収することが必須である。2. Description of the Related Art In recent years, computer performance has become increasingly demanding, and electronic circuits are now being manufactured using high-speed, highly integrated IC chips and plug-in packages in which these IC chips are densely mounted. has come true. When this plug-in package is mounted on a printed wiring board and used, it is essential to absorb noise generated between the power supply and ground.
従来この種のＩＣチップを塔載したプラグインパッケー
ジは、第３図に示す様な構造を有していた。そのために
、このプラグインパッケージをプリント配線板に実装し
てノイズ吸収を行なうために、第４図及び第５図に示す
ようにプリント配線板上で、プラグインパッケージの周
囲に単体のコンデンサを実装する方法をとっていた。Conventionally, a plug-in package mounted with this type of IC chip had a structure as shown in FIG. Therefore, in order to mount this plug-in package on a printed wiring board and absorb noise, a single capacitor is mounted around the plug-in package on the printed wiring board as shown in Figures 4 and 5. I had a method of doing this.
しかし、このような実装方法では、プリント配線板にお
ける実装密度が高められないという欠点があった。However, such a mounting method has the drawback that the mounting density on the printed wiring board cannot be increased.
発明が解決しようとする問題点
本発明の目的は、上讃冬点、すなわちプリント配線板の
実装密度が高められないという問題点を解決するプラグ
インパッケージを提供することにある。Problems to be Solved by the Invention An object of the present invention is to provide a plug-in package that solves the problem that the mounting density of printed wiring boards cannot be increased.
問題点を解決するための手段
本発明は上述の問題点を解決するために、セラミック基
板の表面に１個のＩＣチップを搭載するだめの複数個の
ボンディングパッドと、前記セラミック基板の裏面に複
数本のリードピンと、前記ボンディングパッドと前記リ
ードピンとのそれぞれを接続する複数個の接続配線とを
有するブラッグインパッケージにおいて、前記ＩＣチッ
プ用ポンディ／グバッドエリャに隣接して設けられた少
なくとも２個のコンデンサパッド間にコンデンサを搭載
し、かつ前記２個のコンデンサパッドを前記ボンディン
グパッドの電源端子およびグランド端子にそれぞれ内部
接続した構成を採用するものである。Means for Solving the Problems In order to solve the above-mentioned problems, the present invention provides a plurality of bonding pads on the front surface of a ceramic substrate for mounting one IC chip, and a plurality of bonding pads on the back surface of the ceramic substrate. In a plug-in package having a lead pin and a plurality of connection wirings connecting each of the bonding pads and the lead pins, at least two capacitor pads are provided adjacent to the IC chip pad area. A configuration is adopted in which a capacitor is mounted between them, and the two capacitor pads are internally connected to the power supply terminal and the ground terminal of the bonding pad, respectively.
実施例
次に本発明の実施例について図面を参照して詳細に説明
する。Embodiments Next, embodiments of the present invention will be described in detail with reference to the drawings.
本発明の一実施例を示す第１図において、本発明のコン
デンサ付プラグインパッケージは、セラミック基板１と
、ボンディングパッド２と、接続配線３と、リードピン
４と、グイアホール配線５と、コンデンサ電極７をもつ
コンデンサチップ６と、コンデンサパッド８と、コンデ
ンサ接着剤９とから構成されておシ、セラミック基板１
の表面には、ＩＣの端子数に等しい複数個のボンディン
グパッド２と、このボンゲイングパッドエリャに隣接し
て２個のコンデンサパッド８が形成されておシ、ボンデ
ィングパッド２の各々には、セラミック基板１０表面に
形成された複数個の接続配線３の各々がつながれておシ
、さらに接続配線３の各々は、セラミック基板１内に形
成されたグイアホール配線５と接続配線３の各々を経由
してセラミック基板１の裏面に立てられたリードピン４
に接続されている。又、コンデンサパッド８は、それぞ
れグイアホール配線５を経て、ボンディングパッド２か
らの電源及びグランドのラインに内部接続され、かつコ
ンデンサテップ６のコンデンサ電極７に対しコンデンサ
接着剤９により固着接続されている。In FIG. 1 showing an embodiment of the present invention, a plug-in package with a capacitor of the present invention includes a ceramic substrate 1, a bonding pad 2, a connection wiring 3, a lead pin 4, a Guiahole wiring 5, and a capacitor electrode 7. A ceramic substrate 1 is composed of a capacitor chip 6 having a capacitor pad 8, a capacitor adhesive 9, and a ceramic substrate 1.
A plurality of bonding pads 2 equal to the number of terminals of the IC and two capacitor pads 8 are formed adjacent to the bonding pad area on the surface of the . Each of the plurality of connection wirings 3 formed on the surface of the ceramic substrate 10 is connected, and each of the connection wirings 3 is connected via each of the Guiahole wiring 5 and the connection wiring 3 formed in the ceramic substrate 1. Lead pins 4 placed on the back side of the ceramic substrate 1
It is connected to the. The capacitor pads 8 are each internally connected to the power supply and ground lines from the bonding pad 2 via the Guiahole wiring 5, and are fixedly connected to the capacitor electrode 7 of the capacitor tip 6 by a capacitor adhesive 9.
第２図は第１図の実施例にＩＣチップ１０を塔載して、
ＩＣチップの保護用キャップ１３を取シ付けた状態を示
す断面図であシ、ボンディングワイヤ１１、ＩＣ接着剤
１２、キャップ接着剤１４を使用して組み立てたところ
を示している。FIG. 2 shows an IC chip 10 mounted on the embodiment shown in FIG.
This is a sectional view showing a state in which a protective cap 13 for an IC chip is attached, and shows assembly using a bonding wire 11, an IC adhesive 12, and a cap adhesive 14.
以上に述べた本発明に係るコンデンサ付プラグインパッ
ケージは、外形寸法を従来のプラグインパッケージとほ
ぼ同サイズで実現できるので、プる。The above-mentioned plug-in package with a capacitor according to the present invention is advantageous because it can have an external dimension that is approximately the same as that of a conventional plug-in package.
なお第１図の実施例では、コンデンサパッド８にコンデ
ンサチップ６が１測置着接続されているが、さらにノイ
ズ吸収を良くするため、コンデンサパッドを多くして複
数個のコンデンサを搭載することも可能である。In the embodiment shown in FIG. 1, one capacitor chip 6 is connected to the capacitor pad 8, but in order to further improve noise absorption, the number of capacitor pads may be increased to mount a plurality of capacitors. It is possible.
発明の詳細
な説明したように１本発明によれば、ＩＣチップに隣接
してコンデンサを配置し、このコンデンサの両極を電源
およびグランドのライン間に接続する構成を採用するこ
とによ、り、ＩＣチップを実装するプリント配線板の配
線領域の拡大と配線の高密度化ならびに実装部品の高密
度化が可能になる。また電気的特性を優れたものとする
だめのノイズ吸収が可能になるという効果がある。DETAILED DESCRIPTION OF THE INVENTION According to the present invention, by adopting a configuration in which a capacitor is disposed adjacent to an IC chip and both poles of the capacitor are connected between the power supply and ground lines, It becomes possible to expand the wiring area of a printed wiring board on which IC chips are mounted, increase the density of wiring, and increase the density of mounted components. Further, it has the effect of making it possible to absorb noise which makes the electrical characteristics excellent.
第１図は不発ＭＫ係るコンデンサ付プラグインパッケー
ジの一実施例を示す断面図、第２図は第１図の実施例に
ＩＣチップを搭載して保護用キャツブを接着した状態を
示す断面図、第３図は従来のプラグインパッケージの一
例を示す断面図、第４図、第５図はプリント配線板に第
３図の従来のプラグインパッケージとコンデンサとを実
装した状態を示す断面図および全体の斜視図である。
１・・・・・・セラミック基板、２・・・・・・ボンデ
ィングパッド、３・・・・・・接続配線、４・・・・・
・リードピン、５・・・・・・グイアホール配線、６・
・・・・・コンデンサチップ、７・・・・・・コンデン
サ電極、８・・・・・・コンデンサパッド、９・・・・
・・コンデンサ接着剤、１０・・・・・・ＩＣチップ、
１１・・・・・・ボンディングパッド、１２・・・・・
・ＩＣチップ接着剤、１３・・・・・・保護用キャップ
、１４・・・・・・キャップ接着剤、１５・・・・・・
コンデンサ、１６・・・・・・プリント配線板、１７・
・・・・・プリント接続配線、１８・・・・・・スルホ
ール。
第７図
ｂｚ図Fig. 1 is a cross-sectional view showing an embodiment of a plug-in package with a capacitor related to an unexploded MK, Fig. 2 is a cross-sectional view showing a state in which an IC chip is mounted on the embodiment of Fig. 1 and a protective cap is attached. FIG. 3 is a cross-sectional view showing an example of a conventional plug-in package, and FIGS. 4 and 5 are cross-sectional views showing the state in which the conventional plug-in package shown in FIG. 3 and a capacitor are mounted on a printed wiring board, and the entire structure. FIG. 1... Ceramic substrate, 2... Bonding pad, 3... Connection wiring, 4...
・Lead pin, 5...Guiahole wiring, 6・
... Capacitor chip, 7 ... Capacitor electrode, 8 ... Capacitor pad, 9 ...
...Capacitor adhesive, 10...IC chip,
11...Bonding pad, 12...
・IC chip adhesive, 13...Protective cap, 14...Cap adhesive, 15...
Capacitor, 16... Printed wiring board, 17.
...Printed connection wiring, 18...Through hole. Figure 7 bz diagram
Claims (1)
めの複数個のボンディングパッドと、前記セラミック基
板の裏面に複数本のリードピンと、前記ボンディングパ
ッドと前記リードピンとのそれぞれを接続する複数個の
接続配線とを有するプラグインパッケージにおいて、前
記ＩＣチップ用ボンディングパッドエリヤに隣接して設
けられた少なくとも２個のコンデンサパッド間にコンデ
ンサを搭載し、かつ前記２個のコンデンサパッドを前記
ボンディングパッドの電源端子およびグランド端子にそ
れぞれ内部接続したことを特徴とするコンデンサ付プラ
グインパッケージ。A plurality of bonding pads for mounting one IC chip on the surface of the ceramic substrate, a plurality of lead pins on the back surface of the ceramic substrate, and a plurality of bonding pads for connecting each of the bonding pads and the lead pins. In a plug-in package having connection wiring, a capacitor is mounted between at least two capacitor pads provided adjacent to the bonding pad area for the IC chip, and the two capacitor pads are connected to a power source of the bonding pad. A plug-in package with a capacitor that is characterized by internal connections to the terminal and ground terminal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59127869A JPS616846A (en) | 1984-06-21 | 1984-06-21 | Plug-in package with capacitor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59127869A JPS616846A (en) | 1984-06-21 | 1984-06-21 | Plug-in package with capacitor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS616846A true JPS616846A (en) | 1986-01-13 |
Family
ID=14970658
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59127869A Pending JPS616846A (en) | 1984-06-21 | 1984-06-21 | Plug-in package with capacitor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS616846A (en) |
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62260825A (en) * | 1986-05-08 | 1987-11-13 | Agency Of Ind Science & Technol | Optically anisotropic aromatic polyester |
| JPH023423A (en) * | 1988-01-13 | 1990-01-09 | Bayer Ag | Production of aromatic polyester |
| US4945399A (en) * | 1986-09-30 | 1990-07-31 | International Business Machines Corporation | Electronic package with integrated distributed decoupling capacitors |
| US4950057A (en) * | 1987-11-30 | 1990-08-21 | Asahi Kogaku Kogyo Kabushiki Kaisha | Progressive multi-focal ophthalmic lens |
| JPH0324125A (en) * | 1989-05-25 | 1991-02-01 | Hoechst Celanese Corp | Preparation of low color tone polyallylate |
| US5027253A (en) * | 1990-04-09 | 1991-06-25 | Ibm Corporation | Printed circuit boards and cards having buried thin film capacitors and processing techniques for fabricating said boards and cards |
| US5097318A (en) * | 1988-04-04 | 1992-03-17 | Hitachi, Ltd. | Semiconductor package and computer using it |
| US5177670A (en) * | 1991-02-08 | 1993-01-05 | Hitachi, Ltd. | Capacitor-carrying semiconductor module |
| US6043987A (en) * | 1997-08-25 | 2000-03-28 | Compaq Computer Corporation | Printed circuit board having a well structure accommodating one or more capacitor components |
| US6198362B1 (en) | 1998-03-16 | 2001-03-06 | Nec Corporation | Printed circuit board with capacitors connected between ground layer and power layer patterns |
| US7615869B2 (en) | 2005-07-25 | 2009-11-10 | Samsung Electronics Co., Ltd. | Memory module with stacked semiconductor devices |
| TWI448707B (en) * | 2010-12-16 | 2014-08-11 | Semicontest Co Ltd | Semiconductor test apparatus |
-
1984
- 1984-06-21 JP JP59127869A patent/JPS616846A/en active Pending
Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62260825A (en) * | 1986-05-08 | 1987-11-13 | Agency Of Ind Science & Technol | Optically anisotropic aromatic polyester |
| JPH048447B2 (en) * | 1986-05-08 | 1992-02-17 | ||
| US4945399A (en) * | 1986-09-30 | 1990-07-31 | International Business Machines Corporation | Electronic package with integrated distributed decoupling capacitors |
| US4950057A (en) * | 1987-11-30 | 1990-08-21 | Asahi Kogaku Kogyo Kabushiki Kaisha | Progressive multi-focal ophthalmic lens |
| JPH023423A (en) * | 1988-01-13 | 1990-01-09 | Bayer Ag | Production of aromatic polyester |
| US5097318A (en) * | 1988-04-04 | 1992-03-17 | Hitachi, Ltd. | Semiconductor package and computer using it |
| JPH0324125A (en) * | 1989-05-25 | 1991-02-01 | Hoechst Celanese Corp | Preparation of low color tone polyallylate |
| US5027253A (en) * | 1990-04-09 | 1991-06-25 | Ibm Corporation | Printed circuit boards and cards having buried thin film capacitors and processing techniques for fabricating said boards and cards |
| US5177670A (en) * | 1991-02-08 | 1993-01-05 | Hitachi, Ltd. | Capacitor-carrying semiconductor module |
| US6043987A (en) * | 1997-08-25 | 2000-03-28 | Compaq Computer Corporation | Printed circuit board having a well structure accommodating one or more capacitor components |
| US6198362B1 (en) | 1998-03-16 | 2001-03-06 | Nec Corporation | Printed circuit board with capacitors connected between ground layer and power layer patterns |
| US7615869B2 (en) | 2005-07-25 | 2009-11-10 | Samsung Electronics Co., Ltd. | Memory module with stacked semiconductor devices |
| TWI448707B (en) * | 2010-12-16 | 2014-08-11 | Semicontest Co Ltd | Semiconductor test apparatus |
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