JPS6167256A - Read only memory cell - Google Patents

Abstract

PURPOSE:To perform a read only memory cell in which data writing step is nearer to final step by using 2-layer conductive polycrystalline wiring and 1-layer aluminum wiring, providing one data read-out wire for two transistors, and generating four states, thereby increasing the density. CONSTITUTION:The first gate 204 is connected with a row line, and a drain 101 is connected through the second gate 107 and an aluminum 109 to a column line. Data wiring is performed by implanting a P type impurity to the gate width 23 of transistors T1, T2, or implanting a P type impurity to the channel 24 of the transistor T2, and increasing the threshold value of the transistor to control the substantial width of the transistor in four steps. The writing step may be performed by actually ion implanting through an intermediate insulating film 105, a gate 104 and the first gate insulating film even if ions are implanted to the channel after growing the second gate since the transistor of the first gate 104 and the second gate 107 are not vertically superposed.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to a read-only memory element that can be highly densified and that can be used in an element whose data writing process is closer to the final process.

(Prior Art) Conventionally, various structures of MOS type read-only memory elements and their memory writing methods have been proposed as shown in Table 1 below.

NOR type structure among (1) to (5) in Table 1 (i.e., any one data read line, that read line, and the source power supply voltage line (usually ground potential) A typical integrated circuit element structure in which there are multiple transistors connected in parallel between the showed something.

There are cell structures that are not N0Ru structures, that is, AND type structures and AND-NOR combination structures, but these are N0R
Although it is possible to achieve higher density when integrated into an integrated circuit than an element with an ffi structure, it is known that the operating speed becomes slower. Since the present invention, which will be described later, relates to an element having a NOR type structure, the AND type structure will not be discussed in the description of the prior art.

The desired performance of an MO3 type read-only memory element (hereinafter referred to as a mask ROM element) is to have a smaller element area per unit of information and to be able to write data closer to the final step in the process. nru. A much smaller element area is a common requirement for all semiconductor memory elements.

The fact that it is desirable for the data writing process to be closer to the final process means that the time from writing all stored information data to the mask ROM to the final product is shortened, which is considered to be a major drawback of mask ROMs. There is. This is a necessary request from the viewpoint of resolving the problem that it takes a long time to obtain the necessary information t-written into the ROM'.

Now, in (1) to (5) of Table 1, the element plan views are shown in FIGS. 5 to 8. In FIGS. 5 to 8, 1 is an N-type impurity layer, 2 is a first gate, 3 is a second contact, 4 is aluminum, 5 is a first contact, 6 is a second gate, The second contact 3 is made of aluminum 4 and connects the drains of the two MOS transistors to each other and serves as a data read line. Table 1 also shows the area of each element when the same pattern design rule is used, based on research conducted by the inventors. Furthermore, the writing process of each n data is also described.

When comparing each method in Table 1, regarding the element area, (5) < (21= (31 < (4) < (1
), and regarding the data writing process, +2+ = (5) < (31(+1+ = (4
It turns out that the delay is in the order of 1. It will be understood that each of these methods has its own advantages and disadvantages.

Also, Variable geometry 7 pack
s 2 bits int.

everyROM cell (Electronic
s March 24, 1983) states that by changing the W7° ratio of the gate of one transistor,
Realizes 4 types of transistor impedance, 11
Techniques for 2-bit T-storage using solid transistors have been widely disclosed.

(Problems to be Solved by the Invention) However, this method involves changing the W7. ratio of the gates to four times 9, and has the disadvantage that the accuracy of the back-cutting of the gates in the manufacturing process must be increased.

Furthermore, since the data is stored using the W41 ratio of the gate, there is a drawback that the data is stored at an early stage of the process.

(Means for Solving the Problems) The read-only memory element of the present invention uses two layers of conductive polycrystalline silicon and one layer of aluminum as wiring layers, and selects one column line and one row line. n storage element is composed of at least two MOS transistors connected in parallel with at least one of gate length or gate width different, and the drain of each MOS transistor is connected to a column line,
Each source is connected to a source power source, and the gate is connected to a row line.

(Function) According to the present invention, since the read-only memory element is configured as described above, the channel resistance can be adjusted to four levels depending on whether or not ions are implanted into the gates of two MOS transistors having different gate lengths or gate widths. Since 2-bit storage is performed, the above-mentioned problem can be eliminated.

(Embodiments) Hereinafter, embodiments of the read-only memory element of the present invention will be described with reference to the drawings. FIG. 1(a) is a plan view of one embodiment, and FIG. 1(b) is A-
It is a sectional view taken along the A' line.

In both FIG. 1(a) and FIG. 1(b), 10
1 is the drain of the >/Ios transistor, which is formed by an N carved piece and a diffusion layer. Numeral 102 is a source and is formed of N carved material like the drain 101, and is normally at ground potential.

Further, 103 is a P-type substrate to which a ground or negative voltage is applied. 104 is a conductive polycrystalline silicon serving as the gate of the transistor (hereinafter referred to as the first gate), 105 is an intermediate insulating film, 106 is a second gate oxide film, and 107 is different from the first gate. It is conductive polycrystalline silicon (hereinafter referred to as a second gate), and 108 is a through-hole portion connecting the second gate oxide film and the N-type impurity layer 1. 109 is aluminum, 10 is aluminum 1
09 and 107tl are connecting through-hole parts, and 11 is a protective film.

Further, 12 is a window for ion implantation used in the 9th stage of the ROM f″, and 22 is a field oxide film. Here, the source 102, drain 101 and the first
'r' -) 1071' Configures CMOS tiger 7 nostar.

It is constructed as shown in Fig. 1(a) and Fig. 1(b)! ″
The operation of the L7 length mask ROM element will be explained. A semiconductor integrated circuit memory using this element structure consists of a large number of memory matrices in which the first gate 104 is connected to the row line, and the drain 101 is connected to the column line through the second /I'''-) 107 and aluminum 109tl-. υ standing.

Now, data implantation is performed by implanting impurity ions into the channel of the transistor (this implantation is performed through the window 12), and by changing the threshold voltage of the transistor (for example, several volts and IV). rB when reading
, "o" is detected.

FIG. 2 shows an equivalent circuit of FIGS. 1(a) and 1(b).

This figure 2 shows an equivalent circuit for one cell of the memory matrix, B is a column line, W is a row line, G is a ground, and transistors T1 and T2 have different gate widths (for example, Tl gate width 2
3 is 3.5μ, and the gate width 24 of transistor T2 is 2μ.
).

Table 2, indicated by an arrow, shows the state when data is written to the elements shown in FIGS. 1(a) and 1(b).

Table 2: In other words, by implanting a P carved into the gate width 23 (hereinafter referred to as the channel) of the transistors Tl and T2 and increasing the threshold voltages of the transistors Tl and T2, or By implanting a P carved into the channel 24 of the transistor T20 and raising the threshold voltage above the transistor T2, the effective width of the transistor can be controlled in four steps.

In Table 2 above, as an example, the gate width of the transistor T1 is 2μ, and the gate width of the transistor T2 is 3.5μ. In the case of the device structure shown in FIGS. 1(a) and 1(b), three converters are required for sensing information, but one reference cell for each comparator is required.
- Even if the width is 14rlJ.

By using 1'-2,75J and r4.5J, 2-bit information can be detected (see the Sensing diagram on page 123 of the above-mentioned document).

Next, the manufacturing process of the read-only memory element of the present invention having the above-described structure will be outlined with reference to FIGS. 3(a) to 3(V). First, as shown in FIG. 3(a), an oxide film 201 is formed using a P-type semiconductor substrate 103 by selectively oxidizing the P-type semiconductor substrate 103 by photolithography.

Next, as shown in FIG. 3(b), the P-type semiconductor substrate 10
A gate oxide film 202 is formed on the protruding portion of No. 3 by thermal oxidation, and a conductive polycrystalline silicon layer 203 is further laminated thereon using the CVD method.

Next, as shown in FIG. 3(c), the conductive polycrystalline silicon layer 203 and the gate oxide film 202 are selectively removed by photolithography.

Next, as shown in FIG. 3(d), ion implantation or solid-phase diffusion of N carved parts is performed using the conductive polycrystalline silicon layer 203 as a mask, and then this portion is heated to form the N+ layer 203. is formed.

Next, as shown in FIG. 3(e), a thermal oxide film 205 (hereinafter referred to as a gate oxide film) is formed on the substrate by a thermal oxidation method.

Next, as shown in FIG. 3(f), the gate oxide film 205 is
is selectively removed by photolithography, and conductive polycrystalline silicon 206 is laminated thereon by CVD (the first
(contact process, second gate process).

Next, as shown in FIG. 3(g), the conductive polycrystalline silicon 206 and the y-toy oxide film 205 are formed by photolithography.
Selectively remove (second goot step).

Next, as shown in FIG. 3(5), the intermediate insulating film 207t
Lamination is performed using the CVD method, and then this portion is heated.

Next, as shown in FIG. 3(i), the intermediate insulating film 207 is selectively removed by photolithography (second contact step).

Next, as shown in FIG. 3(j), aluminum 208 is laminated and formed by a vapor deposition method.

Next, as shown in the third drawing, the aluminum 208 is selectively removed by photolithography, and then, as shown in FIG. 3(t), a protective film 209 is deposited by the CVD method. In this way, a structure as shown in FIG. 1(b) can be obtained.

The structure, operating principle, and manufacturing method of the first embodiment have been described above.The advantages of this element structure over the conventional element structure are that the element area of 1 bit afC,j) can be reduced;
Another advantage is that data can be written in a process step that is relatively close to the final step.

According to the measurements by the inventors, n is the element per bit when the elements in Figures 1(a) and 1(b) are designed using the same design rules as in Figures 5 to 8. The area will be 26μ-.

This is comparable to the element having the structure shown in FIG. 8, and is sufficiently smaller than the element having the structure shown in FIGS. 5 to 7.

That's naive. The cell structure is equivalent to the cell structure in the above document with the same design rules, and the main reason why the device of this invention is smaller than the device with the structure shown in FIGS. 5 to 7 is that Since the cell with the structure shown in Figure 7 requires one aluminum wiring for one transistor, the pitch of the aluminum wiring determines the size of the element in the row line direction. This is because in the device having the structure shown in FIG. 1(b), one aluminum wire is required for two transistors, and the aluminum wiring pitch does not become a limiting factor for the device area.

Data writing in the first embodiment can be performed in two steps. First writing process (1
) is the conductive polycrystalline silicon 2 in FIG. 3(b).
03t--Ion implantation of P features into the channel of a particular transistor after forming the gate oxide 202 before stacking.

This increases the threshold voltage of the lansostar.

The writing step (2) of the second bud is performed by ion implantation into the channel of the transistor after laminating the electrically conductive polycrystalline silicon 203 in FIG. 3(d) or after forming the thermal oxide film 205 in FIG. 3(e). This is what we do.

The third writing process (3) is the one in which all ions are implanted into the channel of the transistor after the intermediate insulating film 207 is laminated and heated in FIG. 3(h) or after the second contact process in FIG. 3(1). It is.

The writing process (1) is better than the writing process (2).
(3) is written in a slower process than 2).

In particular, the third tucking step (3) is shown in FIG. 1(a).

This writing process is possible because of the element structure shown in FIG. 1(b). In other words, since the transistor part of the first gate 104 and the second gate 107 do not overlap in the vertical direction, even if ions are implanted into the channel after growing the second gate, in reality, the intermediate insulating film 105 and gate 10
4 and the first gate insulator M (+-), which is sufficient to perform the ion implantation in currently technically available ion implanters.

Now, when writing data in the writing process (3), when compared with the writing process of the conventional element structure shown in Table 1, the writing process is the same as that of methods (1), (3), and (41). Method L2 + + (a) It is possible to write at 9 times slower than (a).

A second embodiment of the present invention is shown in FIG.

All symbols in Figure 4 are from Figure 1 (a) and Figure 1 (b).
Same meaning as tliIl:'t. In the first embodiment, the device structure was such that the channel of the transistor and the second gate did not overlap, whereas in the second embodiment, in addition to the second gate, the aluminum was also perpendicular to the channel of the transistor. This is to avoid awarding awards based on direction.

This is made possible by placing the aluminum wiring on top of the field oxide between the two transistor chamfers. According to research conducted by the inventors, the element area per one bit in the second embodiment is 28 .mu.-, which is larger than the first embodiment, but smaller than the conventional device.

Furthermore, in the structure shown in FIG. 4, in addition to the data writing process described in the first embodiment, after selectively removing aluminum in FIG. This can be done only through the film, if-gate, and first gate insulating film. In other words, writing can be performed in a process later than the conventional writing process.

The above explanation is about two transistors with different gate widths. However, similar effects can be obtained using two transistors with different gate lengths. It is also possible to extend the memory to 8-bit storage by connecting three transistors in parallel.

As is clear from the above description, in this invention, two layers of conductive polycrystalline silicon wiring and one layer of aluminum wiring are used, one data readout line is provided for two transistors, and one By generating four states in the data read line of the book, it is possible to achieve a higher density than the conventional mask ROM element, and to realize an element in which the data writing process is closer to the final process.

In addition to this, it is possible to construct a mask ROM element by making some changes to this element structure, which can be easily inferred from the basic characteristics of the present invention.

Furthermore, compared to the cell structure disclosed in the above-mentioned literature, writing can be performed depending on whether or not ion implantation is performed. Therefore, like the cell disclosed in the literature, W7 of r-t
．． Since the degree of dependence on the precision of the ratio is small, the tolerance for manufacturing variations can be widened.

This makes it possible to adopt a smaller design rule, resulting in a smaller cell size and a writing time closer to the final process.

(Effects of the Invention) As described above in detail, according to the present invention, at least two MOS transistors having different gate lengths or gate widths are connected in parallel, and the plurality of MOS transistors are connected in parallel. High density can be achieved by connecting each drain of the run source to a column line, applying a source supply voltage to each source, and connecting the gate to a row line to generate four states on one column line. In addition, it is possible to realize an element in which the data writing process is closer to the final process, and it is also possible to increase the tolerance for manufacturing variations.

Along with this, it is possible to adopt smaller design rules, and the writing time can be brought closer to the final process while maintaining the same cell size.

[Brief explanation of the drawing]

FIG. 1(a) is a plan view of one embodiment of the read-only memory element of the present invention, FIG. Equivalent circuit diagram of one cell of the dedicated memory element, FIG. 3(a) to FIG. Plan views of other embodiments of the read-only storage element, FIGS. 5 to 8, are plan views of conventional mask ROM elements. 10...Through hole portion, 23, 24... Channel, 102... Source, 103... P-type Motoyuki, 1
04...y-), 105... intermediate insulating film, 106...
...Second gate insulating film, 107...Second gate, 10
8...Through hole part, 109...Aluminum. Figure 3 Figure 5 Figure 7 Figure 8

Claims (6)

[Claims] (1) By connecting at least two MOS transistors with different gate lengths or gate widths in parallel and changing the current drive capability of these multiple transistors, three or more types of source-drain connections can be achieved with a fixed gate voltage. A read-only memory element comprising at least one read-only memory cell capable of obtaining impedance. (2) In the read-only memory cell, the current driving capability of the plurality of transistors is changed by independently selecting one of at least two possible states of the threshold voltage of the plurality of transistors, and at least three types are available. The read-only memory element according to claim 1, characterized in that the above source-drain impedance can be obtained. (3) A second conductor is electrically connected to the drains of the plurality of transistors, and the second conductor is electrically connected to the column line of the memory cell matrix. The read-only memory element according to item 1. (4) The read-only memory element according to claim 3, wherein the first and second conductors are made of polycrystalline conductive silicon, and the column lines are made of aluminum. (5) The read-only memory element according to claim 3, wherein in the read-only memory cell, the first conductor and the second conductor do not overlap in a direction perpendicular to the semiconductor substrate. (6) In the read-only memory cell, the channels of the plurality of transistors do not overlap in the vertical direction with respect to the column line and the semiconductor substrate.
Read-only storage element as described in Section 1.