JPS6161439A - Master slice type semiconductor integrated circuit device - Google Patents

Master slice type semiconductor integrated circuit device

Info

Publication number
JPS6161439A
JPS6161439A JP18280684A JP18280684A JPS6161439A JP S6161439 A JPS6161439 A JP S6161439A JP 18280684 A JP18280684 A JP 18280684A JP 18280684 A JP18280684 A JP 18280684A JP S6161439 A JPS6161439 A JP S6161439A
Authority
JP
Japan
Prior art keywords
slice type
master slice
wirings
wiring
checking
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18280684A
Other languages
Japanese (ja)
Inventor
Seiji Niwa
丹羽　清司
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP18280684A priority Critical patent/JPS6161439A/en
Publication of JPS6161439A publication Critical patent/JPS6161439A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/118—Masterslice integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

PURPOSE:To check defects occurring especially during wiring in a manufacturing process by a method wherein some wirings not related to logical circuits already in existence are provided by exploiting hitherto unused input/output terminals and regions not loaded with wirings. CONSTITUTION:Simple wirings are provided by exploiting input/output terminals 1 and wiring-capable regions that are not in service in a master slice type LSI device. Such simple wirings are to be ensured not to affect service circuits. For example, such wirings 2, 3 as indicated by broken lines are provided, to be used for the purpose of checking the serving wirings in the manufacturing process. Such checking includes those for detecting open or short circuits of the like. Defects not involving functional checks out of the defects that a master slice type LSI device may experience may be isolated by a simple continuity test. Accordingly, some complicated functional checks may be replaced with simplified checks in an LSI device of this design, which reduced the steps necessary for the isolation of defective master slice type LSI devices.

Description

【発明の詳細な説明】 〔発明の技術分野〕 この発明はマスタースライス型中導体集積回路装置の構
成方法疋係り、特に使用されていない入出力端子及びチ
ップ上の領域の使用法に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for configuring a master slice type medium conductor integrated circuit device, and particularly to a method for using unused input/output terminals and areas on a chip.

〔発明の技術的背景とその問題点〕[Technical background of the invention and its problems]

半導体集積回路装ｆｉｆｆｉ　（以下ＬＳＩと略す）の
高集積化、高密度化、大規模化に伴ない、ＬＳＩをいか
に効率良く構成するかがますます重要となってきている
。又、製作するＬＳＩの機能が複雑になるため、不良品
の判別に際しても機能チェックがますます困難となって
きている。従来、マスタースライス型中導体集積回路装
置（以下マスタースライス型ＬＳＩと略す）ではその性
質上、使われない領域があるが、これが充分に生かされ
ておらず、不良品のチェックの際にも通常ＬＳＩと同様
の複雑な（幾能チェックが心安であり、不良品のチェッ
クにかなりの時間がかかるという問題があった。2. Description of the Related Art As semiconductor integrated circuit devices (hereinafter referred to as LSIs) become more highly integrated, densely packed, and large-scale, it is becoming increasingly important to efficiently configure LSIs. Furthermore, as the functions of manufactured LSIs become more complex, it is becoming increasingly difficult to check the functions when determining defective products. Traditionally, master slice type medium conductor integrated circuit devices (hereinafter referred to as master slice type LSI) have areas that are not used due to their nature, but these areas are not fully utilized and are often used when checking for defective products. Similar to LSI, complicated (geometrical) checks were not reliable, and there was a problem in that it took a considerable amount of time to check for defective products.

〔発明の目的〕[Purpose of the invention]

この発明は上記問題点の解決のため、マスタースライス
型ＬＳＩにおける使用されていない入出力端子及び使用
されていないチップ上の領域を使って、製造工程での不
良を検出するものであるにれによシ、複雑な機能チェッ
クをする以前に簡単なチェックで第１次の不良品を除く
ことが可能となる。In order to solve the above-mentioned problems, this invention detects defects in the manufacturing process by using unused input/output terminals and unused chip areas in a master slice type LSI. Well, it is possible to eliminate first-order defective products with a simple check before conducting a complicated function check.

〔発明の概要〕[Summary of the invention]

即ち本発明はマスタースライスｍＬｓＩ上ノ未使用の入
出力端子と未使用の配線領域を使って、簡単な配線を行
なう、この配線は実際に使用する回路には影響がない様
に配線する。この配線の導通試験を実施することによシ
、製造工程の特に配線工程で起きた不良をチェックする
。That is, the present invention uses unused input/output terminals and unused wiring areas on the master slice mLsI to perform simple wiring, and this wiring is wired so as not to affect the circuits actually used. By conducting this wiring continuity test, defects occurring in the manufacturing process, especially the wiring process, can be checked.

〔発明の効果〕〔Effect of the invention〕

この発明を採用することにより、マスタースライスｑＬ
ｓ工の不良の５５機機能チェックする必要のない不良（
即ちここでは配線工程で生じた不良）に対して簡単な導
通試験を実施するのみで除去できる。By adopting this invention, master slice qL
55 defective machines in S engineering.Defects that do not require functional checks (
In other words, defects (in this case, defects that occurred during the wiring process) can be removed by simply conducting a simple continuity test.

したがって、複雑な機能チェックによる不良チェックを
軽減することができ、マスタースライス型ＬＳＩの不良
品チェックにかかる負担を大幅に低減する。Therefore, it is possible to reduce the number of defect checks based on complicated function checks, and the burden of checking defective products of master slice type LSIs is significantly reduced.

〔発明の実ＩＭ例〕[Actual IM example of invention]

第２図は本発明を実施する前のマスタースライス型ＬＳ
Ｉ、第１図は第２図のマスタースライス型ＬＳＩＫ本発
明を実施した例を示す。図中、ｌは配線工程チェック用
入出力端子、２は開放チェック用パターン、３は配線工
程チェック用配線、４は短絡チェック用パターン、５は
内部機能セルを示す。Figure 2 shows a master slice type LS before implementing the present invention.
I. FIG. 1 shows an example of the master slice type LSIK shown in FIG. 2 in which the present invention is implemented. In the figure, l indicates an input/output terminal for checking the wiring process, 2 indicates a pattern for checking an open circuit, 3 indicates a wiring for checking the wiring process, 4 indicates a pattern for checking a short circuit, and 5 indicates an internal functional cell.

第１図で破線で示したものは配線工程チェック用の配線
でおる。チェックとしては配線の開放チェック（段切れ
など）と短絡チェック（スペース不足など）が考えられ
５図中の左部と下部に示す。The broken lines in FIG. 1 are wiring for checking the wiring process. Possible checks include checking for open wiring (for breaks, etc.) and checking for short circuits (for lack of space, etc.), as shown on the left and bottom of Figure 5.

第１図に示す様なレイアウトで本発明を実施すれば、第
１図でのマスタースライス型ＬＳＩと第２図のマスター
スライスｆｉＬ、ＳＩの性能は全く同じである。したが
って本発明による効果が充分に生かされる。If the present invention is implemented with a layout as shown in FIG. 1, the performance of the master slice type LSI in FIG. 1 and the master slices fiL and SI in FIG. 2 will be exactly the same. Therefore, the effects of the present invention can be fully utilized.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は第２図に示すマスタースライス型ＬＳＩに本発
明を実施した実施例の平面図、第２図はマスタースライ
ス型ＬＳＩの一例を示す平面図でちる。 代理人　弁理士　則近憲佑　（他１名）第　　１　図FIG. 1 is a plan view of an embodiment in which the present invention is implemented in the master slice type LSI shown in FIG. 2, and FIG. 2 is a plan view showing an example of the master slice type LSI. Agent: Patent attorney Kensuke Norichika (and 1 other person) Figure 1

Claims (3)

【特許請求の範囲】[Claims] （１）１つの半導体チップ上で使用していない入出力端
子及び、配線の通っていない領域の両方を使って、既に
ある論理回路とは無関係な配線を設けることを特徴とす
るマスタースライス型半導体集積回路装置。(1) A master slice type semiconductor characterized by providing wiring unrelated to existing logic circuits by using both unused input/output terminals and areas with no wiring on one semiconductor chip. Integrated circuit device. （２）既にある論理回路と無関係に設ける配線を配線工
程のチェックに使うためにパターンを形成することを特
徴とする特許請求の範囲第１項記載のマスタースライス
型半導体集積回路装置。(2) The master slice type semiconductor integrated circuit device according to claim 1, wherein a pattern is formed to use wiring provided independently of existing logic circuits for checking a wiring process. （３）配線工程チェック用のパターンを配線の開放チェ
ック及び短絡チェック用に形成することを特徴とする特
許請求の範囲第２項記載のマスタースライス型半導体集
積回路装置。(3) The master slice type semiconductor integrated circuit device according to claim 2, wherein a pattern for checking the wiring process is formed for checking for open circuits and short circuits of the wiring.
JP18280684A 1984-09-03 1984-09-03 Master slice type semiconductor integrated circuit device Pending JPS6161439A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18280684A JPS6161439A (en) 1984-09-03 1984-09-03 Master slice type semiconductor integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18280684A JPS6161439A (en) 1984-09-03 1984-09-03 Master slice type semiconductor integrated circuit device

Publications (1)

Publication Number Publication Date
JPS6161439A true JPS6161439A (en) 1986-03-29

Family

ID=16124756

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18280684A Pending JPS6161439A (en) 1984-09-03 1984-09-03 Master slice type semiconductor integrated circuit device

Country Status (1)

Country Link
JP (1) JPS6161439A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63316455A (en) * 1987-06-18 1988-12-23 Nec Ic Microcomput Syst Ltd Gate-array type semiconductor integrated circuit
JPH02220454A (en) * 1988-12-22 1990-09-03 Internatl Business Mach Corp <Ibm> Apparatus having process monitor for thin film wiring and method of process monitoring
JPH0312945A (en) * 1989-06-09 1991-01-21 Toshiba Corp Tape carrier and testing method therefor
JPH04312974A (en) * 1991-01-10 1992-11-04 Nec Corp Master slice integrated circuit

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63316455A (en) * 1987-06-18 1988-12-23 Nec Ic Microcomput Syst Ltd Gate-array type semiconductor integrated circuit
JPH02220454A (en) * 1988-12-22 1990-09-03 Internatl Business Mach Corp <Ibm> Apparatus having process monitor for thin film wiring and method of process monitoring
JPH0312945A (en) * 1989-06-09 1991-01-21 Toshiba Corp Tape carrier and testing method therefor
JPH04312974A (en) * 1991-01-10 1992-11-04 Nec Corp Master slice integrated circuit

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