JPS6159474A - Thin film transistor - Google Patents

Thin film transistor

Info

Publication number
JPS6159474A
JPS6159474A JP59180597A JP18059784A JPS6159474A JP S6159474 A JPS6159474 A JP S6159474A JP 59180597 A JP59180597 A JP 59180597A JP 18059784 A JP18059784 A JP 18059784A JP S6159474 A JPS6159474 A JP S6159474A
Authority
JP
Japan
Prior art keywords
thin film
electrode
film transistor
display
scanning
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP59180597A
Other languages
Japanese (ja)
Other versions
JPH0564357B2 (en
Inventor
淳一 大和田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP59180597A priority Critical patent/JPS6159474A/en
Publication of JPS6159474A publication Critical patent/JPS6159474A/en
Publication of JPH0564357B2 publication Critical patent/JPH0564357B2/ja
Granted legal-status Critical Current

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  • Liquid Crystal (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 〔発明の利用分野〕 本発明は液晶やエレクトロルミネセンス等を用いた平面
型表示装置のうち、表示パネル内にトランジスタ等の能
動素子を形成した、いわゆる、アクティブマトリクス表
示装置に好適な薄膜トランジスタに関する。
[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a so-called active matrix display in which active elements such as transistors are formed within a display panel among flat display devices using liquid crystals, electroluminescence, etc. The present invention relates to a thin film transistor suitable for devices.

〔発明の背景〕[Background of the invention]

アクティブマトリクス表示装置は表示部にスイッチ素子
を形成し、高精細、高品質画質の表示が可能であるとい
う利点をもっている。特に、透明基板上に形成した多結
晶シリコン、あるいは、再結晶化シリコン薄膜を用いた
TPTによシ構成したアクティブマトリクスディスプレ
イは、TPT素子のドレインコンダクタンスgmが大き
いだめ、TPT素子の小型化が可能でめシ、表示画業の
開口率(有効光示部の占める割合)を大きい値としたま
ま、各表示画素の微細化ができ、また、表示の周辺部に
駆動回路を形成できる可能性が大きいため、特に、高精
細なディスプレイに適したTPT素子である。なお、多
結晶シリコンTPTや再結晶化シリコンTPTによるア
クティブマトリクスディスプレイに関連するものは、特
開昭58−”’″−i゛◇″・ 90690号、あるいは特開昭59−31055号公報
に記載されている。
An active matrix display device has a switch element formed in a display portion, and has the advantage of being able to display high definition and high quality images. In particular, active matrix displays configured with TPT using polycrystalline silicon formed on a transparent substrate or recrystallized silicon thin film can be made smaller because the drain conductance gm of the TPT element is large. In fact, it is possible to miniaturize each display pixel while keeping the display aperture ratio (the ratio of the effective light display area) to a large value, and it is also possible to form a drive circuit at the periphery of the display. Therefore, the TPT element is particularly suitable for high-definition displays. Note that matters related to active matrix displays using polycrystalline silicon TPT and recrystallized silicon TPT are described in JP-A-58-90690 or JP-A-59-31055. has been done.

これらの公報ではTPT形状を工夫し、開口率を向上さ
せているが、たとえば、多結晶シリコンTPTや再結晶
化シリコンTPTのように、半導体膜の移動度が大きく
、ロングチャネル構造ノTPT素子が形成できるものは
、さらに、改良の余地がある。
In these publications, the TPT shape is devised to improve the aperture ratio, but for example, the mobility of the semiconductor film is large and the TPT element with a long channel structure, such as polycrystalline silicon TPT or recrystallized silicon TPT, is There is still room for improvement in what can be formed.

〔発明の目的〕[Purpose of the invention]

本発明の目的は、アクティブマトリクス表示パネルにお
いて、衣示部の開口率を改善した、セルファライ/(自
己整合)型の薄膜トランジスタを提供するにある。
SUMMARY OF THE INVENTION An object of the present invention is to provide a self-aligned thin film transistor that has an improved aperture ratio in a display area in an active matrix display panel.

〔発明の実施例〕[Embodiments of the invention]

本発明の一実施例を第1図に示す。すなわち信号電圧を
列方向の画素に印加するための信号電極配線2と液晶に
電圧を印加するだめの表示電極4とをソースまたはドレ
イン電極とし、衣示部の行方向の画素を走査する走査パ
ルスを印加するだめの走査電極配線3をゲート電極とし
た構造のトランジスタである。半導体薄膜1は信号配線
2と走査配線3との下に形成しており、表示電極4と接
続する部分が、信号配線2と走査配線3との下から出る
構造としている。また、このトランジスタのチャネル部
は走査配線3の下に形成される、このため、トランジス
タのチャネル長■はチャネル幅Wに比較して長い、ロン
グチャネル型のトランジスタとなる。このような構造に
することにより、薄膜トランジスタの大部分が配線の部
分に形成でき、表示電極4が宍示部に占める面積の割合
が大きくなム良好な表示特性のディスプレイが構成でき
る。
An embodiment of the present invention is shown in FIG. That is, the signal electrode wiring 2 for applying a signal voltage to the pixels in the column direction and the display electrode 4 for applying voltage to the liquid crystal are used as source or drain electrodes, and a scanning pulse is generated to scan the pixels in the row direction of the display area. This transistor has a structure in which the scanning electrode wiring 3 used to apply the voltage is used as a gate electrode. The semiconductor thin film 1 is formed under the signal wiring 2 and the scanning wiring 3, and has a structure in which a portion connected to the display electrode 4 comes out from below the signal wiring 2 and the scanning wiring 3. Further, the channel portion of this transistor is formed under the scanning wiring 3, so that the transistor has a channel length (2) longer than the channel width (W), making it a long channel type transistor. By adopting such a structure, most of the thin film transistors can be formed in the wiring portion, and a display with good display characteristics can be constructed in which the display electrode 4 occupies a large proportion of the area of the display portion.

第2図は本発明の薄膜トランジスタの製造工程を示す。FIG. 2 shows the manufacturing process of the thin film transistor of the present invention.

これは第1図のn−tt矢視断面を示したものである。This is a cross section taken along the line n-tt in FIG.

(a)ガラス、あるいは、石英などの絶縁性基板6の上
に、多結晶シリコン、非晶質シリコン、まだは、結晶化
シリコン等の半導体薄膜7を形成し、必要な部分を島状
に残す。(b)ゲート絶縁膜8を熱酸化、CVD法、ス
パッタリング、プラズマ酸化等の方法によ多形成する。
(a) A semiconductor thin film 7 of polycrystalline silicon, amorphous silicon, crystallized silicon, etc. is formed on an insulating substrate 6 such as glass or quartz, and necessary portions are left in the form of islands. . (b) Gate insulating film 8 is formed by a method such as thermal oxidation, CVD, sputtering, or plasma oxidation.

なお、ゲート絶縁膜8は半導体薄膜7と連続形成し、そ
の後、半導体薄膜7とゲート絶縁膜8とをまとめて島状
に形成しても良い。(C)走査電極と兼用のゲート電極
9を、多結晶シリコン、あるいは、各種の金属シリサイ
ド等により形成する。(d)ゲート絶縁膜8の一部を除
去し、ソーダ及びドレイン部をイオン打込み、熱拡散、
ディポジション等の方法で形成する。(e)ゲート電極
と信号配線との間の二層配線の層間絶縁膜と薄膜トラン
ジスタのパッシベーションを兼用した絶縁膜11をCV
D法やスパッタリン夛法あるいはスピンオン法等によ多
形成し、ソース、ドレイン部にコンタクトホールをあけ
る。
Note that the gate insulating film 8 may be formed continuously with the semiconductor thin film 7, and then the semiconductor thin film 7 and the gate insulating film 8 may be formed together into an island shape. (C) Gate electrode 9, which also serves as a scanning electrode, is formed of polycrystalline silicon, various metal silicides, or the like. (d) Part of the gate insulating film 8 is removed, and the soda and drain parts are ion-implanted, thermally diffused,
It is formed by a method such as deposition. (e) CVD the insulating film 11 that serves as the interlayer insulating film of the two-layer wiring between the gate electrode and the signal wiring and the passivation of the thin film transistor.
A contact hole is formed in the source and drain portions by the D method, sputtering method, spin-on method, or the like.

(f)ソース、ドレイン電極と兼用した信号配線13と
画素電極12を形成する。これらの電極は両方ともIT
O等の透明電極で形成する構造や、信号配線13をアル
ミニウム等の金属を使用する構造が考えられる。
(f) Signal wiring 13 and pixel electrode 12, which also serve as source and drain electrodes, are formed. Both of these electrodes are IT
Possible structures include a structure in which a transparent electrode such as O is used, and a structure in which the signal wiring 13 is made of a metal such as aluminum.

本実施例ではゲートは自己整合型の構造であシ、走査配
線の位置が多少ずれても、薄膜トランジスタ・のチャネ
ル長りとチャネル幅Wが変化することかないため、特性
の揃った素子を得ることができる。
In this example, the gate has a self-aligned structure, and even if the position of the scanning wiring is slightly shifted, the channel length and channel width W of the thin film transistor will not change, making it possible to obtain an element with uniform characteristics. Can be done.

まだ、実施例では自己整合型のゲート電極の構造につい
て述へたが、ソースおよびドレインのコンタクト部はゲ
ート電極を形成する前に公知の技術、たとえば、不純物
の熱拡散やイオン打込み方などを用いて形成し、その後
、ゲート絶縁膜、ゲート電極の順序で形成しても良い。
Although the structure of the self-aligned gate electrode has been described in the embodiment, the source and drain contact portions are formed using known techniques such as thermal diffusion of impurities and ion implantation before forming the gate electrode. After that, the gate insulating film and the gate electrode may be formed in this order.

なお、図中10は不純物拡散部、12は表示電極兼ソー
ス電極である。
In addition, in the figure, 10 is an impurity diffusion part, and 12 is a display electrode and a source electrode.

第3図は第1図に示した構造で薄膜トランジスタのチャ
ネル長りを短かくした構造を示す。第1図と第3図とを
比較してもわかるように、本発明の構造では、チャネル
長りの長さによらず開口率が一定とな如、特に、チャネ
ル長りが長い場合にのパターン及びコンタクト孔5のパ
ターンを変更するだけで、他のパターンは同一のパター
ンを使数を削減することができる。
FIG. 3 shows a structure in which the channel length of the thin film transistor is shortened in the structure shown in FIG. 1. As can be seen by comparing FIG. 1 and FIG. 3, in the structure of the present invention, the aperture ratio is constant regardless of the length of the channel, especially when the channel length is long. By simply changing the pattern and the pattern of the contact holes 5, the number of other patterns that are the same can be reduced.

〔発明の効果〕〔Effect of the invention〕

本発明によれば、薄膜トランジスタを配線電極部に形成
し、表示電極面積の占める割合を大きくすることができ
るので、表示特性の良好なアクティブマトリクスディス
プレイが得られ、薄膜トランジスタのゲート電極は自己
整合型で形成できるので特性の揃った素子が得られる。
According to the present invention, since the thin film transistor is formed in the wiring electrode part and the proportion of the display electrode area can be increased, an active matrix display with good display characteristics can be obtained, and the gate electrode of the thin film transistor is self-aligned. Since it can be formed, an element with uniform characteristics can be obtained.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の平面構造図、第2図は製造工程を示す
第1図の■−■矢視断面図である。 1・・・半導体薄膜、2・・・信号配線兼ドレイン電極
、3・・・走査配線兼ゲート電極、4・・・表示電極兼
ソース電極、5・・・コンタクトホール。
FIG. 1 is a plan view of the structure of the present invention, and FIG. 2 is a sectional view taken along the line ■--■ in FIG. 1, showing the manufacturing process. DESCRIPTION OF SYMBOLS 1...Semiconductor thin film, 2...Signal wiring and drain electrode, 3...Scanning wiring and gate electrode, 4...Display electrode and source electrode, 5...Contact hole.

Claims (2)

【特許請求の範囲】[Claims] 1.複数の信号電極と、この信号電極に交叉する複数の
走査電極と、それぞれの交点に接続した薄膜トランジス
タとを絶縁性基板上に形成し、液晶等の電気光学効果を
もつ物質と積層したアクティブマトリクスディスプレイ
において、 前記信号電極と前記走査電極とを直線状に形成し、前記
薄膜トランジスタと表示電極との接続部を除いて、前記
薄膜トランジスタを前記信号電極及び前記走査電極に沿
つて形成したことを特徴とする薄膜トランジスタ。
1. An active matrix display in which multiple signal electrodes, multiple scanning electrodes that intersect with the signal electrodes, and thin film transistors connected to each intersection are formed on an insulating substrate, and are laminated with a material that has an electro-optical effect such as liquid crystal. The signal electrode and the scanning electrode are formed in a straight line, and the thin film transistor is formed along the signal electrode and the scanning electrode except for a connecting portion between the thin film transistor and the display electrode. Thin film transistor.
2.特許請求の範囲第1項において、 ソース電極とドレイン電極とをたがいに前記走査電極の
反対側に位置させたことを特徴とする薄膜トランジスタ
2. The thin film transistor according to claim 1, wherein a source electrode and a drain electrode are located on opposite sides of the scanning electrode.
JP59180597A 1984-08-31 1984-08-31 Thin film transistor Granted JPS6159474A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59180597A JPS6159474A (en) 1984-08-31 1984-08-31 Thin film transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59180597A JPS6159474A (en) 1984-08-31 1984-08-31 Thin film transistor

Publications (2)

Publication Number Publication Date
JPS6159474A true JPS6159474A (en) 1986-03-26
JPH0564357B2 JPH0564357B2 (en) 1993-09-14

Family

ID=16086041

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59180597A Granted JPS6159474A (en) 1984-08-31 1984-08-31 Thin film transistor

Country Status (1)

Country Link
JP (1) JPS6159474A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62280890A (en) * 1986-05-30 1987-12-05 松下電器産業株式会社 Active matrix array
JP2006323396A (en) * 1997-02-17 2006-11-30 Seiko Epson Corp Display apparatus
US7710364B2 (en) 1997-02-17 2010-05-04 Seiko Epson Corporation Display apparatus
US8188647B2 (en) 1997-02-17 2012-05-29 Seiko Epson Corporation Current-driven light-emitting display apparatus and method of producing the same

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62280890A (en) * 1986-05-30 1987-12-05 松下電器産業株式会社 Active matrix array
JP2006323396A (en) * 1997-02-17 2006-11-30 Seiko Epson Corp Display apparatus
US7710364B2 (en) 1997-02-17 2010-05-04 Seiko Epson Corporation Display apparatus
US7880696B2 (en) 1997-02-17 2011-02-01 Seiko Epson Corporation Display apparatus
US8154199B2 (en) 1997-02-17 2012-04-10 Seiko Epson Corporation Display apparatus
US8188647B2 (en) 1997-02-17 2012-05-29 Seiko Epson Corporation Current-driven light-emitting display apparatus and method of producing the same
US8247967B2 (en) 1997-02-17 2012-08-21 Seiko Epson Corporation Display apparatus
US8354978B2 (en) 1997-02-17 2013-01-15 Seiko Epson Corporation Display apparatus
US8362489B2 (en) 1997-02-17 2013-01-29 Seiko Epson Corporation Current-driven light-emitting display apparatus and method of producing the same

Also Published As

Publication number Publication date
JPH0564357B2 (en) 1993-09-14

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