JPS6158058A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To shorten an access time by accessing simultaneously plural memory cells at peripheral address having a prescribed relation with the address specified by an access command as a center. CONSTITUTION:A memory device is constituted of 1st-4th memory blocks 1-4, data bus selection circuit 6 and data bus 7. Receiving row address signals b6y a random access action, respective blocks 1-4 act in parallel, and the side of the data bus selection circuit 6 decides any one of them to be accessed. When the block 1-4 input and output data to the memory cell of a selective word line in parallel, memory cells at adjacent row addresses are accessed in paralllel.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory device, and particularly relates to not only data in a memory cell specified by an address signal, but also data in a memory cell specified by an address signal.
The present invention relates to a semiconductor memory device in which data of a plurality of mesori cells surrounding the memory cell in a two-dimensional direction can be simultaneously accessed.

The semiconductor memory device according to the present invention is suitably used for multidimensional gutter processing such as image protection data processing.

[Conventional technology]

For example, in image processing, an image memory is used to store image data, and this image memory often stores image data corresponding to an image displayed on a graphic display or the like. The image data stored in such an image memory is subjected to (1) compression, (2) taking a difference, (3) smoothing, and other data processing between data stored in adjacent addresses. It often happens. In order to perform such data processing, it is necessary to read and process data not only in the target memory cell but also in the peripheral memory cells. Therefore, in such an image memory, etc., it is required to be able to quickly access not only the target memory cell but also the peripheral memory cells.

Furthermore, such requirements are not limited to access for each memory cell, but also for each word in matrix calculations and three-dimensional data processing. This will improve processing efficiency.

There are semiconductor memory devices that have already been proposed by the present inventors as devices that meet these requirements (for example, the
No. 8-53568). Regarding such a semiconductor device, the second
This will be described below with reference to the figures.

The semiconductor memory device shown in FIG. 2 has a word line 'vVLO'
, WLI, WL2, . . . and data line BLO.

BLI, BL2, . . . and memory cells h (
COO, M CO1, M CO2,..., MCl0゜MCII, MCI2... and three data buses DB-
1゜DBO, DB+1 and column decoders CDO, CDI
.

CD2,... and transfer dart transistor QOOIQO11QO21Q1G1Q111Q12
Equipped with +゛° fathom. Transistor Qoo + Qo
t r QO2 is connected between the data line BLO and the data buses DB-1, DBO, DB+1, and the transistors Qto * Qt r O12 are connected between the data BiBL1 and the data bus DI3-1 DBO, respectively.
, DB+1, and other transistors are similarly connected between each data line and each data bus. The output of each column decoder is the data line and the data bus DB which are connected between one data line and the data bus DBO.
-1 and DB+1 of each transistor. For example, column decoder C
DI is connected between the data line BLO and the dirt of the transistor Qll connected between the data line BLI and the data bus DBO.
The data line BL2 and the data bus DB+1 are connected between the data line BL2 and the data bus DB+1.
It is commonly connected to the dart of the transistor Qzz connected between. In addition, in Figure 2, the data line is 1
A line connecting each memory cell and each transfer gate transistor arranged in one column is called 9. For example, the data line BLO is connected to the memory cells MC0O, M
C0I , MCO2・= and transistor Qoo r
It connects Qot + QO2.

In the memory device shown in FIG. 2, for example, when the word line WLI is selected and this potential is set to a high level, the word @W
Memory cell MC0I connected to LI.

The data of MCI 1 , MC21, MC31, . . . correspond to data lines BLO, BLl, BL2, respectively.
゜BL3. It will be forwarded to... For example, if the memory cell MCII is a memory cell for address specification, by outputting a column selection signal from the column decoder CDI) the transistor Qll and the transistor Qoo
and Qzz is turned on. In this case, data from memory cell MCII is outputted via data line BLI, transistor Qll, and data bus DBO, and memory cells MC0I and MC21 on both sides of memory cell MCII are outputted via data lines BLO and BL2, respectively.
l-lansostar Qoo and O22,database,',D
It is output via B-1 and DB+1. Therefore, by specifying the address of the center memory cell MCII and accessing the memory cell MCII, the memory cells MCII adjacent to both sides of the memory cell MCII can be accessed at the same time.
It also becomes possible to read data from the MC21.

[Problem that the invention seeks to solve]

However, in the semiconductor memory device described above, only data in the momentary contact column of the same word line can be read. Art studio 3! I! etc., it is often necessary to have data that spreads two-dimensionally at the same time. For example, a 3×3 multi-region (MCOO, MCl0.M
C20), (MCOI.

MC11, MC21), (MCO2, MC12, M
When data of C22) is required simultaneously, in the semiconductor memory device described above, selection of word line WLO, selection of column decoder CDI, selection of WLI and selection of CDI, selection of WL2 and selection of CDI are required. Thus, the same selection operation must be repeated three times, leaving complexity in the memory access operation and not reducing the access time sufficiently. An object of the present invention is to enable data from adjacent memory cells connected to adjacent word lines to be simultaneously output or input in parallel to a memory cell to be accessed.

[Means to solve the problem]

In the present invention, a plurality of memory blocks each having a plurality of memory cells, a plurality of word lines and a plurality of word lines for accessing any one of the plurality of memory cells, and each of the memory blocks operates in parallel for a specific row address, and by selecting input/output data of the memory block corresponding to the specific row address, random access to the word line corresponding to the specific row address is performed. In addition, an operation mode is possible in which word lines belonging to a memory block different from the word line and having a predetermined address positional relationship are simultaneously accessed in parallel. A semiconductor memory device characterized in that the block is provided with means for selecting a word line different from a word line corresponding to a row address for random success so that the predetermined address positional relationship is maintained. is provided.

[Effect]

In the present invention, any one of a plurality of memory cells divided into a plurality of memory blocks is selected in response to an address signal for random access, and is adjacent to the word line of the accessed memory cell. The contents of the 'MI' number of memory cells connected to the word line are simultaneously output to the data bus, and are arranged in a predetermined positional relationship within a plurality of memory blocks in response to one access signal. A word line is selected. This makes it possible to access '& number of memory cells in a plurality of memory blocks in response to one access signal.

〔Example〕

Embodiments of the invention will be described below with reference to the accompanying drawings.

FIG. 1 shows a configuration diagram of a semiconductor memory device as an embodiment of the present invention. The storage device shown in FIG. 1 is composed of first to fourth memory blocks 1 to 4, a data bus selection circuit 6, and a data bus 7.

The first memory block 1il'i, as shown in detail in FIG. IB LO to BL 4 and word line WLO.

WL4. Memory cell MC0O connected between WL8
~MC40, MCO4~MC44, MCO8~MC4
8, a data line selection circuit 12 in which transistors Qoo to Q42 as transformers 7 are connected as shown in FIG. 3, a word line decoder 13 and its addition circuit 14. There is. The second to fourth memory blocks 2 to 3 are similarly configured.

However, the second and third memory blocks 2 and 3 are provided with an adder circuit 14, while the fourth memory block 4 is provided with a subtracter circuit 44 instead of the adder circuit 14. Further, column decoders 51 and 52 are connected to first and second memory blocks 1 and 2 and third and fourth memory blocks 3 and 4, respectively. 1st to 4th
Data line selection circuits 12 and 22 for memory blocks 1 to 4
32.42 are connected to the data bus selection circuit 6 via data buses 71-74.

Here, each block 1 to 4 operates in parallel in response to row address signals A2 to A when looking only at random access operations, and the lowest two bits of row address signal Ag
+ AI determines which block is to be accessed on the data bus selection circuit 6 side. Therefore, when the row address signal A'O"Ag is counted up by 1 from O, the word line selected is WL6 *WL1+".
If WLH, word line C, first cell block 11
Now W.L.O.

WL4. WL8. ..., in the second cell block 21, WLI, WL5, WLO, ..., in the third cell block 31, WL2, WL6, WLIO, ...,
In the fourth cell block 41, WL3. WL7. WLII
If you look at the address order, there are 4 in each cell block.
adjacent ones, e.g. WLO and WLI
, WLI and WL2 belong to different cell blocks and are provided in adjacent cell blocks. Within each block, word lines designated by adjacent row addresses are selected and operated simultaneously.

Therefore, by inputting and outputting data to and from memory cells on a selected word line in parallel in each block, memory cells at adjacent row addresses can be accessed in parallel.

However, the center row address due to random access is
When a word line in either end blocks 1 or 4 is selected, the word line corresponding to the row address immediately before or after the selected row address becomes unselected. Even if each block is simply operated in parallel, word line data related to a specific address cannot be output in parallel depending on the row address.

Therefore, in the present invention, in a mode in which memory cells on adjacent word lines are simultaneously accessed, the word line selection order for both end blocks is made cyclic. This will be explained in detail later.

The embodiment shown in FIG. 1 shows a case where there are 256 memory cells, and a 9-bit address signal A is used on the low side to specify the address of the memory cells.

~A, (A, is LSD, Aa is MSD) are connected to decoder circuit 13.23.33.43. However, the decoder circuits 23 and 33 are connected to only the A2 to A8 bits, the decoder circuit 13 has the A'2 to As bits processed by the adder circuit 14 for the AO to A8 bits, and the decoder circuit 43 has the A'2 to As bits processed by the subtracter circuit 44. taAτ~A'6
Bit is applied. A6 to A4 bits and N to A
The meaning of the % bit will be explained later.

Furthermore, the 1 bit of Agh is applied to the data bus selection circuit 6, which will also be described later.

The operation of the storage device shown in FIG. 1 will be explained.

In block access mode, memory cell MC25
A case will be described in which a read command is issued by specifying an address. Block access mode means nXn for rows and columns around the addressed memory cell McCc, in this example 3X3=9.
This refers to the case where data in memory cells is accessed with a single access command.

When an address signal for addressing the memory cell MC25 is applied to the WL decoder 13, 23, 33, 43, the word line WL5 in the second cell block 21 to which MC25 is connected is selected, and the second The word 1lWL4 of the first cell block 11 has the same positional relationship as the word line WL5 of the cell blocks on both sides of the cell block 21.
The word line WL6 of the third cell block 31 is also selected at the same time. At this time, word 1ilWL7 of cell block 41 is also selected, although it is not directly related to reading.

That is, the WL decoders 13.23, 33.43 select the word line WL to which the addressed memory cell is connected.
x and at least the word line WLx- connected before and after it
j and WLx+1 are selected at the same time, but these word lines do not belong to the same cell block as described above.

Simultaneously with the selection of the word lines WL4, ``vVL5, and WL6, CD2 of the column decoders 51 and 52 becomes high level so that memory cells MC15 and MC35 on the left and right sides of the memory cell MC25 are simultaneously read out.Therefore, as shown in FIG. Regarding the cell block 11 shown in FIG.
Data of C14, MC24, MC34 is transferred to data bus 71
are output to DB-1, DBO, and DB+1, respectively.

Similarly for the cell block 21, the memory cell MC1
5, MC25, MC35, and the data of memory cells MC16°MC26, MC36 of cell block 31 are output to data buses 72, 73 consisting of DB-1°DBO and DB+1, respectively.

The data of the memory cells simultaneously outputted to the data buses 71 to 73 in this way is applied to the data bus selection circuit 6, but the address signal A (by the 1r A1 bit),
centered on MC25, lo-1-1: MC1, respectively
4, lo-10: MC241 lo-1+1: MC34
.

l0o-1: MC15, l0oo: MC25, IOo
+1: MC35° engineering 0+1-1: MC16, IO+1°: MC26, IO+1+,: MC36.

The data of the memory cell is outputted to terminals 10-1-1 to IO+1+1 corresponding to K.

In other words, data in 3×3 memory cells around the addressed memory cell MC25 is 1.
It is possible to issue a ``C'' for access at any time.

Next, the case where the addressed memory cell is MC24 will be described. In this case, IO low 1: MC14, IOg O: MC24, 10 as above with MC24 as the center.
0+1: MC34,'IO+1-1: MC15,I
O+10: MC25, lo-l-1-1-1: MC3
The obvious choice is 5°. However, M
When the same process as described above is performed for the fourth cell block 41 which is cyclically connected to the column immediately before C24, word line WL4. MC17°MC27, MC37 of word @WL7 which is in the same positional relationship as WL5 will be selected, and the above relationship will not be maintained, which is different from the case where MC25 is the center. - In this case, MC13, MC23 and MC33 of the fourth cell block 41 should be selected, and these are the ones selected by WL3 immediately before word 5wL7. Therefore, in such a case, that is, when the A (1 + AH bits of the address signal are both low and the central memory cell corresponding to the specific address signal for random access is the first cell block), the subtraction circuit 44 The address signal A% to h% with 1 subtracted is applied to the WL decoder 43 to select the previous word line.Thereby, ICLl-1: MC13, IO-, , :MC23, lo
-1-1-1: MC33 is output.

On the other hand, when the center cell is MC20, the last word line WL127 of the cell block 41 is selected as the word line immediately before WL3 in the fourth cell block 41.

Furthermore, the case where the addressed memory cell is in the fourth cell block 41 will be described.

For example, if memory cell MC27 is specified as the center, lo-1-1: MC16, lo-10: MC26, IO
1+1 2 MC36IO (1-1: MC17, l0o
o: MC27, 100+1: MC37 is selected as described above. However, for the next subsequent row, MCI 4 , MC24 , MC24 of the word line WL4 of the first cell block 11, contrary to the above case,
MC34 will be selected. Therefore, when the address signal AOr A1 bits are both high and the center memory cell is the fourth cell block, the adder circuit 14 adds 1 to the address signals A'2 to A'8 to the WL decoder 13. and selects the next word line. According to this, lo-4-1-1: MC18, IO+1 g: MC2
8, IO+1+1: MC38 is output.

In this way, the addition circuit 14 and the subtraction circuit 44 ensure continuity of the memory cells.

This continuity also applies to the data gland.

For example, if MCO4 is specified as the center cell,
From the first cell block 11, as shown in FIG. 3, the last cell MC of the word line WL4 is
44, MCO4° as the center, MC as the next cell
14 are each DB-1.

It is output to DBO and DB+1. Conversely, when MC44 is selected, MC34, MC44, and MCO4 are output.

FIG. 4 shows another embodiment. The embodiment illustrated in FIG.
A modification of the decoders 13 and 43, the addition circuit 14, and the subtraction circuit 44 of FIG. 1 is shown.

Other parts are the same as in FIG. An actual example of the increment signal generation circuit 15 and decoder 13a shown in FIG. 4 is shown in FIG.
3a is shown in FIG. 6. In FIG. 4, the increment signal generation circuit 15 is
Consisting of an NDr-to 151 and an inverter 152,
When the addressed memory cell is in the fourth cell block, AO"H+AI"H, so the increment signal IC8=H.

Generates a signal of IC3=L. On the other hand, the decoder 13& is NOR) 131, 134, 138. AND dirt 1
32.135,136,137,139,140,OR
133, 137, and 141 are connected as shown in the figure. Therefore, for example, pNO
When the output of R dart 131 is high, A(1=H,
If AI=H, IC8=H and IC8=I, so the output of ANII"-to 135 becomes high and the word line WL4 connected to OR gate 137 becomes high level. On the other hand, if A6 + AI is other than the above If IC3=
Since IC3=H, the word line WLO whose output from the HD gate 132 is high is selected. In this way, it has the same functions as the adder circuit 14 and decoder 13 in FIG.

The decrement signal generating circuit 45 in FIG. 6 is composed of a NOR gate 451 and an inverter 452), and the address specification is the first cell block, that is, A 6 =L tAt =
In case of L, increment signal DC8=H, DC3=L
becomes. The decoder circuit 43a is NOR (NOR) 431°4
35.439, AND? '-1432,433,43
6゜437.440.441, OR goo) 434,
438°442 are constructed as shown. It is clear that the operation of this circuit is opposite to that of the circuit of FIG.

In the above embodiments, block access to a 3×3 array has been described, but the same can be done to any arbitrary array, mXn. For example, in the case of a 5x57 ray Glock access, the cell block may be e.g.
3=8 pieces. Although it is possible to use four cell locks as in the above embodiment, the relationship between the word lines is complicated.
'';-da circuit becomes complicated.On the other hand, it is not economical to use more than 24 cell blocks.By using 8 cell blocks, the adder circuit includes the WL decoder K of the first and second cell blocks,
Subtraction circuits are provided corresponding to the WL decoders of the seventh and eighth cell blocks. On the other hand, five transfer transistors of the data bus driven by column f code 1''K are also driven at the same time, and the data bus DB-2゜DB-1, DB O, DB+1 is transferred via five consecutive data lines.
, output data to DB +2.

Also, as in the above embodiment, I1 is always applied to the center cell.
It is not necessary to perform block access for two adjacent memory cells, and it is also possible to arrange them in a certain relationship, for example, so that every other memory cell is accessed.

Although the above embodiment has been described in the case of a read operation, it is also possible to write the data applied to the terminals lo-1-1 to IO+1+1 in one access.

In the above explanation, only the case of block access was described, but by providing a control circuit, it is possible to perform either access to only one cell as in the conventional case or block access as in the present invention by switching by command 9. It can be carried out.

Further, the present invention allows block access not only in units of 1 bit as described above but also in units of words.

〔Effect of the invention〕

As described above, according to the present invention, multiple memory cells at peripheral addresses having a predetermined relationship around an address specified by a single access command can be simultaneously accessed with a relatively simple circuit configuration. This makes it possible to shorten access time.

[Brief explanation of drawings]

FIG. 1 shows a semiconductor device (()) as an embodiment of the present invention.
R factor, Figure 2 is a configuration diagram of a conventional semiconductor memory device, Figure 3
The figures are a detailed circuit diagram of the storage device shown in FIG. 1, FIG. 4 is a configuration diagram of a semiconductor storage device as another embodiment of the present invention, and FIGS. 5 and 6 are partial circuits of the storage device shown in FIG. 4. Figure. (Explanation of symbols) 1 to 4...Memory block, 11, 21, 31.41
... Cell block, 12, 22, 32.42 ...
Data storage selection circuit, 13, 23, 33, 43... Word line decoder, 14... Addition circuit, 44... Subtraction circuit, 6... Data bus selection circuit, 7... Data bus.

Claims (1)

[Claims] 1. A plurality of memory blocks each having a plurality of memory cells, a plurality of word lines for accessing any one of the plurality of memory cells, and a plurality of word lines;
Each of the memory blocks operates in parallel for a specific row address, and by selecting input/output data of the memory block corresponding to the specific row address, random access to the word line corresponding to the specific row address is performed. In addition, an operation mode is possible in which word lines belonging to a memory block different from the word line and having a predetermined address positional relationship are simultaneously accessed in parallel. In the memory block of
A semiconductor memory device, further comprising means for selecting a word line different from a word line corresponding to a row address for random access so that the predetermined address positional relationship is maintained. 2. The means includes one of the plurality of memory blocks.
row address adding means attached to a word decoder circuit included in the memory block, and another one of the plurality of memory blocks.
and row address subtraction means attached to a word decoder circuit included in the memory block, and when a word line in a memory block to which one belongs is randomly accessed, the addition means and the subtraction means correspond to the random access row address in the other memory block. 2. The semiconductor memory device according to claim 1, wherein a word line corresponding to a row address added or subtracted by a predetermined value is selected.