JPS6158033A - Disc controller - Google Patents

Abstract

PURPOSE:To detect and process an error at data write in a disc controller in a short time without relieving the load from software by using an operation processor to read write data of a disc storage device and collating the data with the write data from the processor stored in a memory. CONSTITUTION:The processor 2 receives a command parameter in a prescribed area of a 2-port memory 401 in a disc controller 4a, generaes an interruption signal to an operation processor 42a, which analyzes it and obtains a non-use block buffer, the information is set to a block selection register 402 and the data of a common memory 3 is fetched into a memory 401. Further, the device 42a writers the data in the memory 401 to a disc device 5, sets status informa tion to the memory 401, informs the end to the device 2, reads the data of the memory 5, compares it with the data of the memory 401, and when they are dissident, the succeeding use is inhibited, other record is assigned, the data in the memory 401 is written to release it.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a disk control device using a microprocessor.

[Conventional technology]

A typical example of this type of conventional magnetic disk control device (hereinafter referred to as disk control device) is shown in block configuration in FIG. Here, with reference to FIG. 5, a case will be described in which a processing unit (CPU) 2 accesses a magnetic disk storage device (hereinafter referred to as a disk device) 5. First, the CPU 2 sets a so-called high-level command as logical access information on the command register 46 via the common bus 1 and the bus interface 44. When a command is set in the command register 46, the arithmetic processing unit (microprocessor) 42 learns that the command has been set by an interrupt or the like, reads the contents of the command register 46, analyzes the command, and executes the command. Depending on the content, activation of the DMA controller 49 and sending of so-called low-level commands as physical access information to the disk interface 48 are carried out. When such processing is completed, the microprocessor 42 sets predetermined status information in the status register 47 and notifies the CPU 2 that the processing has been completed by means of an interrupt or the like. Therefore, the CPU 2 reads the status register 47 via the bus interface 44, determines whether the process has ended normally or abnormally based on the status information, and ends the series of processes.

[Problem that the invention seeks to solve]

The first problem with such a conventional configuration occurs when data is written to the disk device 5. In other words, if we consider the case where data held in the buffer memory (FiFo) 45 is written to the disk 85 via the internal bus 41 and the disk interface 48, whether or not the data was written normally depends on the This becomes clear only when the data is read. However, in this case, when it is determined that the data has not been written normally, it is impossible to continue normal processing because there is no normal data.

As a method for solving this problem, when the CPU 2 writes data to the disk device 5, it may be possible to immediately read and check the data written to the disk device 5. However, this requires a negative amount of time for the software of the CPU 2, and at the same time, it takes time to process the write operation to the disk device 5.

The second problem is ECC error correction processing.

When writing data to the disk device 5, an ECC pattern is usually also written at the end of the data section. Then, if that data is read and a correctable ECC error is found, the data to be corrected is in a buffer memory under the control of the CPU, and the microprocessor 42
Since the correction cannot be executed, the CPU 2 must receive a notification to that effect and correct the data;
The disadvantage is that it places a burden on the software in step 2.

[Purpose of the invention]

Therefore, the main object of the present invention is to detect errors that occur when writing data to a disk device within a disk controller without placing a burden on software or increasing processing time. , the purpose is to improve the reliability of the processing.

Another object of the present invention is to allocate a replacement record to a defective record when a correctable ECC error occurs when reading data from a disk device, thereby reducing the burden on software and speeding up the processing. The object of the present invention is to provide a disk control device that can process data without dropping it.

[Means for solving problems]

In order to achieve such an object, the present invention includes an arithmetic processing unit, a memory, and a disk interface between the processing device and the disk storage device, and the memory is accessed by the processing device and the arithmetic processing device. Then, the write data transferred from the processing device is stored, and the arithmetic processing device reads the write data transferred and stored in the disk storage device and compares it with the write data stored in the memory. The write data stored in the storage device is checked. Specifically, the data buffer between the CPU and the magnetic disk drive is configured with a two-boat memory consisting of a plurality of blocks, each block of which is the same size as a record. By knowing which blocks are being used by the microprocessor built into the CPU, data read from the CPU side can be written to blocks that are not being used.

[Effect]

Due to the above configuration, even after data is written to the disk device, the written data is retained in memory, especially data written to a block of 2-board memory. It becomes possible to provide a block and an empty block. Therefore, when the microprocessor in the disk control device is in an idle state, it is possible to check the data by sequentially outputting write data from the disk device and comparing the write data on the 2-port memory. . As a result, it becomes possible to detect errors during writing and to fluidly allocate alternative records.

〔Example〕

FIG. 1 shows one preferred embodiment of the present invention, and the operation of writing data to a disk device will now be described in correspondence with the description of the prior art described above. In addition, in FIG. 1, the same reference numerals are given to the same components as those in FIG. 5, and those that include partial changes are as follows.
The subscript a is added.

First, before transmitting a command to the disk control device 4a, the CPU 2 sends command parameters such as the record address of the disk device 5, the memory address where the data of the common memory 3 is stored, and the number of records to be transferred to the disk control bag Wfj. -2 port memory 40 with 4rx
After that, the command is set in the command register area on the two-port memory 401.

When a command is set in the command register area, an interrupt signal is sent to the microprocessor 42a. Therefore, microprocessor 42a learns that a command has been set by receiving the interrupt signal and analyzes the command and command parameters.

As a result, the microprocessor 42a sends a seek command to the disk interface 48, searches for an unused buffer block from a table showing the usage status of buffer blocks in the memory 43, and stores the information in the block selection register 402. and set
Data from the designated address of the common memory 3 is taken into the designated buffer block of the 2-port memory 401 via the bus interface 44. Furthermore, when the seek operation is completed, the DMA controller 49 is activated, a data write command to the disk device 5 is sent to the disk interface 48, and the data in the buffer block in the 2-port memory 401 is transferred to the disk device 5. dented. At this time, simultaneously with the data transfer from the 2-port memory 401 to the disk device 5, the 2-port memory 401 is also used in a time-sharing manner for data transfer from the common bus 1 to another vacant buffer block in the 2-port memory 401. This is done simultaneously. Further, here, even when writing is completed, the buffer block in the 2-port memory 401 is not released, and the written data is held as is. When writing of the designated number of records is completed in this manner, the microprocessor 42a sets status information in the status area on the 2-port memory 401, and sends an interrupt signal to the CPU 2 to notify the CPU 2 of the end of the process. In response to receiving this interrupt, the CPU 2 reads the status information on the 2-port memory 401, checks the processing status, and ends the write operation to the disk device 5.

Thereafter, when the microprocessor 42a enters the idle state, it reads the data previously written to the disk device 5 and compares it with the corresponding written data on the two-port memory 401. If the comparison results match, the corresponding area in the table showing the usage status of buffer blocks in the memory 43 is rewritten to an unused status, and the 8 corresponding buffer blocks in the 2-port memory 401 are transferred. release. If the comparison data does not match and an error occurs, the record that has been dented in the disk device 5 is regarded as a defective record, and its future use is prohibited, and another normal record is allocated. The data on the 2-port memory 401 is written there, and then the buffer block of the 2-port memory 401 is released. In the above operation, the number of records transferred at one time must be less than the number of buffer blocks in the two-port memory 401.

Next, the operation of reading data from the disk device 5 will be explained. First, the CPU 2, as in the case of writing,
Command parameters and commands are set in the command register area of the 2-board memory 401 in the disk controller 4a. Microprocessor 42a reads the command in its command register area through an interrupt and parses it. Furthermore, after analyzing the command, the microprocessor 42a sends a seek command and a record read command to the disk interface 48, and also activates the DMA controller 49 to read the read data from the disk device 5 into the 2-board memory 401. data into one of the two buffer blocks. After the data corresponding to the code is successively fetched into the buffer block, if there is no ECC error, the bus interface 44 is activated and the data is transferred to the designated area of the common memory 3. Simultaneously with this data transfer, the next record is taken into the other area of the reading buffer block using the block of the two-port memory 401 as a time division. Then, if there is no error, data transfer to the common memory 3 is started. In this manner, in the successive output operation, two buffer blocks in the two-vote memory 401 are used alternately to prevent a decrease in processing speed.

If an ECC error is found after one record worth of data has been loaded into the buffer block, the microprocessor 42a accesses the 2-board memory 401, corrects the error location, and after correcting the data, transfers the data to the common memory. Start data transfer to 3. When data transfer for the designated number of records is completed, the microprocessor 42a sets status information in the status area of the 2-port memory 401 and sends an interrupt signal to the CPU 2. In response to this interrupt signal, the CPU 2 reads the status information of the two-board memory 401, learns the result of the data transfer, and ends the process.

Next, referring mainly to FIGS. 2 and 3, the process by which the microprocessor 42a manages the buffer blocks of the 2-port memory 401 will be specifically described. Second
The figure shows a 2-port memory 401 and a roux code (1
Buffer "0" 401a, buffer "1" 40 lb, buffer "2" 401c, . . . buffer "N-2" 401-
z, buffer "N-1" 401-+, buffer "N" 4
01n, command area 401x and status area 40
An example is shown in which the pants are divided into one piece as 1y, and FIG. 3 shows 3 bytes of information contained in the memory 43 necessary to manage the buffer. The initial values of these 3-byte control information 431, 432, and 433 are all O. Here, the control information 431 is used as a flag, the control information 432 indicates the buffer number to be used next, and the control information 433 indicates the buffer number to be checked next.
Indicates O.

If the microprocessor 42a receives a command and the result of its analysis is, for example, a write command to the disk device 5, the microprocessor 42.
First, a checks the flag (data) of the first byte of control information 431 in FIG. Here, for convenience of explanation, flag data "XOI" corresponds to 1 buffer in use, and "XOO" corresponds to "buffer not in use."Thus, if the flag is "Xoo", then the flag data "XOI" corresponds to "1 buffer in use". , and the microprocessor 42a sets the data of the second byte of control information 432 in FIG. 3 in the block selection register 402.

As a result, if the data value of the second byte is 0, for example, buffer 0 shown in FIG. 2 will be accessed from the bus interface 44. When the transfer to buffer 0 is completed, data 432 is incremented by 1 in the second byte of control information in FIG. As a result, from the lotus interface 44, the buffer 1 in FIG.
The transfer will take place. At this time, the data in buffer 0 in FIG.

If the above operation is repeated and the data transfer for the specified record is completed, as mentioned above, the data from buffer O will be retained as is, so these data will be transferred sequentially from O to the disk device 5. Check with the above data. In this case, each time the verification for one buffer is completed, the data of the control information 433 in the third hide in FIG. By the way, the process is ended and all three data of 3 bytes shown in FIG. 3 are cleared to O.

By the way, among the buffers shown in FIG. 2, buffers O through N-2 are used as buffers for recessing, and buffers N-1 and N-1 are used as buffers for reading. To manage the read buffer lN-1+N, it is sufficient to have flags corresponding to the two buffers indicating whether or not they are in use.

FIG. 4 shows a preferred embodiment of a two-port memory 401 that can be used in the present invention. 2 here
The port memory 401 has address buffers 411.41
2, a memory control section 413, a RAM 414, and data buffers 415 and 416. R.A.
M414 is a normal RAM used in time division according to a control signal from the memory control unit 413. The memory control unit 413 receives control signals 428 (address decode signal, memory read signal, memory write signal, etc.) from the bus interface 44 and control signals (RAM chip select, memory read, memory write signals, etc.) from the internal bus 41. etc.) 427, performs priority control, outputs control signals 4.29, 430.431, and uses the memory in a time-sharing manner.

A control signal 429 from the memory control unit 413 selects the output of the address buffer 411 or 412 as the memory address signal 423.

The control signal 430 selects either the data buffer 415 or 416 and also specifies the data transfer direction. The control signal 431 is a control signal for chip select, memory write strobe, etc. for the memory 414.

The output 420 of the buffer selection register 402 becomes the base address for the address signal 421 from the bus interface 44 and modifies which buffer is selected if the memory 414 is partitioned as shown in FIG. In a relationship. Further, the address signal 421 from the bus interface 44 is a relative address within the buffer. Therefore, CPU2. That is, from the perspective of the bus interface 44, the buffer is treated as one buffer that is accessed using this relative address,
I can only see one. Therefore, there is no effect on access on the CPUZ side. When accessing the command area and status area of the memory 414 from the bus interface 44, the output 420 of the block selection register 402 is naturally invalidated, and the command area 401X or status area 401y is accessed, respectively.

As described above, the embodiment uses a two-board memory, but this may be any memory that can be accessed by the CPU side and the microprocessor side.

Further, the write data stored in the disk device only needs to be stored in this memory until it is verified.

In the embodiments, a magnetic disk control device is mainly explained as a disk device, but this is not limited to magnetic disks, and may be a disk control device for optical disks, etc. Alternatively, data may be transferred in units of integral multiples thereof.

Furthermore, in this case, each block of memory that stores write data is a block corresponding to a sector as a record unit, but it is of course possible to allocate and use the storage capacity of a record unit or an integral multiple thereof as one block. .

〔Effect of the invention〕

An arithmetic processing unit, a memory, and a disk interface are provided between the processing unit and the disk storage device, and the memory includes:
Write data accessed and transferred from the processing device and the processing device is stored, and the processing device reads out the occupied data transferred and stored in the disk storage device and stores it in the memory. Since the written data stored in the disk storage device is checked against the written data stored in the disk storage device, the data can be retained even after the data is transferred to the disk device, and the data written to the disk device can be checked. can. As a result, errors can be detected early at the time of writing, and countermeasures can be taken, for example, by processing a replacement record for a defective record to ensure correct storage within the disk controller, without increasing the burden on the software. , the reliability of the system can be increased.

Furthermore, when a 2-boat memory is used, it is possible to provide two buffer blocks in the 2-boat memory and configure the blocks to be used alternately, so that when reading data from a disk device, When an ECC error occurs, the microprocessor within the disk controller accesses the two-port memory and can correct the error. Therefore, it is possible to correct ECC errors within the disk control device without reducing the processing speed or placing a burden on the software.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a preferred embodiment of a disk control device according to the present invention, FIG. 2 is a configuration diagram of a two-boat memory used in the embodiment of FIG. 1, and FIG. 3 is a usage state of buffer blocks. FIG. 4 is a block diagram of the second 2-boat memory, and FIG.
The figure is a block diagram of a conventional disk control device. 1... Common bus 2... CPU3... Common memory 4... Disk control device 5... Disk unit W 41... Internal bus 42... Microprocessor 43... Common memory 44. ... Bus interface 45 ... Buffer memory 46 ... Command register 47 ... Status register 48 ... Disk interface 49 ... DMA controller 401 ... 2 boat memory 402 ... Block selection register Patent application Fuji Electric Manufacturing Co., Ltd. Same as above Fuji Facom Control Co., Ltd. Patent attorney Agent Tetsuya Mori Patent attorney Agent B Yoshiaki Patent attorney Agent Masashi Shimizu Patent attorney Agent Nobu Kajiyama Figure 1 Figure 2 fart

Claims (4)

[Claims] (1) Provided between the processing device and the disk storage device,
The device includes an arithmetic processing device, a memory, and a disk interface, the memory being accessed by the processing device and the arithmetic processing device, storing write data transferred from the processing device, and the memory being accessed by the processing device and the arithmetic processing device, and storing write data transferred from the processing device. teeth,
The write data transferred to and stored in the disk storage device is read out and compared with the write data stored in the memory to check the write data stored in the disk storage device. disk controller. (2) The arithmetic processing unit reads the write data transferred and stored in the disk storage device during its idle time, compares it with the write data stored in the memory, and reads the write data stored in the disk storage device. 2. The disk control device according to claim 1, wherein the disk control device checks data. (3) The memory is a 2-port memory that has multiple blocks each having a storage capacity of each record of the disk storage device or an integral multiple thereof, and the arithmetic processing unit manages the usage status of each block, and the processing unit manages the usage status of each block and 3. The disk control device according to claim 1, wherein the write data is written to an unused block. (4) The disk control device according to claim 3, characterized in that for records with errors as a result of the check, the corresponding data stored in the memory is stored in another record of the disk storage device.