JPS6146524A - Pseudo random number generating device - Google Patents

Abstract

PURPOSE:To generate a pseudo random number whose uniformity having reproducibility is verified sufficiently at a high speed by providing a random number generation instruction which generates a pseudo random number using an (m) sequence and executing it through hardware. CONSTITUTION:The random number generation instruction consists of an operand code OP, general register specifying field GR, and address syllable AS. The lower 64 bits of an initial value Y0 (128 bits) read out of a memory 1 are shifted by one bit to right to obtain Y1, which is ORed exclusively with the lower 63 bits of Y0 by ALU9 to obtain Y2, which is registered as a generated random value in a general register having a number specified by the GR field of an instruction word. Bits 1-64 of the Y2 and Y0 are concatenated to obtain 16-byte data, which is stored in an address X to finish the execution of the instruction. The high-order bits 1-31 (stored in general register) of the random number value Y2 generated as mentioned above are used a fixed-point number.

Description

Detailed Description of the Invention Technical Field The present invention relates to a pseudorandom number generator, and in particular to a maximum length sequence (m This invention relates to a binary pseudorandom number generator using a binary number sequence.

BACKGROUND OF THE INVENTION Arithmetic random numbers are used to supply a large amount of random numbers required when performing simulations such as large-scale Monte Carlo experiments using conventional electronic computers.

Conventionally, an n-stage ring counter capable of assuming 2n possible states has been known as a hardware means for generating random integers within the range of 0 to 2n (n is an integer of 2 or more). However, the pseudo-random numbers obtained by the ring counter have a short period and are not uniformly distributed, making it difficult to regard them as uniform random numbers, making them unsuitable for precise simulations.

As a software means, one that has been used for a long time is random number generation using the congruence method, and by appropriately setting a natural number 819% integer and giving a non-negative initial value (integer) 2iQ, the recurrence formula % formula % ( 1) "Random number sequences" Z6, ZI, ic41, etc. are created by the following.

However, the number sequence generated by the congruence method has periodicity, and the period must be less than or equal to p, and p is the maximum number that can be expressed by the computer used, plus 1, and is determined by the number of digits of the computer used. You will be subject to restrictions. Also, since the same number never appears in one cycle of the sequence, when creating a multidimensional distribution, ("0, r, +, "', z
n-1) + (xn ”n+1゜..., ro.

-1), ... are located at at most two of the pn lattice points in the n-dimensional (hyper)cube, and the distribution of these points in the n-dimensional space is not random. It has a regularity that it lies on a hyperplane of less than (n, /p)/n sheets, so it is inappropriate when the random numbers generated by the congruence method create a multidimensional distribution. There were many.

In addition, as a software means, the maximum periodic sequence (hereinafter m
There is a method of generating uniform random numbers using a random number sequence. To briefly describe the random number generation method using m-sequences, constants c, , c2 . ...+Cpl are both 0 and still 1
Assuming that cp=l, consider a sequence (al) consisting of 0 and 1 produced by the recurrence formula %). However, the initial value aOr al + for + ap, 1
shall be chosen so that all are not O. The value of al is permutation (air + ai 21 ”'l ai-p
), the number of different permutations is 2p-
1, it is clear that the period m of the sequence (al) does not exceed 2p-1. The condition for exactly m=211'' is that the characteristic polynomial %(22) is a primitive polynomial on the Galois field G F (2). Also, in this case, (al) is the maximum periodic sequence (maxi
mum-1angth 1inearly recur
It is called a ring sequence (m-sequence for short).

Now, Tausworth extracts t (≦p) successive numbers from the m sequence [al], arranges them, and arranges the t-bit 2
Hexadecimal lJ\number “k”’ (La(+r+I to 7, a(Fk+r+2
Create +, +t--- (2-3) on °-B6, series (
uk) as a uniform random number on the interval (0,1). Here, r is any non-negative integer and σ(
≧t) is the interval at which t bits are successively extracted from (al). If σ is chosen to be coprime to the period m of (a,), then the period of (uk) will also be m. In one period, 0 appears 2Pl-1 times and all other t-bit binary digits appear 2p-t times. Therefore, if pt does not decrease to /), it can be assumed that (uk) (at least in terms of frequency) follows an approximately uniform distribution. Furthermore, if the delay is less than or equal to (m-t)/σ, the autocorrelation of (uk) almost matches that of an ideal uniform random number, and if the dimension is less than or equal to p/σ, then the autocorrelation of (uk) is a multidimensional distribution. It was theoretically shown that the distribution is almost uniform.

In this way, Tausworth's method is very superior in the sense that the various properties of the number sequence obtained by it are known theoretically, but the time required to generate one random number is longer than that of the congruential method, for example. In comparison, Harukiya has long drawbacks.

So Lewis & Payne decided to use Tauswort.
he (I improved the D method and devised a method to generate random numbers in a short time. First, select the tricycle f (z) - zp + zq + 1 river... song (2, 4) as a primitive polynomial (p'>q).Therefore, (ai)
The recurrence formula that creates al = ai, + ai-Q (mod 2) song -- (2, 5). And from (ai) to (U
, ), uk=0. akak+r +・+
ak+ (t −+ ) r . . . song (2, 6). Here, kt≦p, and r is an integer coprime to the period m. The feature of this method is that the number taken from (ai) is
They are arranged vertically (column direction) rather than horizontally (row direction) as in 2 and 3), and the phase is shifted by r between adjacent columns.

Since a large number of primitive 3 polynomials are known, there is a large degree of freedom in selecting p and q. Of these, 2”-
Choosing one for which 1 is a prime number is advantageous because it eliminates the need to worry about choosing values of other parameters so that they are coprime to the period. The reason why this method generates random numbers quickly is as follows.

Since the operation of recurrence formula (2, 5) is addition without carry, it is the same as exclusive OR, and therefore (uk
) can be created using the relational expression % (27).

Purpose of the Invention The present invention provides a pseudorandom number generator capable of rapidly generating a pseudorandom number sequence with a high degree of uniformity in hardware without using physical phenomena that do not have reproducibility such as thermal noise. It is intended to.

Structure of the Invention The pseudo-random number generator according to the present invention has a primitive polynomial f (x
)=Zp+zq+1 A device for generating an n-bit binary pseudo-random number using an m-sequence of 1, the device comprising means for reading p bits from a main memory address specified by a command word;
means for temporarily holding the contents of this p bit as an initial value; a shifting means for shifting the contents of this p bit by p -q bits; and a means for temporarily holding the contents of this p bit as an initial value; an exclusive OR means that performs an exclusive OR bit by bit with the contents of consecutive m bits in Means for writing the contents of a total of p bits, including the contents of the upper pm bits and the lower pm bits, to the main memory address specified by the instruction word, and means for deriving n bits from the output of the exclusive OR means. The configuration includes the following.

More specifically, a feature of the present invention is that in an information processing device that generates pseudorandom numbers that are arithmetically reproducible by setting an initial state and using a random number generation algorithm, reads an initial value from a storage address, shifts this read initial value by a predetermined number of bits, creates a bit-wise exclusive OR from this read initial value and the shifted value,
A first predetermined number of digits is extracted from this value and stored in a software visible register specified by the instruction word, and a second predetermined number of digits is extracted from the generated exclusive OR value. The extracted value and the value extracted by extracting a third predetermined number of digits from the initial value are concatenated and stored in the main memory address to be used as the initial value for the next generation of random numbers.

Example Hereinafter, the present invention will be explained in detail using the drawings.

FIG. 1 shows the format of a random number generation instruction according to an embodiment of the present invention, where OP is an operation code and an operation code unique to the random number generation instruction is assigned. GR is a general-purpose register specification field, and specifies the GR (general-purpose register) in which the generated fixed-point random number is to be stored. AS is an address syllable, and by normal address expansion, an initial value of 16 bytes is read from the first byte indicated by AS, and the execution result is stored at the same address as an initial value for the next random number generation.

FIG. 2 is a block diagram of an embodiment of the present invention, in which 1 represents a memory, and 2 and 3 represent memory read registers. Reference numeral 4 denotes a software visible register, which is a register that can be specified as a target of operations by reading and writing from software, and is a register that is a target of computer instructions. This software visible register 4 is a base register (
It consists of a general register (GR), a general register (BR), and a scientific operation register (SR).

5 and 6 indicate the operand 1 selector and operand 2 selector, respectively, and 7 and 8 indicate the operand register and operand 2 register, respectively. An ALU (arithmetic logic unit) 9 and a chic 10 are provided which receive the contents of these registers 7 and 8, respectively.
Outputs from both ALUs 9 and shifter 10 serve as inputs to arithmetic result selector 11 and operand 1, 2 selectors 5 and 6, respectively.

The output from the selector 11 is stored in the operation result register 12, and this stored output is input to the memory 1 and the software visible register 4.

FIG. 3 is a schematic diagram showing changes in the contents of the memory before and after execution of the random number generation instruction due to the operation of the device shown in FIG. 2, and FIG. 4 shows the operational flow of the embodiment of the present invention. It is a diagram.

Below, p=127. The operation will be sequentially explained assuming q=1.

First, when the instruction word is read and it is recognized by decoding the OP code that it is a random number generation instruction, the A of the instruction word is
After S is expanded, the absolute address is converted and 16 consecutive bytes (12
8 bits) is read out. At this time, for example, the first 8 bytes (bits 0 to 63) are read from memory 1 and stored in memory read register 2, and the next 8 bytes (bits 64 to 127) are read from memory 1 and stored in memory read register 2. 3. Therefore, the contents of both registers 2 and 3 correspond to the value of Yo in FIG.

Then, the operand register 7 is cleared (0 is stored in this register 7), and the contents of the memory read register 3 are transferred to the operand 2 register 8 through the operand 2 selector 6. In the chic 10, which receives both registers 7 and 8 as input, a 63-bit shift is performed to the left, and the shift result is stored in the operation result register 12 through the operation result selector 11. The contents of the register 12 at this time become Yl in FIG. Note that 7(1) in FIG. 4 indicates 1 bit whose content is O.

Next, a shift of 65 bits to the left is performed by a shifter having the operand register 8 and operand 2 register 8 as inputs, and the shift result is stored in the operand register 8. Still, the operation result register 12 is transferred to the operand register 8, and the contents of both registers 7 and 8 are shifted to the right by 2 bits, and the result is stored in the operand 2 register 8. After that, both registers 7 and 8 are set in ALU9.
Exclusive OR operation is performed for each bit of Y2 in FIG.
is obtained and stored in the register 12.

From this register 12 to software visible register 4
The upper 32 bits of Y2 are stored in the general-purpose register (GR) of , and Y2 of the operation result register 12 is stored in the upper 8 bytes of memory 1 (0:64), and from the memory read register 2 to the operand database. Transfer from register 3 to register 8, respectively.

, t In this case, Yo moves to both operands 1 and 2 registers.

The contents of both registers 7 and 8 are shifted 1 bit to the left by the shifter 10, resulting in a Yo (1:64) register 12Ki. The contents of this register 12 are stored in the lower 8 bytes of memory 1.

The above operation can be summarized as shown in Figure 3,
The lower 64 bits of the initial value Yo (128 bits) read from the memory are shifted 1 bit to the right and set as y, and the lower 63 bits of Yo are exclusive ORed with Yl and this is set as Y2.
Let Y2 be the generated random value and GR of the instruction word.
Store in the general-purpose register with the number specified in the field. Y2 and Y. bits 1 to 64 are concatenated and stored as 16-byte data at address X, and instruction execution ends.

For example, high-order bits 1 to 31 (stored in a general-purpose register) of the random value Y2 generated this time are used as a fixed-point random number.

In this example, p = 127. of equation (2, 4). q
The primitive polynomial % formula % (31) with = 1 is used, and ai "" ai-127■at -126-----°
Pseudo-random numbers are generated by the recurrence formula = (3, 2). .

Effects of the Invention As described in the paper, according to the present invention, by providing a random number generation instruction for generating pseudo-random numbers using an m-sequence and executing this by software, a reproducible number can be obtained. Pseudo-random numbers whose properties have been fully verified can be generated faster than by software.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the format of the instruction word of the random number generation instruction according to the embodiment of the present invention, FIG. 2 is a block diagram of the embodiment of the present invention, and FIG. 3 is a diagram showing the memory before and after execution of the instruction according to the embodiment of the present invention. FIG. 4, which is a diagram showing changes in content and how random numbers are generated, is a flowchart of command operations according to an embodiment of the present invention. Explanation of symbols of main parts 1...Memory 2.3...Memory read register 4...Software visible register 7.8...Operand register 9...ALU 10...Shifter 12
... Arithmetic calculation register

Claims (1)

[Claims] Primitive polynomial f(x)=x^p+x^q+1 (p, q are p
n(0<
A device for generating a binary pseudo-random number of (n≦p) bits, which includes a means for reading p bits from a main memory address specified by a command word, and a means for temporarily reading out p bits using the contents of the p bits as an initial value. means for retaining the contents of the p bits as p-q;
Shifting means for bit shifting and m(
m≧n) bits and the contents of successive m bits among the retained p bits, exclusive OR means for bit by bit, and m bits of this exclusive OR result; means for writing the contents of a total of p bits into the main memory address specified by the instruction word, with the contents being the upper m bits and the contents of the upper p-m bits of the held p bits being the lower p-m bits; and means for deriving n bits from the output of the exclusive OR means.