JPS6144425B2 - - Google Patents
Info
- Publication number
- JPS6144425B2 JPS6144425B2 JP55038187A JP3818780A JPS6144425B2 JP S6144425 B2 JPS6144425 B2 JP S6144425B2 JP 55038187 A JP55038187 A JP 55038187A JP 3818780 A JP3818780 A JP 3818780A JP S6144425 B2 JPS6144425 B2 JP S6144425B2
- Authority
- JP
- Japan
- Prior art keywords
- transmission
- transmission control
- control station
- data
- station
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 230000005540 biological transmission Effects 0.000 claims description 105
- 230000005856 abnormality Effects 0.000 claims description 12
- 230000002159 abnormal effect Effects 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 3
- 230000006870 function Effects 0.000 description 3
- 230000004044 response Effects 0.000 description 2
- 238000001514 detection method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/42—Loop networks
- H04L12/437—Ring fault isolation or reconfiguration
Landscapes
- Small-Scale Networks (AREA)
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
Description
【発明の詳細な説明】
本発明は、複数の制御装置間相互のデータ伝送
を行うデータ伝送システムに於いて、各制御装置
が相互の伝送相手アドレスをハードウエア及実際
の物理的配置で定まる物理アドレスと、物理アド
レスとは無関係に制御装置のプログラムの都合上
定めた論理アドレスの両者をもつ事で、制御装置
の異常故障に対して、予備の制御装置が、バツク
アツプを行なうデータ伝送システムに関する。DETAILED DESCRIPTION OF THE INVENTION The present invention provides a data transmission system in which data is transmitted between a plurality of control devices. The present invention relates to a data transmission system in which a backup control device performs backup in case of an abnormal failure of the control device by having both an address and a logical address determined for the convenience of the control device program regardless of the physical address.
従来、例えば、第１図の様なループ状のデータ
伝送システムで構成された複数の制御装置PC1〜
PC4が、相互の伝送を行つている場合、PC1〜
PC4のプログラムは、各々接続している伝送制御
局（St1〜St4）の物理アドレスでデータの授受を
行なつていた。今、制御装置PC1が異常となり、
伝送システムから切離される様な場合、伝送シス
テムを用いて、他の制御装置PC4が、制御装置
PC1の機能を肩代りさせる場合、制御装置PC4へ
制御装置PC1と全く同一のプログラムを入れて伝
送を行うと、伝送相手の制御装置PC2，PC3のプ
ログラムでは、各々、元の制御装置PC1に対して
伝送を指定する為、制御装置PC2，PC3では、制
御装置PC4が制御装置PC1の肩代りを行つた事を
検出して、制御装置PC1から制御装置PC4へ、伝
送相手先アドレスを変更する必要があり、制御装
置のプログラム処理として複雑・膨大となつてい
た。 Conventionally, for example, a plurality of control devices PC 1 to 1 configured in a loop-shaped data transmission system as shown in FIG.
When PC 4 is performing mutual transmission, PC 1 ~
The program of PC 4 exchanged data using the physical addresses of the transmission control stations (St 1 to St 4 ) connected to each station. Now, control device PC 1 has become abnormal.
If the control device PC 4 is disconnected from the transmission system, the other control device PC 4 can be connected to the control device using the transmission system.
When taking over the functions of PC 1 , if you put exactly the same program as control device PC 1 into control device PC 4 and transmit it, the programs of control devices PC 2 and PC 3 , which are the transmission destinations, will each have the same program as the original. In order to specify transmission to the control device PC 1 , the control devices PC 2 and PC 3 detect that the control device PC 4 has taken over the role of the control device PC 1 , and send the data from the control device PC 1 to the control device. It was necessary to change the transmission destination address to PC 4 , making the program processing for the control device complicated and enormous.
本発明は、上記の事情に基きなされたもので、
複雑なプログラム処理を個々の制御装置PCでは
行なわないで、異常を起した制御装置が有するア
ドレスを予備の伝送制御局に割当て、異常を起し
た伝送制御局のバツクアツプを行なうデータ伝送
システムを提供することを目的とする。 The present invention was made based on the above circumstances, and
To provide a data transmission system that allocates an address owned by a control device in which an abnormality has occurred to a backup transmission control station and backs up the transmission control station in which an abnormality has occurred, without performing complicated program processing on each control device PC. The purpose is to
以下本発明の一実施例を図面を参照しながら説
明する。 An embodiment of the present invention will be described below with reference to the drawings.
制御装置間のデータ伝能を行う場合、データ伝
送に必要とする機能を伝送制御局にまとめてもた
せ、制御装置本来の機能と独立させ、伝送制御局
を経由して、複数の制御装置間相互のデータ授受
を行なわせるようにしている。この場合、相手の
制御装置と伝送制御局とは１：１の関係にあり、
従つて制御装置PCのプログラムは、相手の伝送
制御局を指定して伝送を行う事となる。 When transmitting data between control devices, the functions required for data transmission are provided in a transmission control station, independent of the control device's original functions, and multiple control devices can communicate with each other via the transmission control station. data exchange. In this case, there is a 1:1 relationship between the other party's control device and the transmission control station,
Therefore, the program of the control device PC specifies the other party's transmission control station and performs the transmission.
第２図は、本発明を構成する伝送制御局のブロ
ツク図である。 FIG. 2 is a block diagram of a transmission control station constituting the present invention.
Ｐは伝送制御に必要な論理判断を行なうプロセ
ツサである。RAM（Random Access
Memony）はこのプロセツサＰが論理判断するた
めのデータ等が格納されるメモリ、PROM
（Programable Read Onlg Memory）は伝送制御
プログラム格納用のメモリである。TMは伝送ラ
イン上のデータ（有意信号）の無を検出を一定時
間カウントし、伝送制御局あるいはこの伝送制御
局に接続される制御装置PCの異常を検出するタ
イマー回路である。ADRSスイツチSWにてアド
レスを設定するアドレス設定回路である。TRCV
は他の伝送制御局とデータの授受するための送受
信回路である。IFは伝送制御局に接続される制
御装置PCを接続するためのインターフエースで
ある。PCはこのインターフエースIFに接続され
他の伝送制御局とデータの授受を行なう制御装置
である。 P is a processor that makes logical decisions necessary for transmission control. RAM (Random Access
Memony) is a PROM memory that stores data, etc. for logical judgment by this processor P.
(Programmable Read Onlg Memory) is a memory for storing transmission control programs. TM is a timer circuit that counts the detection of no data (significant signal) on the transmission line for a certain period of time and detects an abnormality in the transmission control station or the control device PC connected to this transmission control station. This is an address setting circuit that sets the address using the ADRS switch SW. TRCV
is a transmitting/receiving circuit for exchanging data with other transmission control stations. IF is an interface for connecting the control device PC connected to the transmission control station. The PC is a control device that is connected to this interface IF and exchanges data with other transmission control stations.
このように構成された複数の伝送制御局を伝送
ラインにて第１図に示すように接続する。このう
ち特定の伝送制御局がデータ伝送システム全体を
監視するスーパーバイザとなる。即ち、スーパー
バイザーとなつた伝送制御局はデータ伝送システ
ム内に異常が生じたときの対策を講ずるプログラ
ムを有している。 A plurality of transmission control stations configured in this manner are connected by transmission lines as shown in FIG. 1. Among these, a specific transmission control station serves as a supervisor that monitors the entire data transmission system. That is, the transmission control station that has become a supervisor has a program that takes measures when an abnormality occurs in the data transmission system.
次に、本発明のデータ伝送システムの起動の仕
方及びシステム内部に異常が発生したときの対策
について説明する。 Next, a description will be given of how to start up the data transmission system of the present invention and what to do when an abnormality occurs inside the system.
起動時、各伝送制御局は自局の電源を投入する
（電源回路は図示せず）。続いて自局の物理アドレ
スをアドレス設定回路ADRSにて設定し、その設
定された物理アドレスを送受信回路TRCVにも設
定する。最初この伝送制御局は、この物理アドレ
スにて他の伝送制御局とデータの授受を行なう。
従つてこのときスーパーバイザーとなるべき伝送
制御局は、第３図ａに示すような制御情報テーブ
ルを持つ。即ち、正常時には、物理アドレス
“１”と定義された伝送制御局は、同時に論理ア
ドレス“１”を有するわけである。他の伝送制御
局も順次物理アドレスと論理アドレスとを対で持
ち、これらの関係は、前述の制御情報テーブルに
登録される。制御情報テーブルに物理アドレスと
論理アドレスの対応が登録されると、これらの各
論理アドレスは、送受信回路にも設定される。従
つて各伝送制御局は、他の伝送制御局とデータの
授受を行なうときは、この論理アドレスを互いに
指定することによつて行なう。各伝送制御局は第
３図ｂに示すような情報を持つ。 At startup, each transmission control station turns on its own power (the power circuit is not shown). Next, the physical address of the own station is set in the address setting circuit ADRS, and the set physical address is also set in the transmitting/receiving circuit TRCV. Initially, this transmission control station sends and receives data to and from other transmission control stations using this physical address.
Therefore, the transmission control station that is to become the supervisor at this time has a control information table as shown in FIG. 3a. That is, under normal conditions, a transmission control station defined with a physical address of "1" also has a logical address of "1". Other transmission control stations also sequentially have pairs of physical addresses and logical addresses, and the relationship between them is registered in the control information table described above. When the correspondence between physical addresses and logical addresses is registered in the control information table, each of these logical addresses is also set in the transmitting and receiving circuits. Therefore, each transmission control station exchanges data with another transmission control station by mutually specifying this logical address. Each transmission control station has information as shown in FIG. 3b.
以上はデータ伝送システムが正常に起動したと
きの動作であるが、データ伝送システムに異常が
発生した時の動作について説明する。 The above is the operation when the data transmission system starts up normally, but the operation when an abnormality occurs in the data transmission system will be explained.
例えば、第１図で、伝送制御局ST1がスーパー
バイザーとなるべき伝送制御局であるとし、伝送
制御局ST2と伝送制御局ST3とがデータの授受を
行なつているとする。また、伝送制御局ST4は予
備局とする。これらの伝送制御局STを接続して
いる伝送ラインDLは第１図では一本の線で表わ
されているが、本実施例では２本の線を内在さ
せ、時計回りのものと、反時計回りのものとがあ
る。正常時は同図のように反時計回りのもののみ
が使用されている。 For example, in FIG. 1, it is assumed that transmission control station ST 1 is the transmission control station that should become a supervisor, and that transmission control station ST 2 and transmission control station ST 3 are exchanging data. Furthermore, transmission control station ST 4 is assumed to be a backup station. The transmission line DL connecting these transmission control stations ST is represented by a single line in FIG. There is a clockwise version. Under normal conditions, only the counterclockwise rotation is used as shown in the figure.
このような構成にて、伝送制御局ST2に異常が
発生すると、伝送制御局ST3から送信するデータ
は、伝送制御局ST2には取込まれない。あるいは
取込まれたとしても正しく処理されない。また伝
送制御局ST2からはデータの送信が伝送制御局
ST3に行なわれないことになる。つまり伝送ライ
ンDL上には一定時間経過してもデータ（有意信
号）が搬送されない。そこでデータが一定時間、
伝送ラインDLに存在しないことをタイマー回路
TMがカウントすると、スーパーバイザーとなる
伝送制御局ST1は、どの伝送制御局STに異常が
発生したかを調べる。まず伝送制御局ST2を伝送
制御局ST1は診断する。当然伝送制御局ST2から
は応答がないからこの局に異常が発生したことを
知る。更に伝送制御局ST3，ST4を伝送制御局
ST1は診断する。当然これらの局ST3，ST4から
は応答があるので、異常があるのは、伝送制御局
ST2のみであることを確認する。続いて伝送制御
局ST1は、伝送制御局ST2が有していた論理アド
レス“２”を伝送制御局ST4に割当てる。即ち物
理アドレス“４”で表わされる伝送制御局ST4の
論理アドレスは“２”に置換される。続いて、伝
送制御局ST1は、伝送制御局ST2が有していた同
一の制御情報を伝送制御局ST4に送信し、伝送制
御局ST2のバツクアツプは完了する。 In such a configuration, if an abnormality occurs in the transmission control station ST 2 , the data transmitted from the transmission control station ST 3 will not be taken in by the transmission control station ST 2 . Or even if it is imported, it will not be processed correctly. In addition, data transmission from transmission control station ST 2 is
It will not be done in ST 3 . In other words, no data (significant signal) is carried on the transmission line DL even after a certain period of time has elapsed. So the data is stored for a certain period of time,
Timer circuit that does not exist on transmission line DL
When the TM counts, the transmission control station ST 1 serving as the supervisor checks which transmission control station ST has experienced an abnormality. First, the transmission control station ST1 diagnoses the transmission control station ST2 . Naturally, since there is no response from transmission control station ST 2 , we know that an abnormality has occurred in this station. Furthermore, transmission control stations ST 3 and ST 4 are
ST 1 diagnoses. Naturally, there are responses from these stations ST 3 and ST 4 , so the problem is the transmission control station.
Make sure it is ST 2 only. Subsequently, the transmission control station ST 1 allocates the logical address "2" that the transmission control station ST 2 had to the transmission control station ST 4 . That is, the logical address of the transmission control station ST 4 represented by the physical address "4" is replaced with "2". Subsequently, the transmission control station ST 1 transmits the same control information that the transmission control station ST 2 had to the transmission control station ST 4 , and the backup of the transmission control station ST 2 is completed.
尚、伝送制御局ST2において自局異常の際は、
置換してくれる伝送制御局ST4を第４図に示すよ
うに指定してある。同図では伝送制御局のことを
ステーシヨンと呼んでいる。 In addition, in the event of an error in transmission control station ST 2 ,
The transmission control station ST 4 that will be replaced is designated as shown in FIG. In the figure, the transmission control station is called a station.
以上述べたように本発明のデータ伝送システム
によれば、各伝送制御局は物理アドレスと論理ア
ドレスの２つを持ち、通常は各伝送制御局はこの
論理アドレスを使つて、相手方を指定し、そして
異常が伝送制御局に発生すると、その伝送制御局
が有していた論理アドレスを予備の伝送制御局に
与えることができるので、データ伝送を再開する
ことができる。 As described above, according to the data transmission system of the present invention, each transmission control station has two addresses, a physical address and a logical address, and each transmission control station usually uses this logical address to specify the other party, If an abnormality occurs in a transmission control station, the logical address owned by that transmission control station can be given to a backup transmission control station, so data transmission can be resumed.
第１図はデータ伝送システムの構成図、第２図
は本発明の伝送制御局のブロツク図、第３図ａは
制御情報テーブルを示す図、同図ｂは各伝送制御
局が持つ情報を示す図、第４図は伝送制御局ST2
が有している情報を示す図である。
ST1乃至ST4……伝送制御局、PC1乃至PC2……
制御装置、Ｐ……プロセツサ、RAM……読出し
書込みメモリ、PROM……読出し専用メモリ、
PC……制御装置、TM……タイマー回路、TRCV
……送受信回路、ADRS……アドレス設定回路。
Fig. 1 is a block diagram of a data transmission system, Fig. 2 is a block diagram of a transmission control station of the present invention, Fig. 3a shows a control information table, and Fig. 3b shows information held by each transmission control station. Figure 4 shows transmission control station ST 2
FIG. ST 1 to ST 4 ...Transmission control station, PC 1 to PC 2 ...
Control device, P...processor, RAM...read/write memory, PROM...read-only memory,
PC...control device, TM...timer circuit, TRCV
...Transmission/reception circuit, ADRS...Address setting circuit.
Claims (1)
ツサと、このプロセツサが論理判断するためのデ
ータ等を格納するメモリと、自局のアドレスを設
定するアドレス設定回路と、伝送ライン上のデー
タの有無を一定時間監視し装置の異常を検出する
タイマー回路と、伝送ラインとデータの授受を行
なう送受信回路とから成る伝送制御局を複数備え
これらを伝送ラインで接続したデータ伝送システ
ムにおいて、前記タイマー回路が異常を検出した
とき所定の伝送制御局がスーパーバイザーとなり
異常を起した伝送制御局のアドレスを予備の伝送
制御局に割当て、この割当られた伝送制御局に前
記異常伝送制御局が有していた制御情報と同一の
制御情報を送出しこの制御情報に基きデータ伝送
を行なわせることにより異常伝送制御局のバツク
アツプを行なうことを特徴とするデータ伝送シス
テム。1 A processor that makes logical decisions required for data transmission, a memory that stores data etc. for this processor to make logical decisions, an address setting circuit that sets the address of its own station, and a processor that determines the presence or absence of data on the transmission line for a certain period of time. In a data transmission system that includes a plurality of transmission control stations each consisting of a timer circuit that monitors and detects an abnormality in a device, and a transmitter/receiver circuit that sends and receives data to and from a transmission line and connects these stations via a transmission line, the timer circuit detects an abnormality. When this occurs, a predetermined transmission control station becomes a supervisor and assigns the address of the transmission control station that caused the error to a backup transmission control station, and then transfers the control information held by the abnormal transmission control station to the assigned transmission control station. 1. A data transmission system characterized by backing up an abnormal transmission control station by sending out the same control information and performing data transmission based on this control information.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3818780A JPS56136059A (en) | 1980-03-27 | 1980-03-27 | Data transmission system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3818780A JPS56136059A (en) | 1980-03-27 | 1980-03-27 | Data transmission system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS56136059A JPS56136059A (en) | 1981-10-23 |
| JPS6144425B2 true JPS6144425B2 (en) | 1986-10-02 |
Family
ID=12518365
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3818780A Granted JPS56136059A (en) | 1980-03-27 | 1980-03-27 | Data transmission system |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS56136059A (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5941940A (en) * | 1982-09-01 | 1984-03-08 | Canon Inc | Local area network |
| JPS60136443A (en) * | 1983-12-26 | 1985-07-19 | Hitachi Ltd | Intra-network path switching system |
| JPS63221741A (en) * | 1987-03-11 | 1988-09-14 | Omron Tateisi Electronics Co | Terminal system |
-
1980
- 1980-03-27 JP JP3818780A patent/JPS56136059A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS56136059A (en) | 1981-10-23 |
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