JPS6142793A - High speed memory system - Google Patents

Abstract

PURPOSE:To access data at a high speed by causing a dynamic RAM to act in a page mode when a column address is coincident with the storage contents of submemory. CONSTITUTION:When a column address 1 is dissident with contents of a submemory 5, an output HIT20 of a comparator 6 becomes inactive, while a timing controller 9 becomes a random access mode to lead a low access strobe RAS to become continuously active. Then selected dynamic RAM modules 11a, 11b... are accessed at a high speed only by a row address. On the other hand, when they are coincident, the modules 11a, 11b... are brought into a page mode, and a dynamic RAM system is quickly accessed accordingly.

Description

[Detailed Description of the Invention] (Industrial Application Field) The present invention provides high-speed access to main memory by storing part of an address in an auxiliary memory mapped at the upper level of the address. It is about a high-speed memory system that can perform various functions.

(Prior art) Conventionally, when dynamic RAM (hereinafter referred to as DRAM) 7 is used in the random access memory system, DR
Since the AM atto-V path is multiplexed with the column address and row address, as shown in the first row, the daj address and row addition are respectively divided into the column address trope (hereinafter referred to as RAS) and the row address stroke (hereinafter referred to as CAB). It had to be synchronized and fed to the DRAM. Further R
For AS, Rhs grid time 1 or DRAM
It takes a non-negligible amount of time compared to the access time of . Therefore, the random cycle time, which takes about t5 to 2.5 times as long as the access time, limits the speed of the memory system.

In DRAM, as shown in Figure 2, by setting the column address to 4, keeping the RAEI active, and setting it to page mode, high-speed access can be achieved. I can do it.

With this method, data can be accessed from the second time onward by simply providing the row address and CAS request, so the cycle time is half Afj and Ik compared to the random access cycle time. For example, since computer programs and the like often access memory addresses sequentially, rather than all (randomly), successive domain pages are accessed sequentially, the probability of access in page mode 7 is very high.

(Problem? Means for solving the problem) In the memory system of the present invention, the last accessed column address of each memory bank is stored in advance in the auxiliary memory mapped at the upper address. If the part of the column address 1σ of the address given to the memory system when the memory is accessed matches the memory content, the DRAM will work in page mode, allowing access to the data at speed limit. It is composed of

(Embodiment) FIG. 6 is a block diagram of the present invention, in which eight 64Kbit
This is an example when configured with a DRAM memory bank,
FIG. 4 is a time chart of an example of this operation. The block diagram and tie and whipyard signals are consistent.

DRAM 7 joules are substituted by 8 banks a to h, and selected by bank send 1δ No. 13Sa to h. Each bank is given a common address, RAS, and CAEI, but is treated as invalid unless the BEI signal is active. In addition, the DRAM RAM module mill is constructed such that a latch B is provided to hold each RAS, and each module has 5 ICs in the page mode.

Timing controller 9 is RAE1 for DRAM
7.0A1318, WE19, multi-pressed DR
AM address bus switching 1M MUX22, auxiliary memory write signal LO21, and memory system?
Acquisition end signal ACK4Y for the accessed device
These signals are the memory system select signal 5KL3 given to the memory system, the read/write signal R/W2, and the output of the comparator 6 (g HIT2[1, the output of the clock 24 0LIC24
AlC prompts to change the operation mode. Depending on the operation mode, there are fresh mode, random access mode, and page mode, and the timing controller 9 determines the mode.

The timing roller 9 counts OL]K24a'7, enters refresh mode at an appropriate interval, and executes DR.
9777717 signals are generated for AMK.

An example of the operation used in the time chart of FIG. 4 will be explained below.

When the memory system is selected by the SEL signal 6, the part corresponding to the bank address of the upper part of the address 1 given to the memory system is given to the bank '4 voltage vector 7 and the auxiliary memory 5, and the DRAM module is selected, and the contents of the auxiliary memory 5 are read out.

The auxiliary memory has column address 2 as shown in the 5th ra.
In addition to B, a valid bit and V bit 27 are also stored.

The V bit 27 is a bit that indicates whether a clear address has been written in the past and is in refresh mode &? )Ba'7-ON
Cleared on reset.

If the read V bit 27 is active, the contents of the auxiliary memory 1' address 28 is compared by the comparator 6 with the part of address 1 given to the memory system that corresponds to the column address.

If the V bit 27 is inactive or the comparison result does not match, the output H:20 of the comparator 6 becomes inactive. In this case, the timing controller 9
enters the random access mode, writes into the auxiliary memory, generates a write signal L021, stores the portion of address 1 corresponding to the column address, and simultaneously makes KRAS'ff inactive. Next updated auxiliary memory 5 F'
3 Answer Y selector 8x passes through and gives it as a column address to the DRAM address bus, RA817'& becomes active again, and then sends the part corresponding to the row address of address 1σ to selector 8 (71)i to the DRAM address bus. The memory is accessed by activating the CAS18.

When the data access is completed, the timing controller 9 generates an access completion signal ACK4g, and the memory system informs the accessed @ device of completion. At this time, even after the access ends, the RAS 17 remains active.

When the V bit 27 is active and the comparison result is one, the output H of the comparator 6 becomes active. In this case, the timing controller 9 is in page mode, and the part corresponding to the row address of the given address 1 is transferred to the DRAM RAM address 17 through the selector 8.
The CA 318 becomes active and access is performed in page mode. Once the data has been accessed,
The timing controller 9 receives the access end signal -A C
K 4χ is generated and the device that accessed the memory system is notified of termination.

(Effects of the Invention) As explained above, the present invention provides the auxiliary memory 5 to store recently used column addresses in memory bank units,
The DRAM is configured so that when the column addresses of each bank match among the addresses given to the memory system, the DRAM operates in page mode and can be accessed at high speed.

If this method is used, when memory IJ'F is accessed continuously in a certain 11 range, the memory 7 stem can be accessed faster than when it is configured by normal random access.

Dad, memory addresses in different ranges for each bank can be used in page mode, so multitasking, multiprocessing,
It is also effective for use as a memory system in computer systems with multi-user applications.

Also, in the above ν, since 64KB TDRAM7a was used, 256 addresses were within the range that could be accessed quickly in page mode.DR of 256 KBIT or more
If AMY is used, the accessible range will be further expanded and the effect will be increased.

In addition, in this text, we have mainly explained DRAM'Y, but it is a static RAM with a configuration in which addresses are multiplexed.

1 to the memory provided by Page Morton in ROM etc.
It goes without saying that Kawato's system can be constructed.

[Brief explanation of drawings]

FIG. 1 is a time chart of memory random access mode, and FIG. 2 is a time chart of page mode. . Figure 46 is a block diagram of this 4G light. 4 is a time chart of the memory system of the present invention. The fifth L is the contents of the auxiliary memory used in the invention. The column address 2nd of this content is V bit 27 or 1 [
5... Auxiliary memory 6... Comparator 7...
Bank selector 8...Selector 9...Timing controller 10...Data 11a ~ 11h-=DRAM 7 dicor 12...
DRAM 16...RAM address 17...R
AS 1B...0AI319...WK20...
Engineering (English T 21...Lo 22...MσX signal 21a ~ 2
3h・-)3Sa 24...0LOCK 24&・0LK 26...RTtFo or more

Claims (1)

[Claims] In high-speed memory systems in which memory is accessed through external interfaces such as addresses, R/W signals, SEL signals, ACK signals, and data, the auxiliary memory mapped at the upper address level is accessed in advance at the end of each memory bank. A high-speed memory system characterized in that a DRAM stores a column address and operates in page mode when a portion corresponding to the column address matches the storage contents of an auxiliary memory.