JPS6141241A - Pcm voice transmission method - Google Patents

Abstract

PURPOSE:To attain detection of a transmission error of PCM voices through a simple circuit constitution and without increasing the redundancy, by separating an upper bit group having the violent sound from a lower bit group that has no problem in particular in terms of the hearing sense to divide the upper bit group with plural blocks for enclosure of each bit and to produce an error detecting signal with the lower bit group as its all bits defines as a block. CONSTITUTION:For an upper bit group (9-MSB), plural bits are defined as a block so that any type of bit errors can be detected. Then plural blocks are prepared so that each of those bits is included by each block. an exclusive OR operation is carried out to the divided block information to obtain detection signals P1-P8. While an exclusive OR operation is carried out to all information between LSB and the 8th bit to obtain a detection signal P9 for a lower bit group.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention provides a system for converting audio information into PCM and transmitting it at high speed to a receiving device using an optical fiber cable or the like.
The present invention relates to a PCM audio transmission system in which an error detection means is provided to detect an erroneous signal generated during signal transmission and replace the erroneous signal with another signal so that the sound does not become too loud when reproduced into an audible sound.

Conventional configuration and its problems In the method of converting the audio signal into PCM and transmitting it to the receiving device, erroneous signals were generated during the transmission process due to the introduction of pulse noise, short-term signal loss, or bit errors. In this case, when such a signal is demodulated and reproduced into audible sound, completely foreign noise will be mixed in. In particular, the more the quality and quality of the signal itself improves due to I-FI directivity, the more the problem of noise mixing due to erroneous signals becomes more prominent.

For the PCM signal, encoded data converted using a quantization bit number of 16 bits will be explained for one block. This P
To detect errors in CM audio signals, first, the transmitting device detects audio 1 encoded data (
The output P (error detection signal) obtained by exclusive ORing each bit MSB to LSB of 16 bits is added to form one word and transmitted. One possible method is to perform similar processing in the receiving device, and if the resulting values P are the same, that one word is normal, and if they are different, it can be detected as an error. For example 2
If an error occurs only in 4 locations, 6 locations, etc.), the result is judged to be normal.

In addition, as another method, as shown in FIG. 1(b), n
There is also a method in which a correction signal and an error detection code CRCC divided by a generator polynomial are added to these signals by dividing the audio sampled data into one segment, but the arithmetic processing circuits in the transmitter and receiver are The drawback is that it becomes complicated and requires a huge circuit scale.

OBJECTS OF THE INVENTION In view of these points, the present invention provides a system that can detect transmission errors in PCM audio with a simple circuit configuration without increasing redundancy.

Structure of the Invention In encoded data that has been A/D converted, there are two groups: an upper bit group that causes audible noise when a bit error occurs, and a lower bit group that causes no particular audible problem even if a bit error occurs. The upper bit group is divided into multiple blocks so that each bit can be detected even if an error occurs, and the error detection signal for that block is divided into multiple blocks. to occur. The lower bit group generates an error detection signal with all bits of the lower bit group as one block.

The error detection signals generated in this manner are transmitted after being added after the encoded data.

The receiving section compares each error detection signal with the encoded data to detect errors.

If an error is detected within the word, the error word is replaced with pre-encoded data (before being made into one block) and is supplied to the D/A converter.

Description of examples The present invention will be explained in detail below.

FIG. 2 is an explanatory diagram illustrating the method of generating an error detection signal according to the present invention, and shows an example of 16 points in which audio is made into one block.

FIG. 3 is a block diagram of a transmitter which is an embodiment of the present invention;
Figure 4 is a block diagram of a receiving section which is an embodiment of the present invention.
6 is a timing chart for explaining the operation of the transmitter shown in FIG. 3 which is the same embodiment, and FIG. 6 is a timing chart for explaining the operation of the receiver shown in FIG. 4 which is the same embodiment. be.

In Figure 2, when the analog audio signal is converted into a digital signal by the transmitter A/D converter, LSB-M
Converted to SB 16-bit code. Within this encoded data, the portion where a bit error occurs during transmission and causes an audible noise is in the upper bit group, and the lower bit group has a small level, so it does not pose much of a problem.

Therefore, the upper bit group that is the most problematic at the error location [
For example, from the 9th bit (LSB) to the 16th bit (MSB)], and the lower bits that are demodulated and do not cause any problems to the audible sense (for example, from the 1st bit (LSB) to the 8th bit).
The signal is divided into two groups, and each group is subjected to signal processing for error detection.

The upper bit group (9 to MSB) contains any bit errors (multiple bits) in this group. It is composed of a plurality of blocks so as to include the block diagram, and is divided so that an odd number of erroneous bits always occur in one of the block diagrams in response to a plurality of bit errors. An exclusive OR operation is performed on the divided block information, and Pl, P2, P3,
P4゜p6. Detection signals of p6, p7, and p8 are obtained.

Further, for the lower bit group, an exclusive OR operation is performed on all information from the LSB to the 8th bit to obtain a detection signal of P9.

This calculated pl, p2, p3, p4, p5
.

The detection signals p6, p7, p8, and p9 are added after the calculated encoded data and transmitted to the receiving section.

Each detection signal is composed of 1 bit, for a total of 9 bits. Similarly, in the receiving section, the detection signal generated by being divided into an upper bit group and a lower bit group in the transmitting section and the information in the divided block (for example, 12th, 13th, 14th, 15th, 16th bit Detection signal P2 calculated with the information of the 13th, 12th, 11th, 10th, and 9th bit information Detection signal 8+P3,) The lower bit group consists of all lower bit information (LSB to 8th bit) and its Each calculation process is performed using the detection signal P9 to detect an error. That is, error detection in the receiving section is performed using information and a detection signal. For example, if a single error occurs at the 12th bit, block P1. In columns P2, P3, P4, and P6.28, the P value calculated by the transmitter and the P value calculated by the receiver are different, and it is revealed that there is an error in this word.

The same applies to other single errors. Multiple solo exhibition J (
2, 3, 4...), the error detection signal in a block with an even number of erroneous bits in the divided block is considered normal, but if one of the multiple blocks is erroneous. Since it is divided so that the number of pits is an odd number, it can be detected in that block, and it becomes clear that there is an error in that word. Further, even if both the information bits and the error detection signal in a block are erroneous, detection can be similarly made using the same block.

In a normal line, the BER is 1o-9 or more, and even when the line is low, it is only about 10-6.In reality, there is a small probability that multiple errors will occur in the same word, but as shown above, For the problematic upper bit group,
If there is an error, it can be reliably detected.

Error detection for the lower bit group starts from the 8th bit
Although the detection signal is only 1 bit in the information up to SB,
Even if it is not possible to detect errors in the lower bits (an even number of errors in the 8th to 1st bits), this is sufficient because it does not cause any particular problem in terms of hearing.

The circuit configuration will be explained below.

In FIG. 3, 1 is an input terminal for audio encoded data, 2
is a one-word switching pulse input terminal; 3 is an output terminal that outputs a signal obtained by adding detection signals P1 to P9 to audio encoded data; 4 is a shift register; 5, 6, 7, 8, 9,
10,11. 12 and 13 are exclusive 17 circuits (EX'-Q R
), 14 is a decoder circuit, 15, 16, 17, 18, 1
9, 20° 21, 22, 23 are gate circuits, 24 is a synthesis circuit 25 is a synthesis circuit. In FIG. 4, reference numeral 26 denotes a detection signal P for the audio encoded data shown in FIG.

27 is a one-word switching pulse input terminal similar to input terminal 2, 28 is an error detection signal output terminal, 29 is a shift register, 30,
31. 32, 33, 34, 35° 36. 37. 38 is the exclusive OR operation @ (EX-OR) for performing the exclusive OR operation of each block, 39, 41. 43, 4
5,47°49.51.53.55 are error detection signals p1, p2, p3 . p4. p6. p6゜p7, p8. A gate circuit that gates the parts p and 39→P, 41→P2, 4s→P3゜4
5→P4,47→P6,49→P6,51→P7゜63
→p8 and ss→P9 are gated, respectively.

40.42, 44, 46.4B, 50, 52°54.5
6 is Pl, P2, P3, P4, P6, . P6.
P7. Gate the signals of P8 and P9. 57 is a decoder circuit, 5B, 69, 50° 61. 62, 63, 64,
65 and 66 are comparison circuits, 67 is a synthesis circuit, 68 is a previous value hold correction circuit, and 69 is an encoded data output terminal.

Next, the operation of this device will be explained using FIG. 6 and the timing chart shown in FIG.

3. A/D converted audio encoded data b is input to the input terminal in FIG. 1, and one word switching pulse (sampling period) a is input to the input terminal 2 in FIG.

The A/D converted audio encoded data b is input to the shift register 4 and shifted bit by bit.

This shift register 4 is a serial to parallel output conversion shift register.

Necessary bits in each block unit shown in FIG. 2 are calculated at each error detection signal generation position from the parallel output audio encoded data shifted one bit at a time.

C is the calculated gate pulse of Pl, d is the calculated gate pulse of P2, and e is the calculated gate pulse of P9, which are each output from the decoder circuit 13 in parallel. At the position of each gate pulse, the parallel output of each bit to be shifted and operated by the shift register 4 is outputted by each EX-OR.
Enter.

For example, when calculating P2, the bits required for the calculation from audio encoded data b are 12, 13 degrees, 14.15 degrees.
, is the 16th bit. Therefore, shift register 4
At the position of the gate pulse d of P2, only the parallel outputs (f, 9.h, i, j) where the above-mentioned bits are output are taken out, and the exclusive OR circuit (EX-OR) e
supply to.

The signal calculated by the EX-OR circuit 6 is input to the gate circuit 16 and gated by the gate pulse d of P2. P
l 1P3 1P4, P5 1 P6 1P7.
P8. Similarly, for P9, Pl is the EX-OR circuit 6 and gate circuit 15, and P3 is the EX-OR circuit 7 and gate circuit 1.
7, P4 is EX-OR circuit fil g and gate circuit 1ε, P5 is EX-OR circuit 9 and gate circuit 19, P6 is EX-OR circuit 1o and gate circuit 2o, P7
is the EX-OR circuit 11 and the gate circuit 21, Ps is EX-OR circuit 12 and the gate circuit 22, Ps
The E X OR circuit 13 and the gate circuit 23 each perform calculations. Each calculated P , P , ...
...The error detection signals of P8 and P9 are input to the combining circuit 24, and a signal k is generated. The output of the synthesis circuit 24 is input to a synthesis circuit 26 to generate a signal of 1 which is superimposed on the encoded audio data b from the input terminal 1. The output of the synthesis circuit 26 is supplied to the output terminal 3. This completes the processing in the transmitter.

In the receiving section, the received signal n transmitted to the input terminal shown in FIG. 4 26 is inputted to the input terminal shown in FIG. 4 27, and the one-word switching pulse m is inputted to the input terminal shown in FIG. 4 27, respectively. The transmitted received signal n is input to the shift register 29 and shifted bit by bit. This shift register 29 is a serial to parallel output conversion shift register. From the parallel output received signal n shifted by 1 pin, the necessary bits in each block unit processed by the transmitter are calculated at each error detection signal position. 0 is a Pl gate pulse, p is a P2 gate pulse, and q is a P9 gate pulse, which are output from the decoder circuit 67 in parallel.

At each gate pulse position, the shift register 29
The parallel outputs of each bit to be shifted and operated are input to each EX-OR circuit.

Furthermore, each output of the error detection signals P1 to P9 is extracted from the received signal n, and the EX-OR calculated by this signal and the receiving section is
By inputting the output signal of the circuit to a comparison circuit composed of an EX-OR circuit, if the P value generated by the transmitting section and the P value generated by the receiving section match, a constant value of 1'' is generated. For example, when checking P2, the bits calculated by the transmitter are the 12th, 13th, 14th, 15th, and 16th bits, so From the shift register 29, only the parallel outputs r, s, t, u, and v, in which the above-mentioned bits are output at the position of the gate pulse p of P2, are taken out and input to the exclusive OR circuit (EX-OR) 31. do.

The signal calculated by the EX-OR circuit 31 is input to the gate circuit 42, and is gated by the gate pulse p of P2.
get the signal. The output W of the gate circuit 42 is
Enter 9. On the other hand, the error detection signal P2 is taken out from the received signal n by the gate circuit 41, and the output
9. The output of the comparison circuit 59 and each other comparison circuit 68, 60, 61, 62, 63, 64°85
．． The output of 66 is input to a combining circuit 67 to obtain all error detection signals y. The error detection signal output from the synthesizing circuit 67 makes it clear which word is causing the error. The error word is delayed by one word in order to replace the encoded data one word before, and is interpolated by a pre-hold correction circuit 68 having a hold function to obtain a signal of 2. This signal is supplied to the D/A conversion circuit via the encoded data output terminal 69. pl, p3, p4, p6,
p6゜P7, P8. The same goes for checking P9.
In the x-OR circuit 30, gate circuits 39 and 40, and ratio extraction path 58, P3 is
R circuit 33, gate circuits 46 and 46, and comparison circuit 61
P6 is the EX-OR circuit 34, gate circuits 47 and 48, and the comparison circuit 62, P6 is the EX-OR circuit 33, gate circuits 49 and 5o, and the comparison circuit 63, and P7 is the EX-OR circuit 33, gate circuits 49 and 5o, and the comparison circuit 63.
-OR circuit ') is removed. In addition to bit allocation and block division for error detection in the present invention, detection is possible by dividing blocks so that the number of error bits always occurs in an odd number so that bit errors can be detected in any state. It is.

Effects of the Invention As described above, according to the present invention, it is possible to reliably detect transmission errors in PCM audio with a simple circuit configuration without increasing redundancy, and to detect PCM audio that does not give a sense of strangeness in the @ sense. It provides a transmission method and has great practical effects.

[Brief explanation of the drawing]

Figures 1a and b are general format diagrams for erroneous detection of audio encoded data, Figure 2 is a format diagram explaining the erroneous detection method of the present invention, and Figure 3 is an embodiment of the present invention. FIG. 4 is a block diagram of the transmitting section, FIG. 4 is a block diagram of the receiving section which is an embodiment of the present invention, FIG. 5 is a timing chart explaining the operation of the transmitting section in FIG. 3, and FIG. 6 is a block diagram of the receiving section in FIG. 5 is a timing chart illustrating the operation of the receiving section. 1... Audio encoded data input terminal, 2, 27.
...1 word switching pulse input terminal, 3...
・Output terminal, 4.29...Shift register, 5
, 6, 7, 8° 9.10, 11.12, 30, 31.3
2,33゜34.35.36.37.38...
Exclusive OR circuit (EX-OR), 14.57
...Decoder circuit, 15, 16, 17, 18,
19°20.21.22,23,39,40,41. 42 , 43 , 44 , 45 , 46 , 47 , 4
8. 49.50,51. 52, 53, 54, 55°66・
...Gate circuit, 24, 26.67...
Synthesis circuit, 58, 59, 60, 61. 62, 63° 64
．． 65.66... Comparison circuit, 68...
Pre-hold correction circuit, 26... Received signal input terminal, 28... Erroneous 9 detection output terminal, 69...
...Encoded data output terminal.

Claims (1)

[Claims] The encoded data obtained by A/D converting the audio signal is divided into a group of upper bits and a group of lower bits, and a plurality of bits are treated as one block, and each block is divided into blocks such that each bit is included in each block. means for detecting an upper bit group that is divided into blocks and generates an error detection signal for each of the plurality of blocks; and means for detecting a lower bit group that generates an error detection signal with all lower bits as one block. A PCM audio transmission method, characterized in that: is added after the encoded data and transmitted.