JPS6139780A - Automatic gain control circuit - Google Patents

Abstract

PURPOSE:To perform starting value type gain control operation and keyed type gain control operation in combination through one comparing circuit by amplifying a luminance signal on the basis of the head of synchronism through a couple of differential amplifiers whose emitters are connected mutually through a resistance, and using the differential amplifiers which differ in gain distinctively between a burst gate period and other periods. CONSTITUTION:A differential amplifier circuit 13 is connected between a luminance and chromaticity separating circuit 4 and a comparing circuit 13. The collector output of the transistor (TR) Q2 of the differential amplifier circuit 13 is applied to the inverted input terminal of the single comparing circuit 12 in the burst gate period, and the collector output of TRQ3 is applied in other periods. In this case, let R3=R4 and R5=R6, and further R1<R2, and the gain of Q2 is larger than that of Q3. If a synchronizing signal deforms or if a video signal exceeding a prescribed input value is inputted, the voltage of a video signal part rises above the synchronizing input voltage Va of the comparing circuit 12 except during the burst gate pulse period and a starting value type gain control circuit lowers the gain of an amplifier circuit 2. Here, the prescribed level is determined on the basis of the gain difference between Q2 and Q3 so that the starting value type gain control circuit operates.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an automatic gain control circuit that performs a combination of leading value type and keyed type gain control operations.

Conventional technology □ Television receivers, video recorders, etc. are equipped with a system such as the one shown in Figure 3, so that images with a constant contrast can be obtained regardless of the strength of input signals, such as received radio waves or reproduced RF signals. , automatic gain control circuit (AG+: 4 circuits) (2) are provided.

This automatic gain control circuit 1 uses a combination of a leading value type and a keyed type as a detection circuit 3 that generates a control voltage to be applied to an amplifier circuit 2 such as a high frequency amplifier circuit or an intermediate frequency amplifier circuit. The composite video signal which is the output of the amplifier circuit 2 is separated into only the luminance signal by the luminance/chromaticity separation circuit 4.
After the synchronous tip is clamped by a clamp circuit 5 connected via a coupling capacitor C, the signal is supplied to the detection circuit 3.

This conventional detection circuit 3 is provided with two comparison circuits 6 and 7 corresponding to each of the leading value type and keyed type gain control operations, and the outputs of these comparison circuits 6 and 7 are connected to the burst gate. It is selectively supplied to the amplifier circuit 2 as a control voltage via a switch 8 which is switched by a pulse. Note that a time constant circuit 9 is connected between the switch 8 and the amplifier circuit 2 in order to cope with sudden input changes, and the comparison circuit 6 corresponding to the leading value type detects that the luminance signal is 140% of the reference value. Keyed type comparator circuit 7 operates against excessive input exceeding %.
is 1 by comparing the amplitude based on the pedestal level.
The operation is set so that the synchronization signal has a constant amplitude.

Problems to be Solved by the Invention - F The conventional automatic gain control circuit 1 has comparator circuits 6, 6 and 6, respectively, corresponding to the leading value type and keyed type gain control operations.
7, which tends to complicate the circuit configuration.Furthermore, fluctuations in the clamp voltage in the clamp circuit 5 result in fluctuations in the comparison inputs of the comparator circuits 6 and 7, making it difficult to achieve accurate gain control. , 7, the signals are switched at a later stage, which causes problems such as signal transmission loss.

Means for Solving the Problems The present invention solves the above problems, and provides comparison means for extracting a gain control output by comparing either the peak value of the luminance signal or the peak value of the synchronization signal with a reference value. In an automatic gain control circuit that performs a combination of leading value type and keyed type gain control operations according to the gain control output, a luminance signal whose leading end is clamped to a predetermined clamp voltage is applied to the base. a first transistor, a second and third transistor to which the clamp voltage is applied to the base, and a resistor circuit connecting the emitters of the first, second and first and third transistors; an automatic gain control circuit comprising: a switch circuit that selectively takes out respective collector outputs of the second and third transistors in response to a burst gate pulse and supplies the outputs of the collectors of the second and third transistors to the comparison means as the gain control outputs; The main points are as follows.

Effect of the Invention This invention provides a luminance signal to be supplied as a comparison input to a comparator circuit commonly used for both leading value type and keyed type gain control operations, by calculating the difference in gain between the burst gate period and the non-purst gate period. amplified by a dynamic amplifier circuit.

EXAMPLES Hereinafter, examples of the present invention will be described with reference to the drawings. FIG. 1 is a circuit configuration diagram and a main part circuit diagram showing an embodiment of an automatic gain control circuit of the present invention. Furthermore, Figure 1,
Components that are the same as those in FIG. 3 are given the same reference numerals.

In FIG. 1, an automatic gain control circuit 11 performs a keyed type automatic gain control operation and a leading value type automatic gain control operation in a composite manner.
The single comparator circuit 12 allows the above two types of automatic gain control operations. A differential amplifier circuit 13 having different amplifier gains is connected between the luminance/chromaticity separation circuit 4 and the rotation input terminal of the comparison circuit 12. The differential amplifier circuit 13 includes a first emitter follower transistor QI and a common base type second and third transistors Q2 . A resistor R1 or a resistor R2 is connected between each emitter of the transistor Q3 and the emitter of the transistor Ql. Transistor Q2
．． The collector of Q3 and the power supply 700 are connected via a resistor R3 or a resistor R4, respectively. Here, resistors R3 and R4 have the same resistance value. The clamp voltage of the unclamped luminance signal in the clamp circuit 5 is set to vc1.
If the amplitude of the luminance signal is EY, then the voltage of By+Va is the first
is applied to the base of transistor Q1. Transistor Q2. The clamp voltage VC of the clamp circuit 5 is applied to the base of Q3.

Therefore, if the pace emitter voltage when the transistor is conductive is VBFi, the emitter voltage of the transistor Q+ is Ey + Vc - VBE, and the emitter voltage of the transistor Q2. The emitter voltage of Q3 becomes vc-VBFi.

Therefore, only the luminance signal EY is applied to both ends of the resistors R, , R2, and the emitter resistor R6 of the transistor Q2 receives EY/
A current of R will flow. On the other hand, a current EY/R2 flows into the emitter resistor R5 of the transistor Q3. By setting the resistance values of the resistors R5 and R6 that connect the emitters of Q3 and Q2 to the ground to be the same, the collectors of the transistors Q2 and Q3 are clamped at the same voltage and luminance signals with different gains can be obtained.

The output of transistor Q2 is Ey R4/R1+Vcc - (', R4/R6)
・(Va-VBg), and the output of transistor Q3 is EY-R3/R2+Vcc-(R3/R5)・(vc-
vBE).

Here, VOO is the power supply voltage. Here R3=R4.

From R5-R6, the output of transistor Q2 is Ey 6R3
/Rt+Vcc-(R3/R5) 6(VC-VBK)
The output of transistor Q3 is Ey ・Ra/R2+Vcc-(R3/R5) ・(V
a-VBE).

Incidentally, the inverting input terminal of the single comparator circuit 120 receives a luminance signal having a different gain depending on the burst gate period and other periods. If the collector output of transistor Q2 is applied during the burst gate period ゛, and the collector output of transistor Q3 is applied during periods other than □', then the gain during the burst gate period is EY -R.
3/R, otherwise EY -R3/R2.

At this time, the DC potential at the synchronization tip does not change.

Furthermore, R1<R2 is set, and the gain of transistor Q2 is made larger than the gain of transistor Q3.

Here, the waveforms of each part are shown in FIG. (a) shows a burst gate pulse at the input voltage of Q+ (b) and the inverted input voltage (C) of the comparator circuit 120. When the common-mode input voltage of the comparison circuit 13 is Va, a loop operates so that the voltage of the pedicle section becomes the set value va during the burst gate pulse period, and as a result, the level of the synchronization signal becomes constant.

If the synchronization signal is distorted or a video signal exceeding the specified input is input, the voltage of the video signal section will become larger than the set value Va outside the burst gate pulse period, and the gain control circuit of the leading value type will override the amplifier circuit 2. lower the gain. Here, the gain control circuit of the 7-value type can operate and determine the specified level based on the gain difference between the transistors Q2 and Q3.

As described in detail, according to the present invention, a luminance signal is amplified with the synchronization tip as a reference using a differential amplifier pair whose emitters are connected to each other by a resistor, and the luminance signal is amplified during the burst gate period and during the non-burst gate period. Since the configuration uses differential amplifiers with different gains, a single comparator circuit with a fixed standard value for comparison can perform a combination of leading value type and keyed type gain control operations. Furthermore, even if the clamp voltage used to clamp the luminance signal fluctuates, the comparison input of the comparator circuit does not fluctuate, so accurate gain control is possible.゛

[Brief explanation of drawings]

FIG. 1 is a circuit configuration diagram and main part circuit diagram showing an embodiment of the automatic gain control circuit of the present invention, FIG. 2 is a signal waveform diagram of each part thereof, and FIG. 3 is a diagram of a conventional gain control circuit. There is a circuit configuration diagram showing an example. 5... Clamp circuit, 11... Automatic gain control circuit,
12... Comparison means, 13... Differential amplifier circuit, Q+
...first transistor, Q2...second transistor, Q3...third transistor, 8...switch circuit.

Claims (1)

[Claims] Comparing means compares one of the peak value of the luminance signal and the peak value of the synchronization signal with a reference value to obtain a gain control output, and performs leading value type and keyed type gain control operations in accordance with the gain control output. In a composite automatic gain control circuit, a first transistor to which a luminance signal whose synchronization tip is clamped to a predetermined clamp voltage is applied to the base, and second and third transistors to which the clamp voltage is applied to the base. a resistor circuit connecting the transistors and the emitters of the first, second, and first and third transistors; and selectively controlling the respective collector outputs of the second and third transistors in response to a burst gate pulse applied. an automatic gain control circuit comprising: a switch circuit which extracts the output from the gain control output and supplies it to the comparison means as the gain control output.