JPS6138665B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improvement in the processing of the signal system of each line in a signal processing device that accommodates various lines and performs various processes.

Currently, equipment that accommodates various lines, receives data from the lines, and performs various processes, such as communication control equipment and data exchanges for data communications, accommodates many types of lines, and therefore each line is individually Various types of processing must be performed in accordance with the existing signaling system. For example, the signaling systems of telex lines that are currently widely used include U1, U11, and
For data terminals, there are signal systems such as ×20 and ×21.

An example of a conventional method for processing these signal systems will be described with reference to the drawings. FIG. 1 shows an example of a device configuration for processing various lines and signal systems. 1 is a signal processing device that processes various lines based on instructions from the central processing device 2;

2 is a central processing unit that controls the signal processing device 1, and is usually a program-controlled device. Next, an example of the internal configuration of the signal processing device 1 will be explained.

The signal processing device 1 is roughly divided into two parts. That is, in order to send and receive data to and from each line, the interface control unit 4 controls information transfer between the line control unit 3, which mainly controls the assembly of received characters and the disassembly of transmitted characters, and the central processing unit 2. be.

Next, a configuration example of the line control section 3 will be explained. Reference numeral 5 indicates various lines accommodated by the signal processing device 1, such as subscriber lines and trunk lines. 6 is any one of the accommodation lines 5
A scanning device for selecting books. 7 is a line memory that stores orders from the central processing unit 2 for each line and intermediate information when transmitting/receiving processing is performed; 12 is a latch register that temporarily latches the contents read from the line memory; Yes, 8
is an arithmetic unit that performs various processes based on the contents read out from the line memory 7 and the data received from the line selected by the scanning device 6. The configuration of the calculation unit 8 varies depending on the type of line to be accommodated and the division of functions between the signal processing device 1 and the central processing device 2.
Usually has a random logic configuration.

Reference numeral 9 denotes a line memory control circuit, which receives orders from the central processing unit 2 via the interface control unit 4 and stores them in the line memory 7 corresponding to the corresponding line.
In order to write to the area of , store intermediate processing results in the arithmetic unit 8, and process the line that is the arithmetic unit 8, it performs reading control of information on the corresponding line. 10 is called a register queue, and is a first-in, first-out queue. This register 10 includes an arithmetic unit 8, which will be described later.
It stores the characters assembled in , the state of the line, or status, etc. Reference numeral 11 denotes a register queue control circuit for controlling the register queue 10, which has a well-known circuit configuration having a head pointer, a tail pointer, etc.

FIG. 2 shows an example of the format of the line memory 7, in which order 3 from the central processing unit 2 is
A control part 31 that stores information such as 3, etc., and an assembly buffer 36 that temporarily stores intermediate information such as received characters.When the line is for an asynchronous terminal, multi-point sampling is performed, and the number of multi-point samplings is counted. , a sampling counter 34 for identifying one bit, and a bit counter 35 for counting the number of bits in one character. Figure 3 shows an example of the format of the register queue, in which area 4 is used to store received data or line status status such as start-stop errors and parity errors.
A flag 49 indicating whether the contents stored in 1 to 48 and 41 to 48 are data or status, and a line number 50 indicating the number of the line where these were detected.
It is composed of etc.

Next, the processing operation of this conventional device will be explained using the telex signal system U11 as an example.
FIG. 4 shows a signaling system when a call is processed from a calling station and a signaling system when a call is made to a partner station and a response is processed. First, in the case of a call, C20, C20, COT, COTC is sent from the calling station.
The characters will be sent in this order. In the signal processing device 1 that receives this character, the order for character reception is written by the central processing device 2 in the order section 33 of the line memory 7 corresponding to the line, and the scanning device 6 scans the line. At this time, the line memory control circuit 9 reads information regarding the line from the line memory 7, and the arithmetic unit 8 assembles characters using the order unit 33, intermediate information 32, and data received from the line. For example, when the C20 character is assembled,
The calculation unit 8 stores the line number 50 of the line, the received characters 41 to 48, and the flag 4 in the register queue 10.
The register queue control 11 is activated to store a flag indicating that data has been received in the register queue 10. Thereafter, received characters such as C20, COT, etc. are sequentially stored in the register queue 10 in the same manner. The central processing unit 2 sequentially reads these written contents from the register queue 10. The program in the central processing unit 2 sequentially identifies these received data, determines whether or not it is a calling sequence each time it receives a character, and detects a predetermined character sequence. The decision was made to call. This operation is exactly the same for the called trunk line.

In this way, conventionally, the signal processing device 1 receives characters, and the central processing device 2 and the software in the central processing device identify the characters received by the signal processing device 1, judge their sequence, and process the line. is being carried out.

For this reason, when the number of lines accommodated increases and the types of signaling systems increase, the software must manage the status of each line, resulting in an increase in the number of statuses, and furthermore, these processes are handled by the call processing program. Since the process is performed in
As a result, the software becomes complicated, making it difficult to create the software and reducing processing power.

An object of the present invention is to eliminate the drawbacks of the above-mentioned prior art, simplify the configuration of software in a central processing unit, thereby facilitating the creation of software, and further improve signal processing that improves processing performance. We are in the process of providing equipment.

The main feature of the present invention is that a pool memory common to each accommodation line and its control circuit are installed in a conventional signal processing device. Combinations of signal characters and character combinations expected in advance are stored in this pool memory. The central processing unit writes the contents to be reported to the central processing unit when the processing unit detects the detection. In addition, in the memory that stores control words, etc. for controlling the signal processing device, the address of the pool memory for comparing the received characters and the contents of the pool memory when the signal processing device completes character assembly is stored in advance by the central processing unit. Write it down. Each time the signal processing device completes the assembly of one character, it reads out the contents of the pool memory using the address, compares it with the received character, and updates the address if they match. If a mismatch is detected, the address is returned to the address written by the central processing unit. This operation is repeated, and when a series of character combinations is detected, the report information written in the pool memory is written to the register queue, thereby reporting to the central processing unit that a series of character combinations have been detected.

Next, the present invention will be explained using the drawings. FIG. 5 shows an embodiment of a signal processing device to which the present invention is applied. In the figure, 52 is the same configuration as the central processing unit 2 in FIG. 1, 54 is the interface control unit 4, 55 is the line 5, 56 is the scanning device 6, and 59 is the same configuration as the line memory controller 9, so the explanation will be omitted. . 51 is a signal processing device, and 53 is a line processing section. 57 has the same configuration as the line memory 7 in FIG. 1, but its contents are different. 58 is also a random logic calculation section similar to 8 in FIG. 1, but there are some differences in processing from FIG. 62 is a pool memory according to the present invention, the contents of which will be described later. Reference numeral 63 denotes a pool memory controller which performs reading from the pool memory and writing from the central processing unit 52 via the interface control unit 54 upon activation from the arithmetic unit. 64 is the normal calculation unit 5
8 is a well-known collation circuit that detects whether or not the characters assembled by the arithmetic unit 58 match the contents read by the pool memory controller 63.

FIG. 6 shows an example of the format of the pool memory. The pool memory is composed of a character section 65 and a character linkage section 66. The contents of the character section 65 are such that when character assembly is completed in the arithmetic section 58, the contents of the address of the pool memory 62 specified in advance by the central processing unit 52 are read out, and the contents of the character section 65 are checked against the assembled characters. This is the content to be reported. In FIG. 6, the contents of the pool memory 62 to be compared with the typed characters include 4
Needless to say, any number of configurations may be used depending on the functions required of the signal processing device. The character linkage unit 66 is used to assemble characters in the arithmetic unit, and if the contents match the pool memory and match, it indicates whether or not to compare with the next combined character. In the case of FIG. 6, "1" indicates that the characters assembled in the arithmetic section are compared with the contents of the next address in the memory pool,
“0” indicates that there is no need to compare any more, that is, a series of character combinations have been detected, and the content of the next memory pool address is sent to the central processing unit.
This indicates that the report will be made to 2.

For example, if the contents of the characters combined in the arithmetic unit 58 are
If it is CHA1, the content matches CHA167 in FIG. Also, since the character linkage section 66 is "1", character verification continues. That is, when the next character is assembled in the arithmetic section 58, the contents are compared with the character section 65 at the next address in the memory pool. If the next character is CHA2, it matches the memory pool content CHA2,68, and in this case, the character linkage part 6
Since 6 is "0", there is no need to perform any more character matching, and the contents of the next memory pool, i.e.
This indicates that EVTA69 is to be reported to the central processing unit.

FIG. 7 shows an example of a portion of the memory footprint of the line memory 57 related to the present invention. In the figure, the order section 80 has the same contents as the order section 33 in FIG. 2, the bit counter 72 has the same contents as 33, the sampling counter 71 has the same contents as 34, and the assembly buffer 70 has the same contents as 36, so the explanation will be omitted. . Reference numeral 79 indicates the address of the pool memory 62 for comparing the contents with the pool memory 62 when characters are assembled in the arithmetic unit 58, and is written in advance by the central processing unit 52. Reference numeral 78 designates a counter, in which a character is assembled in the arithmetic unit 58 and compared with the contents of the pool memory 62, and if the contents match, it is compared with the contents of the next address in the pool memory 62 when the next character is assembled. This is used to advance the address, and the pool memory 62 is read out based on the pool memory address 79 and the contents of the counter 78. 7
Reference numerals 3 to 76 are flags, and when the characters assembled with the arithmetic unit 58 match the pool memory address 79 and the contents of the address of the pool memory 62 indicated by the counter 78, a flag of "1" is set, for example. The example in Figure 7 corresponds to the pool memory in Figure 6, CHA1, 67,
SA73 if it matches the contents of CHA2, 68...
flag. 77 is work bit,
Sequentially, the received characters and the final content of the pool memory 62, that is, the content whose character linkage section is "0", match, and the report content stored at the next address of the pool memory 62 is sent to the central processing unit 52. For example, it means reporting EVTA69 in FIG. In this case, the arithmetic unit 58 loads the contents of the pool memory 62 corresponding to the work bit 77 and the flags 73 to 76 set into the register queue 60. For example, if work bit 77 and flag SA 73 are set, this means the contents of the pool memory indicated by pool memory address 79 and counter 78, that is, EVTA 69 in FIG. 6, and the contents of EVTA 69 are loaded into register queue 60.

Next, an example of the operation of the signal processing device according to the present invention will be explained. Normally, the arithmetic unit 58 of the signal processing device not only has a random logic configuration as described above, but also has internal circuits that are used in multiple ways for various processes, but a signal processing unit 58 that extracts only the portion related to the present invention is An example of the configuration of the processing device is shown in FIG.

Further, in order to make the present invention more understandable, a case will be described in which only one combination of consecutive characters is detected. In this case, since only one type of consecutive character combination is detected, the contents of the pool memory 62 are as follows: In FIG. 6, the character section 65 is CHA1, 67,
CHA2, 68EVT69... and the character linkage have only one row of "1", "0", and "0".
58 is an arithmetic unit, and only the portions related to the present invention are shown. 102 is a latch register;
Only the parts related to the present invention are shown. Assume now that the signal processing device 51 performs an operation of reporting EVTA69 to the central processing device 52 when it detects consecutive characters CHA1 and CHA2. In this case, CHA1,
CHA2 and EVTA are written in the pool memory address field 79 of the line memory 57, and the starting address of the fixed addresses of this pool memory is written.

Further, the contents of "0" are written in the counter section 79, and the contents of "0" are also written in the work bit 77.
When the received data from a certain line reaches one character,
One character of data is temporarily stored in the line memory 57, and the data is read out to the assembly buffer section 110 of the latch register 102. At this time, the calculation unit 58 calculates the starting address where the character to be compared is stored in the pool memory 62, that is, the pool memory address 111, and a counter (0 in this case).
Pool memory 62 at the address indicated by the contents of 112
Read the contents of. In this case, access from the central processing unit 52 is prohibited as shown by the gate 113 in FIG. A matching circuit 64 determines whether the data read from the pool memory 62 and the combined data match, and if they match CH1, the contents of the counter 112 are incremented by +1 based on the output result from the matching circuit. . Also, in this case, the character linkage 66 is 1, so in order to check against the next character to be assembled, the pool memory address is the contents of 111 as is,
The counter 112 receives the +1 result from the flag 115.
The arithmetic unit 58 processes the contents of "1" and "0" of the work bit 116, and stores these contents in the line memory 57 by the operation of the line memory controller 59.

When the next character is assembled again, the arithmetic unit reads the content to be compared from the pool memory 62 in the same manner as described above. In this case, since the counter 112 has been incremented by 1, the access address of the pool memory 62 is the previous address incremented by 1. Here, the verification circuit 64 performs verification again, and if they do not match, the contents of the counter 112 are set to "0" and written to the line memory 57, and the process returns to the beginning again as if the series of characters were not detected. Repeat the same action.
If they match, the character linkage section 66 is "0" in this case, so the gate 117 determines that a series of characters has been detected, adds 1 to the contents of the counter section 112, and accesses the result again. For bit 116, "1" is written into line memory 57.

When the contents of the line memory 57 for the line are read again in the next cycle, the access bit is "1" at this time, and the contents read from the pool memory 62, that is, the contents of EVTA, are transferred to the gate 118. The data is written to the register queue 60 by the register queue controller 61 via the register queue controller 61. This content is read by the central processing unit 52 by register queue scanning from the central processing unit 42, and the software stores CHA1 and CHA2 on the line.
It is reported that a sequence of characters has been detected.

For example, in the telex U11 sequence of FIG. 4, the software is notified that a call has been placed on a certain line.

In order to perform initial setting, the arithmetic section 58 of the signal processing device writes the contents of the counter section 112 as "0" and the contents of the access bit 116 as "0" to the line memory 57, and executes the same process again.

The operations described above are controlled by the order 80 in FIG. 7 from the central processing unit 52, and if the order 80 requests a column operation,
It goes without saying that the signal processing device performs other operations similar to ordinary processing devices.

As described above, in the signal processing device according to the present invention, consecutive characters can be detected as desired, and the number of combinations can also be made as desired. Furthermore, when consecutive characters are detected, the content of the report can be arbitrarily made.

For example, in the case of a signal processing device that accommodates a large number of telex lines, the subscriber side requests the communication time and time (for example, if there are 4 consecutive letters "B")
I don't know if I will receive a request for an operator call.
In this case, in the conventional device, the software must constantly monitor the received characters on all lines in communication and manage the status of each line. However, by using the present invention, consecutive characters to be detected by the signal processing device are written in advance in a memory common to each line, and
Furthermore, by writing the report contents at the same time, the signal processing device using time division multiplexing can monitor all lines and report to the central processing unit according to the detected contents for each line.

Therefore, the software does not need to monitor the characters or manage the status of each line at all, simplifying the software configuration, making it easier to create software, and at the same time improving the processing capacity of the central processing unit. I can do it.

[Brief explanation of the drawing]

FIG. 1 is an example of the configuration of a conventional signal processing device, FIG. 2 is an example of a line memory memory format in a conventional signal processing device, FIG. 3 is an example of a register queue memory format in a conventional signal processing device, and FIG. 5 is a block diagram of an embodiment of the signal processing device according to the present invention. FIG. 6 is a block diagram of an embodiment of the signal processing device according to the present invention, and FIG. 7
The figure shows an example of a line memory format of a signal processing device according to the present invention, and FIG. 8 is a part of a circuit diagram of the signal processing device for explaining the outline of the operation of the signal processing device according to the present invention. 51...Signal processing device, 52...Central processing unit, 5
3... Line control unit, 54... Interface control unit,
55... Line, 56... Scanning device, 57... Line memory, 58... Arithmetic unit, 59... Line memory controller, 60... Register queue, 61... Register queue controller, 62... Pool memory, 63... Pool memory controller, 64... Verification circuit , 102
...Latch register, 110... Assembly buffer, 111... Pool memory address, 112... Counter, 113... Gate circuit, 114... +1 circuit, 115... Flag SA, 116... Work bit, 117, 118... Gate circuit.

Claims (1)

[Claims] 1. In a signal processing device that executes various types of processing on a large number of data lines by time division multiplexing according to instructions from a central processing unit for storage program control, a common memory is provided for each data line, and a memory is provided that is used to store predicted information in advance in the memory. A series of combinations of signal characters from the data line and information to be reported to the central processing unit when the signal processing unit detects the combination of characters are written, and the signal characters from the data line specified by the instructions from the central processing unit are written. Each time the data is received, it is checked against the data stored at a predetermined address in the memory, and if they match, the address in the memory is updated;
A signal processing device characterized in that when a combination of a series of characters is detected, information to be reported to a central processing unit is read from the memory and transferred to the central processing unit.