JPS6134951A - Monitor section for evaluating semiconductor device capacity - Google Patents

Abstract

PURPOSE:To determine an extremely small capacity with high precision by a method wherein a conductive layer is formed within an insulating layer positioned between at least a portion of a pad or wiring, connected to one of two locations in a monitor section, and the other of the two locations, and a voltage independent of the voltages to be applied to the two locations in the monitor section is applied to this conductive layer. CONSTITUTION:To evaluate a capacity Cj between two prescribed locations in a semiconductor device, for example, a semiconductor substrate 1 and a wiring conductive layer 2 formed at a portion on the surface of the semiconductor substrate 1, at least an additional pad' 5 is built, equivalent in structure to the regular locations 1, 2 and capable of applying separate voltages respectively to the regular locations 1, 2. In a monitor section for evaluating capacity designed as such, a conductive layer 10 is formed in an insulating layer 3' positioned between the pad 5', connected to the location 2, and the location 1 or between the pad 5' and at least a portion of a wiring connecting the pad 5' and the location 2. A pad 11 is formed to connect to the conductive layer 10 and, to this pad 11, a voltage may be applied which is independent of the voltages to be applied to the locations 1, 2 of the monitor section.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a capacitance evaluation monitor section κ formed in a semiconductor device to evaluate various capacitances in the semiconductor device.

[Technical background of the invention]

For example, when it is desired to evaluate the junction capacitance of a wiring semiconductor layer in a semiconductor device, a monitor section having a structure similar to the regular junction capacitance section and a lead section for displaying the number of measurement electrodes is attached to the semiconductor device. The capacitance of this capacitance evaluation monitor section is measured.

FIG. 4 shows a conventional example of this type of junction capacitance evaluation monitor section, where 1 is a p-type silicon substrate, 2 is an n-type silicon substrate doped with arsenic on a part of the surface of the substrate, and 3 is a p-type silicon substrate. An insulating layer 4 formed on the surface of the substrate is formed within the insulating layer 3.
``A contact hole formed on M2; 5 is a metal wiring (for example, aluminum) formed in the contact hole 4 and integrally formed on a part of the insulating layer 3; 6 is a metal wiring 5 formed on the insulating layer 3; An insulating layer 7 formed on the top and the insulating layer 3 is for indicating the number of electrodes of the wiring 6.
This is a hole made in the insulating layer 6 above the pad portion 72 for connecting the portion 5' and an external electrode (not shown).

Here, the purpose of evaluation is the junction capacitance Cj between the n10 layers 2 and the substrate 1 in the monitor section.

The capacitance C in the monitor section is measured by the wiring 5.
A substrate potential V8UB is applied to the substrate electrode take-out shaft (not shown) while fixing the potential of the substrate portion 5' to a constant value.
When t is slightly changed, it can be obtained by measuring the charge ΔQPAD' flowing from the flat portion 5'. Here, ΔvsUB is a small amount of change in vBUIl.

[Problems with background technology]

By the way, there is a stray capacitance C between the wiring 5 and the substrate 1 in the monitor section, and as shown in FIG. Junction capacitance Cj and stray capacitance C1 are connected in parallel. In other words, the C required for the above-mentioned measurement is C = Cj + C.

This means that Cjf including C8 as an error has been measured. In this case, the size of the parasitic capacitance c is approximately 345 fF (for example, assuming that the size of the pad portion 5' is 100 μm x 100 μm and the thickness of the insulating layer 3 is f I km).
1fF is equal to 1O-15F-t". Therefore, if the junction capacitance Cj to be evaluated is a minute capacitance smaller than the above stray capacitance Cs, the measurement accuracy will be significantly insufficient with the above structure of the monitor section. , it is impossible to measure.

[Purpose of the invention]

The present invention has been made in view of the above-mentioned circumstances, and provides a monitor section for evaluating the capacity of a semiconductor device, which enables highly accurate measurement of even minute capacitances in a semiconductor device.

[Summary of the invention]

That is, in order to evaluate the capacitance between two predetermined parts in a semiconductor device (for example, a semiconductor substrate and a wiring conductive layer formed on a part of the surface thereof), In a monitor unit for capacity evaluation of a semiconductor device, which has a structure similar to that of a regular part, and at least one gradation is formed so that an independent potential can be applied to each of the two parts, this monitor A conductive layer is formed in the insulating layer between at least a part of the wire connected to one part of the part or this part and the other part, and this A conductive layer is connected to the conductive layer, and a conductive layer is formed so that a potential independent of the potentials applied to the two portions of the monitor section can be applied to the conductive layer as well. It is something to do.

Therefore, by applying a constant potential to the conductive layer, electrostatic shielding is performed between the motherboard or wiring connected to one part of the monitor section and the other part, and these two Accurate measurement is possible even if the capacitance between the parts is minute.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings. Compared to the conventional example described above with reference to FIG. 4, the junction capacitance evaluation monitor section shown in FIG. The structure is different in that the manufacturing process is slightly different due to this, and the other parts are the same, so the same parts as in FIG.

That is, the conductive layer 10 is formed within the insulating layer 3' between a part of the wiring 5 (including the pad portion 5' in this example) and the substrate 1 in order to completely shield the space between the two. ),
It consists of a polycrystalline silicon layer doped with phosphorus as an impurity, for example. The second electrode 1 is necessary for applying a constant potential to the conductive layer 10, and is provided on the insulating layer 3' above one end of the conductive layer 10, and below it. It is connected to the conductive layer 10 through the contact hole portion 11' and is made of aluminum, for example. A hole 12 necessary for external connection is provided in the insulating layer 6' on this second pad 11.

In the monitor section with the above configuration, n+7iiff and board 1
If the junction capacitance between the wiring 5 and the conductive layer 10 is represented by CA, and the capacitance between the conductive layer 10 and the substrate 1 is represented by C8, these circuit connections are This is shown in an equivalent circuit as shown in Figure 2.

That is, the CA and C5 are connected in series between the first pad (pad portion of the wiring 5) 5' and the substrate electrode 1', and the Cj is connected in parallel to them). ,
A second node 4 is connected to the connection point between CA and CB.

Now, the first pad 5' and the second pad 11 are fixed by applying a constant potential to each independently, and the substrate potential V8 is set.
By measuring the charge ΔQPAD flowing from the first pad 5' when UIl is slightly changed,
The capacitance between the first pad 5' and the substrate 1 can be determined. In this case, CB and Cj are charged and discharged with respect to the minute change ΔvgU]I in vsU]], but since the potential across CA is constant, CA
Charging and discharging is not performed. Therefore, the above ΔQPA
D1 corresponds to the change in the amount of charge of Cj, and C' above represents the junction capacitance Cj. Since stray capacitance is not included as an error, it is possible to measure fine junction capacitance CjO with high precision. Become.

Note that since the conductive layer 10 does not completely shield the space between the wiring 5 and the substrate 1, the measured capacitance C' does not include any stray capacitance as an error. However, as a result of actual measurements, the stray capacitance between the wiring and the board was 0.3 fF in this example, whereas it was C, # 345 fF in the conventional example.
(It is about 1/100 of the conventional example, and the effect of reducing stray capacitance by the conductive layer 10 is very large.

Furthermore, although the above embodiment requires an additional process for forming the conductive layer 10f within the insulating layer 3' compared to the conventional example, this can be easily realized by a normal MOS-LSI manufacturing process. All □The range of applications of semiconductor devices that can be adopted is wide.

Note that the present invention is not limited to the above junction capacitance,
It can also be applied to other capacitances in semiconductor devices, such as a monitor section for evaluating the capacitance of a MOS transistor or a monitor section for evaluating inter-wiring capacitance. That is, in order to configure a monitor section for evaluating the electrode junction capacitance of an N-channel MOS transistor, for example, the source region of the MOS (insulated dart type) transistor should correspond to n12 in the above embodiment, and the wiring should be made in the same manner as in the above embodiment. 5. A conductive layer 10, a second pad 11, etc. may be provided. FIG. 3 shows an example of a monitor section for evaluating inter-wiring capacitance.
1.32 respectively connected correspondingly. When the second aluminum wires ss and s4 are formed on the insulating layer 3', the capacitance C between the polycrystalline silicon wires 31 and 32
In order to reduce the stray capacitance Cs'e between the first layer polycrystalline silicon wiring 31 and the second aluminum wiring 34, which is unnecessary for X't- evaluation, a conductive layer 35 is interposed, and the A constant potential can be applied independently from an electrode pad (not shown).

〔Effect of the invention〕

As described above, according to the capacitance evaluation monitor unit of the present invention, stray capacitance can be reduced to a very small level when measuring capacitance for evaluation purposes such as junction capacitance and wiring capacitance. However, it has the advantage of allowing highly accurate measurements.

[Brief explanation of drawings]

FIG. 1 is a sectional view showing an embodiment of a monitor section for capacity evaluation of a semiconductor device according to the present invention, FIG. 2 is an equivalent circuit diagram of the monitor section in FIG. 1, and FIG. 3 is another embodiment of the present invention. FIG. 4 is a sectional view showing an example, FIG. 4 is a sectional view showing a conventional example, and FIG. 5 is an equivalent circuit diagram of the monitor section shown in FIG. DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 1'... Substrate electrode, 2... Impurity layer, 3/, 6/... Insulating layer, 5.33.34...
・Aluminum wiring, 5'...421 part (first
Mother, de), 10.35... Conductive layer, 11... Second para p, s1゜32... Polycrystalline silicon wiring, Cj.
...Junction capacitance, cx...Inter-wiring capacitance, Cs, CA,
CB... Stray capacitance. Applicant's representative Patent attorney Takehiko Suzue Figure 3 Figure 4 Figure 5 sus

Claims (5)

[Claims] (1) In order to evaluate the capacitance between two predetermined parts in a semiconductor device, the two parts have the same structure as the regular part and are separate from the regular part, and independent potentials are applied to the two parts. In a monitor section for evaluating the capacitance of a semiconductor device in which at least one pad is formed to enable
A conductive layer is formed in the insulating layer between the pad connected to one part of the monitor section or at least a part of the wiring between this pad and the one part, and the other part. A capacitance evaluation monitor for a semiconductor device, characterized in that a connected pad is formed, and a potential that is independent of potentials applied to the two parts of the monitor section can be applied to the pad. Department. (2) Capacity evaluation of the semiconductor device according to claim 1, wherein the two parts are a semiconductor substrate and a wiring impurity layer provided on a part of the surface of the substrate. monitor section. (3) Capacity evaluation of the semiconductor device according to claim 1, wherein the two portions are a semiconductor substrate and one electrode region of a MOS transistor formed on the surface of the substrate. monitor section. (4) The monitor unit for evaluating the capacitance of a semiconductor device according to claim 1, wherein the two parts are two-layer wiring formed in an insulating layer on a semiconductor substrate. . (5) The monitor unit for evaluating the capacity of a semiconductor device according to claim 1, wherein the conductive layer is made of polycrystalline silicon doped with impurities.