JPS6134634B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to an electronic timepiece device having a power failure compensation circuit that reduces power consumption during a power failure. Conventionally, electronic devices such as microcomputer systems that have an electronic clock device are equipped with a power supply with a backup battery that supplies power to the electronic clock device in order to operate the electronic clock device normally in the event of a power outage. The clock control circuit output is connected to the control terminal of the electronic clock circuit, and if power is supplied only to the electronic clock circuit from the backup battery during a power outage, an erroneous control signal may be transmitted from the clock control circuit immediately after the power outage or power is restored. , the electronic clock circuit sometimes malfunctioned. That is,
Control signals such as those shown in the code table below are input from the clock control circuit to the control terminals of the electronic clock circuit via, for example, four signal lines. If the output control signal is not stable, C ₀ ~
There were cases where all _C3 's became "1", which caused a problem in that the timekeeping operation by the electronic clock circuit was disturbed, causing a significant advance or delay.

[Table] Therefore, in order to eliminate such malfunctions, it is necessary to supply power to both the electronic clock circuit and the clock control circuit from the backup battery during a power outage, which not only consumes unnecessary power but also reduces the The purpose of this is to solve the drawback that the capacity must be increased. This will be explained below using figures. FIG. 1 shows an embodiment of the first invention.
A clock control circuit 3 is supplied with a DC power source obtained by rectifying a commercial power source, and receives an input signal to the control terminal R of an electronic timepiece circuit 2, which is supplied with power from a power outage compensation power source 1 having a
A switch circuit 4 is provided for switching between the output signal of
Power is supplied to the switch circuit 4 from a power failure compensation power supply 1, and the switch circuit is controlled by the output of a power failure detector 5 that detects a power failure in the commercial power supply. In the figure, D ₁ and D ₂ are diodes, and R ₁ to _{R 4} are resistors. Note that as the switch circuit 4, an analog switch or an AND gate can be used. FIG. 2 is an explanatory diagram of the operation of the above-described embodiment, in which when a power outage occurs, the voltage Vcc of the DC power supply is changed to the Zener voltage vz of the Zener diode Z connected to the base of the transistor T of the power outage detection circuit 5 and the transistor T.
When the voltage falls below the sum of the base-emitter voltages of No voltage is applied to the control terminal R of the electronic timepiece circuit 2, and a voltage is applied to the control terminal R from the backup battery E via the resistor _R2 , so that the electronic timepiece device 2 operates normally. On the other hand, when the power outage is restored, when the voltage Vcc of the DC power supply rises and exceeds the sum of the zener voltage Vz of the zener diode Z and the base-emitter voltage VBE of the transistor T, the switch circuit 4
The voltage Vc at the control terminal C becomes "H" level, the switch circuit 4 becomes conductive, and the output signal of the timepiece control circuit 3 is applied to the control terminal R of the electronic timepiece circuit 2. At this time, the zener voltage of zener diode Z
Since Vz is set to a voltage at which the timepiece control circuit 3 operates normally, the electronic timepiece device returns to normal operation. FIG. 3 shows an embodiment of the second invention, in which the control input of the switch circuit 4 is connected via a delay circuit 6 consisting of a resistor R ₆ and a capacitor C ₄ having a bypass diode D ₄ in the opposite direction. While applying the DC power supply Vcc, the DC power supply Vcc is connected to a resistor _R5 having a bypass diode _D3 in the forward direction and a capacitor _C3.
The second delay circuit 7 is connected to the power supply terminal X of the control circuit 3 through a second delay circuit 7 consisting of the following. FIG. 4 is an explanatory diagram of the operation of the above-described embodiment. As shown in the figure, when a power outage occurs, the charge stored in the capacitor _C3 of the delay circuit 7 is discharged via the resistor _R5 , and the electric charge of the clock control circuit 3 is discharged. Voltage Vx applied to feed end X
Since the voltage gradually decreases, the clock control circuit 3 will operate normally for a while after the power outage. On the other hand, the charge stored in the capacitor _C4 of the delay circuit 6 is discharged through the diode D4, so that the voltage Vc applied to the control terminal C of the switch circuit ₄ is
instantly goes to the "L" level, and the switch circuit 4 is suddenly cut off. Therefore, while the timepiece control circuit 3 is operating normally, the control voltage applied to the control terminal R of the electronic timepiece circuit 2 is supplied from the backup battery E, and the electronic timepiece device 2 is operating normally. works. On the other hand, when the power outage is restored, the capacitor C ₃ of the delay circuit 7 is replaced by the diode D ₃
Since the normal DC power supply voltage Vcc is immediately applied to the clock control circuit 3 and outputs a normal control signal, the capacitor of the delay circuit 6
_C4 is charged via resistor _R6 , and the voltage Vc applied to the control terminal C of the switch circuit 4 gradually rises, so the switch circuit 4 remains in an off state for a while after the power outage returns. It turns out. Therefore, when the switch circuit 4 becomes conductive, a normal control signal is input from the timepiece control circuit 3 to the electronic timepiece circuit 2, and the electronic timepiece device returns to normal operation without malfunction. The present invention is configured as described above, and is provided with a switch circuit 4 that prevents erroneous control signals from the timepiece control circuit 3 that occur during a power outage or a power outage recovery, and provides the timepiece control circuit 3 with a normal operating voltage. is supplied, the electronic clock circuit is controlled by the output of the clock control circuit 3, and when the normal operating voltage is not supplied, the power failure compensation power supply 1 connects the control terminal R of the electronic clock circuit 2. Since a control voltage is applied, the electronic clock device may malfunction due to an unstable control signal (which may result in an erroneous control signal) output from the clock control circuit during a power outage or when the power is restored. It has the effect of never happening. In addition, the clock control circuit that controls the electronic clock circuit is supplied with DC power obtained by rectifying the commercial power supply, and is not supplied with power from the power outage compensation power supply, which reduces power consumption during power outages. This has the advantage that the electric power stored in the backup battery of the compensation power source can be used effectively to downsize the backup battery or extend the power outage compensation period.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of one embodiment of the present invention, FIG. 2 is an explanatory diagram of the same operation, FIG. 3 is a circuit diagram of another embodiment, and FIG. 4 is an explanatory diagram of the same operation. 1 is a power failure compensation power supply, 2 is an electronic clock circuit, 3 is a clock control circuit, 4 is a switch circuit, 5 is a power failure detector, 6 and 7 are delay circuits, E is a backup battery, and D ₁ to _{D 4} are diodes. , R ₁ ~ R ₆ are resistors, C ₁ ~
_C3 is a capacitor, T is a transistor, and Z is a Zener diode.

Claims (1)

[Scope of Claims] 1. An input signal to a control terminal of an electronic timepiece circuit supplied with power from a power failure compensation power supply having a back-up battery is an output signal of a timepiece control circuit supplied with a DC power source obtained by rectifying a commercial power supply. A switch circuit is provided to switch to a constant control voltage from the power outage compensation power supply, and the switch circuit is supplied with power from the power outage compensation power supply, and the switch circuit is controlled by the output of a power outage detector that detects a power outage in the commercial power supply. An electronic clock device consisting of 2. The input signal to the control terminal of the electronic clock circuit, which is supplied with power from the power outage compensation power supply having back-up battery, is converted into the output signal of the clock control circuit, which is supplied with the direct current power source obtained by rectifying the commercial power supply, and the output signal from the power outage compensation power supply mentioned above. A switch circuit for switching to a constant control voltage is provided, and power is supplied to the switch circuit from a power failure compensation power source, and as a control input of the switch circuit, the above control voltage is supplied through a delay circuit consisting of a resistor and a capacitor having a bypass diode in the opposite direction. While applying the DC power, the DC power is connected to a second circuit consisting of a resistor and a capacitor having a forward bypass diode.
An electronic timepiece device connected to the power supply end of the control circuit through a delay circuit.