JPS6130184A - Clamping circuit for stepped signal - Google Patents

Abstract

PURPOSE:To clamp a stepped signal with simple constitution by clamping the 1st and 2nd levels of an input signal at the same potential respectively, extracting a DC component and the extracting an AC component of the input signl independently of the DC component to add the AC component to the DC component. CONSTITUTION:A stepped linear sequentialy color difference signal inputted through a terminal is branched to a clamping circuit 20 and an HPF21. The circuit 20 executes normal clamping on the basis of a clamping pulse having horizontal frequency corresponding to the pedestal part of an input color difference signal and outputs a signal clamped to a required clamped voltage VC. The clamped output is sent to an LPF22 having several times the time constant of a vertical scanning period and the DC component of video information is extracted. The output of the LPF is added to the input signal obtained from the HPF 21 by an adder, so that the DC component of the input signal is removed and the original signal is reproduced.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a circuit for clamping signals transmitted with alternating level differences (steps).

BACKGROUND ART AND PROBLEMS Generally, a clamp circuit is configured to clamp a constant level portion of a signal of a predetermined period to be clamped to a desired potential. For example, a portion considered to be a constant bell, such as a high or low level portion of a square wave, or a pedestal portion or a sync tip portion of a video signal, is clamped.

However, there is a signal in which portions to be clamped are transmitted at alternating periods with different levels, although at a constant period. For example, in the recording system of an electronic still camera, the R-Y and B-Y signals obtained from the image sensor are line-sequentially frequency-multiplexed with FML in the low range and FM luminance signal in the high range.
It is designed to record on a magnetic disk. In the reproducing device, a frequency difference is generated in the FM carrier in order to distinguish line-sequential RY and BY signals from each other. For this reason, a circuit is inserted in the front stage of the FM modulator of the recording system to create a DC level difference alternately in lines (horizontal scanning) between R-Y and B-Y. This DC level difference becomes a difference in carrier frequency of the FM signal.

If video signals having such line-sequential step levels are clamped using clamp pulses with horizontal periods corresponding to the pedestal sections, the step information will be lost.

Conventionally, therefore, a method has been adopted in which one of the two levels is discriminated and clamping is applied only to this one level. This method requires a level discriminator such as a window comparator, and therefore has a complex circuit.
There is also a risk of malfunction.

OBJECTS OF THE INVENTION In view of the above-mentioned problems, it is an object of the present invention to clamp signals with alternating level differences by simpler means.

Summary of the Invention The clamp circuit of the present invention is a circuit for clamping a stepped signal in which signal portions of a predetermined cycle to be clamped are alternately at first and second levels, and the clamp circuit is a circuit for clamping a stepped signal in which the signal portions of the input signal to be clamped are alternately at the first and second levels. , a circuit 20 that clamps the second level portions to the same potential, and a DC output of the clamp output.
(low-pass filter 22), and a circuit (bypass filter 21) that extracts the input signal OAC component (low-pass filter 22).
) and a circuit (adder 23) that adds the extracted DC and AC components. With this configuration, the clamp circuit for the stepped signal can be made simpler.

Example The present invention will be explained below based on examples.

FIG. 1 is a block diagram of a recording system of an electronic still camera to which the clamp circuit of the present invention can be applied, and FIG. 2 is a waveform diagram of a stepped line sequential color difference signal to be recorded.

In FIG. 1, a video signal obtained from a CCD 1 is transmitted through process amplifiers 2a to 2d to a luminance signal, R, G,
The B signals are outputted to the synchronization addition circuit 3 and the matrix circuit 4, respectively. Note that the synchronization signal is generated by the synchronization generator 16, and each horizontal and vertical synchronization signal is also supplied to the imaging section to drive the CCD 1.

The luminance signal Y is FM modulated in the high frequency range by an FM modulator 5, and then sent to a bypass filter 6, a mixer 7, and a recording amplifier 8.
The signal is supplied to the magnetic head 9 via the servomotor head 9, and recorded on the magnetic disk 10.

On the other hand, the color difference signals R-Y and B-Y of the matrix circuit 4
is converted into a line-sequential signal by a changeover switch 11, a step G is added to it by a level difference adding circuit 12 as shown in FIG. The FM-modulated line-sequential signal is introduced into the mixer 7 through the low-pass filter 15, mixed with the FM luminance signal, and recorded on the disk 10.

The center frequencies of the recorded FM color difference signals are 1.2 MHz for R-Y and 1.3 MHz for B-Y due to the step difference. On the other hand, the luminance signal is FM modulated with a deviation of 6 to 7.5 MHz, and is recorded separately from the color difference signal in band. The color difference signal system clamp circuit 13 includes an FM modulator 14
This modulation input is inserted to fix the level of the modulation input to the LH (horizontal synchronization), as shown in Figure 2A, so conventionally it is used as a clamp pulse. A clamp pulse every 2H as shown in FIG. 2B located at the pedestal was used and required a level discriminator to clamp only one of the two levels.

Note that in playback machines for recorded discs, a delay line such as a CCD is used, for example, to convert line-sequential color difference signals into simultaneous color difference signals, and a clamp circuit is provided at the input of the delay line to fix the level of the signal to be delayed. In this case as well, a level discrimination function is required to clamp the stepped line sequential signal.

Furthermore, in the prior art, since steep mid-shaft operations are performed at the leading and trailing edges of the clamp pulse shown in FIG. 2B, clamp noise N may be superimposed on the clamp output.

FIG. 3 is a block diagram of the clamp circuit of the present invention, and FIG. 4 is a signal waveform diagram of each part in FIG.

The input stepped line sequential color difference signal (FIG. 4A) is branched to a clamp circuit 20 and a bypass filter 21. In the clamp circuit 20, normal clamping is performed based on a horizontal frequency clamp pulse (FIG. 4B) corresponding to the pedestal portion of the input color difference signal, and the voltage is clamped to the desired clamp voltage Vc shown in the fourth [IC]. A signal is derived.

Note that the level difference information disappears due to this clamping.

The clamp output is supplied to a low-pass filter 22 having a very long time constant of several V or more (■ is the vertical scanning period),
A signal that is the DC portion of video information (8 verage P
◇This APL
The signal (FIG. 4D) has exactly the same level information as the APL information based on the intermediate level (average level) E of the step in the input signal of FIG. 4A. Also this APL
The signal is clamped to a clamp voltage Vc.

The output of the low-pass filter 22 (FIG. 4D) is sent to the adder 2
3, it is added to the input signal that has passed through the bypass filter 21. The bypass filter 21 is a DC cant filter having a cutoff frequency of several tens of Hz, and removes the DC component of the signal, that is, the APL information.

Therefore, by adding the output of the bypass filter 21 and the APL output of the low-pass filter 22, the original signal is reproduced. In this case, since the APL signal is clamped to the clamp voltage VC, a step line sequential color difference signal clamped to the voltage Vc shown in FIG. 4E is obtained from the output of the adder 23.

In this way, in the clamp circuit of Fig. 3, the input is D
It is divided into a C component and an AC component, and with the DC component clamped to a desired potential, both are added to obtain a clamped output. D.C.
The minute clamp is achieved by a clamp operation that ignores step information and by extracting the DC component from the clamp output.

FIG. 5 shows a concrete circuit of the clamp circuit of FIG. 3, in which the input signal is injected into the clamp capacitor CI through an emitter follower stage consisting of a transistor T1 and a resistor R1. A transistor T2 is connected to the output of the clamp capacitor C1, which conducts to the level of the clamp voltage Vc in response to a clamp pulse corresponding to the pedestal section of the color difference input signal. When this transistor T2 becomes conductive,
01 is charged so that the level of the signal passing through the clamp capacitor C1 matches the voltage Vc, and thereby the signal passing through the capacitor C1 is clamped to the voltage Vc.

The output of capacitor C1 is connected to field effect transistor T3.
and a source follower consisting of a resistor R3 and a resistor R3 to a connection point A constituting an adder 24. on the other hand,
The emitter output of input transistor T1 is connected to capacitor C2.
is derived to the above-mentioned connection point A, and added at this connection point A.

Since the connection point A is grounded through the resistors R3 and R2 (R2<<R3), the bypass filter 21 shown in FIG. 6A is constituted by the capacitor C2 and the resistor R3.
The emitter output signal of transistor T1 passes through bypass filter 21 and is derived from adder 23. on the other hand,
Viewed from the output of the transistor T3, the connection point A is grounded via the capacitor C2 and the small resistor R1, so the resistance R3 and the capacitor C1 between the source of the transistor T3 and the point A are shown in FIG. 6B. A low-pass filter 22 is configured. Therefore, the source output signal of the transistor T3 passes through this low-pass filter 22 and the adder 23 (
Added to connection point A).

Note that the transfer function of the bypass filter 21 in FIG. 6A is , and the transfer function of the low-pass filter 22 in FIG. 6B is 1+TS, and the sum of these is as follows. In other words, the input/output transfer function in FIG. 5 is 1, and the frequency characteristic is flat. Therefore, even if the screen content suddenly changes, the sudden change in APL will be transmitted to the output through the AC system (bypass filter 21), so the clamped DC level will not fluctuate following the screen content. There isn't.

Furthermore, according to the clamp circuit of the embodiment, only the DC component in the signal is clamped, and the AC component is not clamped, so whisker-like clamp noise is superimposed on the output signal at the steep leading and trailing edges of the clamp pulse. There's nothing to do.

Effects of the Invention As described above, the present invention provides the first clamping of the input signal;
After clamping the second levels to the same potential,
The AC component of the input signal is extracted separately and the DC component is extracted.
Since the stepped signal is clamped to the above potential in addition to the voltage, it is possible to clamp the stepped signal with a very simple configuration.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of the recording system of an electronic switch camera to which the clamp circuit of the present invention can be applied, Fig. 2 is a waveform diagram of a stepped line sequential color difference signal and a waveform diagram of a conventional clamp pulse, and Fig. 3 4 is a block diagram showing an embodiment of the clamp circuit of the present invention, FIG. 4 is a waveform diagram of each part of FIG. 3, and FIG.
This figure is a specific circuit diagram of FIG. 3, and FIG. 6 is an equivalent circuit diagram of the bypass filter and low-pass filter included in FIG. 5. In addition, in the symbols used in the drawings, 20-・-111--・--・・--clamp circuit 21
−・・−・・−・・−・−Bypass filter 22・
−・−−m=−−・−・−Low pass filter 23...
−・−・・−・−−−−−・−Adder.

Claims (1)

[Claims] A circuit for clamping a stepped signal in which signal portions to be clamped at a predetermined period are alternately at first and second levels, wherein the first and second level portions to be clamped of the input signal are at the same potential, respectively. A circuit that clamps so that
A circuit that extracts the DC component of the clamp output, a circuit that extracts the AC component of the input signal, and the extracted DC component and A
A clamping circuit for a stepped signal, comprising a circuit for adding a C component.