JPS61292295A - Programmable read only memory and its writing method - Google Patents

Abstract

PURPOSE:To prevent the breakdown of a diode or a transistor which constitutes a memory cell and a capacitor for a non-writing memory cell by performing a writing using three or more potentials. CONSTITUTION:A programmable read-only memory connects a memory cell which consists of a capacitor C connected in series and a diode D or a transistor Q between each word line WL and each bit line BL respectively. When the writing is performed with breaking down the capacitor C, assuming that a selecting word line impression voltage is set as VrS, a selecting bit line impression voltage as VcS, a non-selecting word line impression voltage as VrN, a non-selecting bit line impression voltage VcN, a writing threshold voltage which breaks down the capacitor as VWT and the breakdown voltage of the diode or the transistor as VB, the writing can be performed by the selection of each voltage so as to satisfy expressions (1)-(4). Assuming that VcN=VrS, the writing condition can be satisfied on three voltage levels.

Description

[Detailed Description of the Invention] [Summary] BIC-PROM (Breakdown of In
5ulator for Cond-uction-P
rogramable Read 0nly Memo
ry), a high voltage is applied to the capacitor of the non-written memory cell, which prevents dielectric breakdown, and also prevents damage to the diode or transistor constituting the memory cell. We propose a BIC-PROM and its writing method that takes combinations into consideration.

[Industrial application field]

The present invention relates to a BIC-FROM that prevents destruction of diodes or transistors constituting memory cells and capacitors of non-written memory cells, and a writing method therefor.

BIC-PRO? l is a FROM that writes by applying a high voltage to the capacitor that makes up the memory cell to cause dielectric breakdown and make it conductive, and the writing time is several μs.
Since it is short as ec and logic can be configured using diodes or transistors even after writing, it is expected that it will be used in various information devices. ' However, in order to put BIC-FROM into practical use,
A high voltage is applied to the capacitor of the non-programmed memory cell,
It is necessary to devise a writing method and a writing circuit to prevent this from causing dielectric breakdown and to protect the diode or transistor constituting the memory cell from being destroyed.

[Problems to be solved by conventional technology and invention] BIC
- Since the structure of FROM is a new structure proposed by the applicant, a new writing method is also required.

If writing is performed only by a combination of high and low levels, as in conventional fuse ROMs, the diode or transistor that constitutes the memory cell will be destroyed, and dielectric breakdown of the capacitor of the non-written memory cell will occur. Since such cases may occur, it is necessary to devise ways to prevent these situations.

Means for Solving Problem c] The solution to the above problem is to connect a capacitor (C) and a diode (D) or a transistor (Q) in series between each word line (WL) and each bit line (BL). ) are connected to each other to form a memory cell array (1
1), and the following relational expression for the memory cell array: The voltage applied to the selected word line (75), the voltage applied to the selected bit line (BL) is VcS, and the voltage applied to the unselected word line (WL). VrN, unselected bit line (B
Assuming that the voltage applied to L) is VCN, the write threshold voltage that causes dielectric breakdown of the capacitor (C) is Vtm, and the breakdown voltage of the diode (D) or transistor ([1) is v8, VWt≦v1. -vcs,...(1)VB<
VrS vcN < VwT, ... (2) VB
<V, N<Vwt+ ...---(3) VB<
A programmable read-only memory according to the present invention including a driver' circuit that provides a voltage level VrS, V(5, VrNsVeN) satisfying VrNV(N<VPt, (4), and each word line (tag) and each Selecting a predetermined memory cell of a read-only memory formed by connecting memory cells each consisting of a capacitor (C) and a diode (D) or a transistor (Q) connected in series between the bit lines (BL), When writing by breaking down the capacitor (C), the voltage applied to the selected word line (WL) is set to 13, the voltage applied to the selected bit vA (BL) is set to VCS, and the voltage applied to the unselected word line (WL) is set to VCS. The voltage to be applied is VrN, the voltage to be applied to the unselected bit line (BL) is VcN, and the capacitor (C)
The write threshold voltage that causes dielectric breakdown is V. T1 If the breakdown voltage of the diode (D) or transistor (Q) is V, then VWt≦Vrs-■35.・・・・・・(1) V, l<
Vrs vCN< Vwt+...(2)V
R〈V r N <V WT + ・ ・ ・ ・
・ ・(3) V B < V rN V c, l <
This is achieved by the writing method according to the present invention, which performs writing while satisfying the relational expression (4).

In the above relational expression, VCM = Vrs.

If so, the write conditions can be satisfied with three voltage levels.

[Effect]

FIGS. 1(1) and 1(21(3)) are a block diagram of a BIC-FROM memory cell array and an equivalent circuit diagram of a memory cell, respectively, which explain the present invention in detail.

The memory cell in FIG. 1(2) shows an example in which a diode D and a capacitor C are connected in series, and the memory cell in FIG. 1(3) shows an example in which a transistor D and a capacitor C are connected in series.

In the figure, row O and row 1 are word lines W.
L, column O, column 1, column 2
constitutes the bit line BL, (Q0), (Q1), (Q2
), (10), (11), and (12) are memory cells connected between respective word lines and bit lines, D is a diode, and C is a capacitor.

Now, consider the case where a memory cell (Q0) is selected and data is written to it.

Assuming that the voltage applied to the memory cell during writing is ■ and the reverse breakdown voltage of diode D is ■8, in the selected cell, V,
≧■I,.

In non-selected cells, -V, l<V. T.

It is necessary that

The voltage of the selected row line is VrS, VCS the voltage of the selected column line, Set the voltage of the unselected row wire to ■0, ■ Unselect column line voltage.

Then, (1) In the selected cell, vwr≦■r 'J ” CS + ・・・・・・
(By selecting VrS, ■6 so that it becomes 11,
(2) In unselected cells, (2-1) In unselected cells on the selected row line, Vc
When N>0, Vn<VrS VcN<VWT, H+ ・(2
1'(2-2) In unselected cells on the selected column line, VB <VrN<VWT, HHHH+ ・(31(2
-3) In unselected cells on unselected row lines, Vll
<VrN VcN<VWT, ・ ・ ・(4
), by selecting VrS,V (e, ,V, ,V-), the diode D is not destroyed and the capacitor C does not suffer dielectric breakdown.Therefore, writing is not performed.

As described above, writing can be performed by selecting each voltage so as to satisfy the above four equations in which the four voltages are unknowns.

In the above relational expression, V (H=V rl If so, the write conditions can be satisfied with three voltage levels.

〔Example〕

FIG. 1(4) is a block diagram showing the configuration of a BIC-PROM according to the present invention.

In the figure, 11 is a BIC-PROM cell array.

Peripheral circuits include a row decoder 12, a column decoder 13, a read/write (R/W) amplifier 14, and an address register 15.
It becomes more.

The row decoder 12, column decoder 13, and (R/W) amplifier 14 are peripheral circuits including the dry eight circuit of the present invention.

Address register 15 receives an address signal from bus 16, performs program control, and sends its output to row decoder 13 and column decoder 14.

The (R/W) amplifier 14 is connected to the column line of the cell array 11 and exchanges data with the bus 16.

FIG. 2 is a block diagram showing the configuration of a microcontroller using BIC-FROM.

In the figure, 21 is a ROM, here BIC-PI?
Use OM.

22 is a central processing unit (CPII), 23 is a random access memory (IIAM), and 24 is an input/output device (Il
o), 25 is a bus.

FIG. 3 is a sectional view showing the structure of a BIC-PROM memory cell for explaining the present invention.

The illustrated memory cell is an example in which the diode and capacitor shown in FIG. 1(2) are connected in series.

In the figure, 1 is a semiconductor substrate, which is a silicon (Si) substrate, 2 is an n-type Si layer, 3 is a p-type 5iJiJ, 4 is an element isolation layer, which is a silicon dioxide (SiOz) layer, and 5 is a heavily doped polycrystalline layer. 6 is a dielectric layer of the capacitor, which is a SiO□ layer; and 7 is a wiring layer and electrode of the capacitor, which is an aluminum (Al) layer.

A diode composed of an n-type Si layer 2 and an n-type Si layer 3, and a capacitor composed of a poly5iFi5, a 5-layer 02 layer 6, and an AI layer 7 are connected in series and formed in an element isolation layer 4. Ru.

Now, the case of writing to a memory cell having such a structure will be described.

The SiO□ layer 6 is formed as thin as, for example, about 200 layers, and VPy=14V, for example, is applied between both electrodes of the capacitor (poly-Si layer 5 and 111 layer 7) to break down the SiO□ layer 6 and write and program. do.

The reverse breakdown voltage of the diode connected between the word line and the bit line after programming is relatively low, for example, VB=8V.

First, if VC, = OV, then from equation (1), 14≦V r S + next, V
If −s = 15V, then from equation (2), 1 <
VeN<23° From formula (3), 8<V r
u < 14° From formula (4), -8 < VrN-V
(N<14°, and writing is performed by selecting VrN and VCN that satisfy these conditions.

Furthermore, if vcN=vrs=15V, then from equation (4), 7<V, H<2g.

For example, if V, N = 8V, this voltage level, V-5 = VcN-15V, and VC, = OV.
The above conditions can be satisfied with one voltage level.

By using the above method, writing to BIC-FROM can be performed.

FIGS. 4(1) and 4(2) are circuit diagrams showing an example of a row and column driver that controls three or more potentials.

In the figure, 01 to Q1□ are MIS) transistors, and odd numbered Ql, Q3, Q3.07, Q7, Q, haha n
The channel type is represented by a thick line symbol, and the others are n-channel type.

Three types of voltage levels of 15.8.5v were used for the power supply, and each was distinguished by the symbol shown in the figure.

The human input signal for controlling each driver is obtained from a signal obtained by decoding the address from the bus and a data signal.

Figure 4 (1) is a row driver, Q, and 0□, Q3 and 0
4.0, I said. are each C? Configure the lOS inverter.

During writing, the R/W signal is at a low level "0", so 06 of n channel is off and 0. of n channel 2 is off. is turned on because a high level "1" is input to the input, and n-channel 07 is turned on because a low level "O" is input to the input.

In this state, the inverter composed of Q3 and Q4 outputs 15ν (connected to the row line) in response to the impark input signal “0” or “1” input from the decoder output. , 8V, and the voltage can be switched.

The inverter composed of Ql and 02, Q, and QIO converts the amplitude from the normal level of 5v to 15V.

At the time of continuous output, the R/- signal is at a high level "1", n-channel 06 is on, n-channel 07 is off, and p-channel Q is short-circuited between the gate and source and becomes a load transistor, turning off. The inverter consisting of 04 and 04 performs normal 5V level operation.

FIG. 4(2) shows a column driver, which is a CMOS impulse amplitude conversion circuit composed of Ql+ and 0.2.

“0” of the inverter input signal input from the decoder output,
In response to “1”, its output (connected to the row line) is 1
5V, OV, and the voltage can be switched.

〔Effect of the invention〕

As explained in detail above, according to the present invention, by using three or more potentials, dielectric breakdown of the capacitor of the non-written memory cell is caused without destroying the diode or transistor constituting the memory cell. It is possible to obtain a BIC-FROM without any problem and to write to it.

[Brief explanation of drawings]

FIGS. 1(1) and 21(3) are a block diagram of a BTC-FROM memory cell array and an equivalent circuit diagram of a memory cell, respectively, which explain the present invention in detail, and FIG. 1(4) is a BIC-FROM according to the present invention. FIG. 2 is a block diagram showing the structure of a microcontroller using BIC-FROM; FIG. 3 is a cross-sectional view showing the structure of a BIC-FROM memory cell to explain the present invention. 4(1) and (2) are circuit diagrams showing an example of a row and column driver that controls three or more potentials. In the figure, 11 is a BIC-FROM cell array, and 12 is a row decoder. , 13 is a column decoder, 14 is an R/- amplifier, 15 is an address register, 16 is a bus, the ridge is a word line consisting of row O and row I, and BL is column 0.
, column 1, column 2, (Q0), (Q1), (Q2), (10), (11),
(12) is a memory cell, D is a diode, Q is a transistor, C is a capacitor, 1 is a semiconductor substrate (Si substrate), 2 is an n-type S4 layer, 3 is a p-type Si layer, 4 is an element isolation layer and is a SiO□ layer , 5 is a heavily doped polySiF, 6 is a dielectric layer of the capacitor, which is a SiO□ layer, and 7 is a wiring layer and an electrode of the capacitor, which is a Δ1 layer. Beef L Shyness BL 阜 1 ■ 纂 2 (6);
1. = and ;7) Cross section [;3] Thatch 3 mouths

Claims (3)

[Claims] (1) Between each word line (WL) and each bit line (BL),
A memory cell array (11) is formed by connecting memory cells each consisting of a capacitor (C) and a diode (D) or a transistor (Q) connected in series, and a word line (WL) selected by the following relational expression is connected to the memory cell array (11). ), V_r_S is the voltage applied to the selected bit line (BL), V_r_N is the voltage applied to the unselected word line (WL), V_c_N is the voltage applied to the unselected bit line (BL), and V_c_N is the voltage applied to the unselected bit line (BL). The write threshold voltage that causes dielectric breakdown of (C) is V_
When the breakdown voltage of W_T, diode (D) or transistor (Q) is V_B, V_W_T≦V_r_S−V_c_S,...
1) −V_B<V_r_S−V_c_N<V_W_T,
...(2)-V_B<V_r_N<V_W_T,...
...(3)-V_B<V_r_N-V_c_N<V
_W_T. ...Voltage level V_r_ that satisfies (4)
A programmable read-only memory comprising: a driver circuit that provides S, V_c_S, V_r_N, and V_c_N. (2) Between each word line (WL) and each bit line (BL),
A predetermined memory cell of a read-only memory formed by connecting memory cells each consisting of a capacitor (C) and a diode (D) or a transistor (Q) connected in series is selected, and the capacitor (C) is dielectrically broken down. When writing, the voltage applied to the selected word line (WL) is V_r_S, the voltage applied to the selected bit line (BL) is V_c_S, the voltage applied to the unselected word line (WL) is V_r_N, and the unselected bit line is V_r_N. The voltage applied to (BL) is V_c_N, and the write threshold voltage that breaks down the capacitor (C) is V_
When the breakdown voltage of W_T, diode (D) or transistor (Q) is V_B, V_W_T≦V_r_S−V_c_S,...
1) −V_B<V_r_S−V_c_N<V_W_T,
...(2)-V_B<V_r_N<V_W_T,...
...(3)-V_B<V_r_N-V_c_N<V
_W_T. A method of writing to a programmable read-only memory characterized by performing writing while satisfying the relational expression (4). (3) In the above relational expression, V_c_N=V_r_S. 3. The method of writing in a programmable read-only memory according to claim 2, wherein: