JPS6129200B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a color signal demodulation circuit for a PAL color television receiver.

In the PAL color television system, the color subcarrier is simultaneously modulated using two color signals, each with a predetermined modulation axis, with the modulation axis for one of the color signals reversed by 180 degrees every horizontal scanning period. A color television signal containing a color signal and a burst signal whose phase is alternately reversed by ±45 degrees every horizontal scanning period is transmitted. In other words, the state of this carrier color signal is as shown in Figure 2, where on one line F _o = (B-Y) _o +j (R-Y) _o on the next line F _{o +1} = (B-Y) _o As expressed by ₊₁ −j(RY) _o+1 , for one color signal, for example, a red color difference signal, the phase of the color carrier wave is inverted line by line.

A conventional example will be explained using FIGS. 1 and 2. A PAL composite color television signal is supplied to a bandpass amplifier (hereinafter referred to as BPA) 1,
The carrier color signal and the burst signal are separated at BPA1. This signal is supplied as it is to the burst gate circuit 7 and one input terminal of the adder 2 and the subtracter 3, and is also supplied to the drive amplifier 4 of the 1H delay line 5 which delays it by one horizontal scanning period (hereinafter referred to as 1H).
is supplied to The drive amplifier 4 amplifies the carrier color signal and supplies it to the 1H delay line 5. The output signal of this 1H delay line 5 is passed through the preamplifier 6 to the adder 2,
The signal is amplified so as to have the same amplitude as the carrier color signal supplied to the subtracter 3, and is supplied to the other input terminals of the adder 2 and subtracter 3. Therefore, the successive lines L ₁ ,
The carrier color signals at L ₂ , L ₃ , L ₄ ... are F ₁ = (B-Y) ₁ +j (R-Y) ₁ F ₂ = (B-Y) ₂ -j (R-Y) ₂ F ₃ = (B-Y) ₃ + j (R-Y) ₃ F ₄ = (B-Y) ₄ -j (R-Y) ₄ Therefore, when line L ₂ arrives, adder 2 calculates (F ₁ + F ₂ )/2 is performed, and the subtracter 3 performs the calculation (F ₁ −F ₂ )/2,
Assuming that the color signals in adjacent lines are equal (B-
When the next line L ₃ arrives, the adder 2 and subtracter 3 produce the color signal (F ₂ +F ₃ )/2, (F ₂ −F _{3 )} . )/2 is performed, and color signals of (BY) and -j(RY) are obtained. That is, the first color signal from the subtracter 3, for example (R
-Y) The signal appears with phase inversion for each line.
The color signals from the adder 2 and the subtracter 3 are separately supplied to a demodulator 8 and a demodulator 9.

On the other hand, the burst signal separated by the burst gate circuit 7 is supplied to a subcarrier generation circuit (hereinafter referred to as APC circuit) 10, which generates a subcarrier signal phase-synchronized with the burst signal. This reference subcarrier signal (phase ₀ ) is sent to the demodulator 8 through a 90° phase shifter 1.
1 as a signal with a phase of ( ₀ - π/2), and the other demodulator 9 receives an APC
A subcarrier signal with a phase of ₀ from the circuit 10 and this which is phase inverted by a phase shifter 12 of 180° - ₀
The switching circuit 13
It is switched and supplied every 1H. Therefore, the demodulators 8 and 9 receive continuous (BY) and (RY) signals of the same polarity.

Since this circuit assumes that the color signals on adjacent lines are equal, the above-mentioned formulas F ₁ and F ₂ must be satisfied. If this formula is not satisfied, adder 2
The output includes not only the (B-Y) color difference signal but also the (R
-Y) Color difference signal components are also generated. Conversely, not only the (RY) color difference signal but also the (BY) color difference signal component is generated in the output of the subtracter 3, which causes color errors in the color signal demodulation circuit. Such a color error occurs when the above-mentioned formulas F ₁ and F ₂ are not satisfied, that is, when the delay time in the 1H delay line 5 varies with respect to temperature. For this reason, in the conventional method, the 1H delay line 5 was built into a constant temperature oven to reduce the deviation in delay time. However, with this method, it is difficult to completely compensate for delay time fluctuations.

The present invention detects the delay time fluctuation of the 1H delay circuit and controls the delay time of the carrier color signal.
It is an object of the present invention to provide a color signal demodulation circuit that does not cause the above color error.

An embodiment of the present invention will be described below based on the drawings. FIG. 3 is a specific configuration diagram of the 1H delay circuit which is the main part of the present invention, and FIGS. 4 and 5 are its time charts. First, the circuit operation in a state where no delay time fluctuation occurs in the 1H delay circuit 19 composed of the drive amplifier 4, 1H delay line 5, preamplifier 6, and variable delay circuit 14 will be described. The carrier color signal and burst signal separated by the BPA 1 are supplied to the drive amplifier 4, where they are amplified with high gain and sent to the 11H delay line 5.
to drive. Since the signal is attenuated by this 1H delay line 5, the output signal of the 1H delay line 5 is amplified by a preamplifier 6. This signal is supplied to a variable delay circuit 14 to control the delay time and output a carrier color signal and a burst signal. Here, the relationship between the input signal and the output signal of the 1H delay circuit 19 is that they have the same amplitude and are temporally different by 1H period. This 1H delayed carrier color signal and burst signal are supplied to the phase detector 16.

On the other hand, the carrier wave signal and burst signal separated by the aforementioned BPA1 are supplied to the burst gate circuit 7, where only the burst signal is separated and the APC circuit 1
0. This APC circuit 10 generates a subcarrier signal phase synchronized with the input burst signal. The phase ₀ of this subcarrier signal is inverted by a 180° phase shift circuit 12 to obtain a ₋₀ subcarrier signal, and this ₋₀ is passed through a 45° phase shift circuit 15 ( ₀ −5/4π). The subcarrier signal (Sc) of this phase is supplied to the phase detector 16.
Therefore, in the phase detector 16, as shown in FIG. The detected signal A shown in the figure is obtained at the output. This detection signal A becomes E ₀ ,0 voltage every 1H of the burst signal period. This detection signal A is sample-and-hold (hereinafter referred to as S&H).
The signal is supplied to the circuit 17. In this S&H circuit 17, the 0 voltage of the detection signal A is sampled and held using a sample pulse (SAMP) every 2H, converted to an optimal DC voltage via an inverting DC amplifier 18, and supplied to the variable delay circuit 14 as a control voltage. be done. The variable delay circuit 14 is controlled, for example, by controlling a variable capacitance diode. As for this control operation, as the DC voltage increases, the capacitance of the variable capacitance diode decreases, the delay time becomes shorter, and the phase lags.

Next, a case in which variation in delay time occurs in the 1H delay circuit 19 will be explained using FIGS. 3 and 5. 1H
A case will be explained in which the phase of the burst signal (n+2) in the delay circuit 19 is delayed by θ from the normal burst axis. In this case, the phase detector 16 outputs the burst signal (n
+2) and the subcarrier signal (Sc) is broken, and the detected signal A has a voltage of △e (here, △e is the detected voltage corresponding to the phase shift of the burst signal by θ). occurs. The voltage of this △e is S&
The signal is amplified by an inverting DC amplifier 18 via an H circuit 17. Therefore, the control voltage of the variable delay circuit 14 becomes lower than the optimum DC voltage of the variable delay circuit 14, and the capacitance of the variable capacitance diode of the variable delay circuit 14 increases, thereby increasing the delay time. That is, the phases of the burst signal and the carrier color signal are advanced by the above-mentioned θ and become in phase with the input signal of the regular 1H delay circuit 19. Here, a description of the case where the phase of the burst signal advances contrary to the above will be omitted, but the phase control operation is performed in the same manner.

In this way, variations in delay time occurring in the 1H delay circuit 19 can be completely compensated for by the closed circuit loop. As a result, only the (BY) and (RY) carrier color signal components are generated in the outputs of the adder circuit 2 and the subtracter circuit 3. That is, there is no crosstalk between each channel, and the demodulators 8 and 9 (B-
It is possible to demodulate the regular color difference signals of Y) and (RY).

In the above description, the phase of the subcarrier signal of the phase detector 16 is set to ( ₀ - 5/4π), but it goes without saying that this phase may also be set to ( ₀ + π/4).

According to the present invention, in the color signal demodulation circuit of PAL color television signals,
By adding a closed circuit loop that detects and controls variations in the delay time of the 1H delay circuit, variations can be completely compensated for. As a result, crosstalk between channels does not occur in the output of each carrier color signal demodulator, and only the (BY) and (RY) color difference signal components can be demodulated.

[Brief explanation of the drawing]

Figure 1 is a system diagram of an example of a demodulation circuit for a conventional PAL color television system, Figure 2 is a vector diagram of a PAL color television system, and Figure 3 is a system diagram of an example of a one horizontal period delay circuit according to the present invention. , FIG. 4 is a vector diagram and time chart for explaining FIG. 3, and FIG. 5 is a vector diagram and time chart for explaining delay time fluctuation. 5...1H delay line, 6...Preamplifier, 7...Burst gate circuit, 10...Subcarrier generation circuit, 12...
180° transfer circuit, 14...variable delay circuit, 15...45
゜Transfer circuit, 16... Phase detector, 17... Sample hold circuit, 18... Inverting DC amplifier, 19...
1H delay circuit.

Claims (1)

[Claims] 1. A chrominance signal demodulation circuit for a PAL color television receiver, which comprises a 1-horizontal-period delay line, an amplifier, and a variable delay circuit, and delays a burst signal and a carrier chrominance signal by 1-horizontal period; a subcarrier generation circuit that generates a subcarrier synchronized with the burst signal; a phase adjustment circuit that adjusts the phase of the subcarrier signal to the modulation axis of the input burst signal of the 2 m (m is an integer of 1 or more) line; a phase detector that detects the phase of the output signal of the horizontal period delay circuit using the subcarrier signal; and a phase detector that detects the phase of the output signal of the horizontal period delay circuit using the subcarrier signal;
A sample holding circuit that samples and holds a 2m-1 line detection signal with sample pulses at intervals of two horizontal periods, and means for controlling the delay time of the variable delay circuit based on the holding voltage of the sample holding circuit. A color signal demodulation circuit featuring: