JPS6129185B2 - - Google Patents

Info

Publication number
JPS6129185B2
JPS6129185B2 JP55145371A JP14537180A JPS6129185B2 JP S6129185 B2 JPS6129185 B2 JP S6129185B2 JP 55145371 A JP55145371 A JP 55145371A JP 14537180 A JP14537180 A JP 14537180A JP S6129185 B2 JPS6129185 B2 JP S6129185B2
Authority
JP
Japan
Prior art keywords
light receiving
receiving element
electrode
charge transfer
transfer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP55145371A
Other languages
Japanese (ja)
Other versions
JPS5768971A (en
Inventor
Toshihiro Furusawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP55145371A priority Critical patent/JPS5768971A/en
Publication of JPS5768971A publication Critical patent/JPS5768971A/en
Publication of JPS6129185B2 publication Critical patent/JPS6129185B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N1/00Scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission; Details thereof
    • H04N1/04Scanning arrangements, i.e. arrangements for the displacement of active reading or reproducing elements relative to the original or reproducing medium, or vice versa
    • H04N1/19Scanning arrangements, i.e. arrangements for the displacement of active reading or reproducing elements relative to the original or reproducing medium, or vice versa using multi-element arrays
    • H04N1/191Scanning arrangements, i.e. arrangements for the displacement of active reading or reproducing elements relative to the original or reproducing medium, or vice versa using multi-element arrays the array comprising a one-dimensional array, or a combination of one-dimensional arrays, or a substantially one-dimensional array, e.g. an array of staggered elements
    • H04N1/192Simultaneously or substantially simultaneously scanning picture elements on one main scanning line
    • H04N1/193Simultaneously or substantially simultaneously scanning picture elements on one main scanning line using electrically scanned linear arrays, e.g. linear CCD arrays

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Facsimile Heads (AREA)
  • Facsimile Scanning Arrangements (AREA)

Description

【発明の詳細な説明】 本発明は、一次元撮像装置に関する。[Detailed description of the invention] The present invention relates to a one-dimensional imaging device.

一次元撮像装置としては、一列に配列した複数
の受光素子を2本のCCD型電荷転送素子列に振
り分けて結合したデユアルチヤンネル型のものが
一般的である。
A one-dimensional imaging device is generally of a dual channel type in which a plurality of light receiving elements arranged in a line are distributed and combined into two CCD type charge transfer element rows.

第1図に従来のデユアルチヤンネル型の一次元
撮像装置を模式的に示す。同図に於て、1は入射
光を感知する為の一次元の光センサ部であつて、
入射光量に応じた電荷を発生する複数M個の受光
素子a,a…が一列に配列されている。2は該光
センサ部1の奇数番目の受光素子a1,a1…の
電荷を読み出し転送する為のM/2ビツトのCCD
型の第1転送レジスタ部であつて、クロツクパル
スφ1が印加される第1電極x1,x1…とクロ
ツクパルスφ2が印加される第2電極x2,x2
…とを備えており、各電極対x1,x2が1ビツ
ト単位を構成している。そして該第1電極x1,
x1…と上記各センサ部1の奇数番目の受光素子
a1,a1…とが結合されている。3は上記光セ
ンサ部1の偶数番目の受光素子a2,a2…の電
荷の読み出し転送する為のM/2ビツトのCCD型
の第2転送レジスタ部であつて、上記第1転送レ
ジスタ部2と同様に第1電極y1,y1…及び第
2電極y2,y2…を備えており、各電極対y
1,y2が1ビツト単位を構成している。そして
該第1電極y1,y1…と上記光センサ部1の偶
数番目の受光素子a2,a2…とが結合されてい
る。4,4は上記光センサ部1と第1、及び第2
転送レジスタ部2,3との間に設けられた移送ゲ
ートであり、上記光センサ部1の奇数番目の受光
素子a1,a1…から上記第1転送レジスタ部2
の第1電極x1,x1…位置へ、並びに上記光セ
ンサ部1の偶数番目の受光素子a2,a2…から
上記第2転送レジスタ部3の第1電極y1,y1
…位置へ、蓄積電荷を移送せしめる為のクロツク
パルスφGが引加される。
FIG. 1 schematically shows a conventional dual channel type one-dimensional imaging device. In the figure, 1 is a one-dimensional optical sensor section for sensing incident light,
A plurality of M light receiving elements a, a, . . . that generate charges according to the amount of incident light are arranged in a line. 2 is an M/2 bit CCD for reading and transferring the charge of the odd-numbered light receiving elements a1, a1... of the optical sensor section 1.
The first transfer register section of the transfer register includes first electrodes x1, x1, . . . to which a clock pulse φ1 is applied, and second electrodes x2, x2 to which a clock pulse φ2 is applied.
..., and each electrode pair x1, x2 constitutes one bit unit. and the first electrode x1,
x1... and the odd-numbered light receiving elements a1, a1... of each sensor section 1 are coupled. Reference numeral 3 denotes an M/2-bit CCD type second transfer register section for reading and transferring charges of the even-numbered light receiving elements a2, a2... of the optical sensor section 1, and is connected to the first transfer register section 2. Similarly, first electrodes y1, y1... and second electrodes y2, y2... are provided, and each electrode pair y
1 and y2 constitute one bit unit. The first electrodes y1, y1, . . . and the even-numbered light receiving elements a2, a2, . . . of the optical sensor section 1 are coupled. 4, 4 are the above-mentioned optical sensor part 1, the first, and the second
It is a transfer gate provided between the transfer register sections 2 and 3, and is a transfer gate provided between the odd-numbered light receiving elements a1, a1, . . . of the optical sensor section 1 to the first transfer register section 2.
from the even-numbered light receiving elements a2, a2... of the optical sensor section 1 to the first electrodes y1, y1 of the second transfer register section 3.
A clock pulse φG is applied to transfer the accumulated charge to the ... position.

第2図は第1図に示した従来装置に用いられる
クロツクパルスφ1,φ2,φGのタイミング図
である。図中のT1期間に於て光センサ間1の両
受光素子a1…,a2…で光電変換が為される。
T2期間に於ては、先のT1期間に両受光素子a
1…,a2…に蓄積された電荷を第1、及び第2
転換レジスタ部2,3に振り分け移送する為にク
ロツクパルスφGの正パルスPが印加される。更
に、このT2期間中に第1、第2転送レジスタ部
2,3に移送された蓄積電荷は、次にT1期間に
於て第1、及び第2転送レジスタ部2,3でクロ
ツクパルスφ1,φ2に依つて、全て外部へ転送
読み出しされる。
FIG. 2 is a timing diagram of clock pulses φ1, φ2, and φG used in the conventional device shown in FIG. During period T1 in the figure, photoelectric conversion is performed by both light receiving elements a1, a2, and so on between the optical sensors 1.
In the T2 period, both light-receiving elements a in the previous T1 period
1..., a2..., the charges accumulated in the first and second
A positive pulse P of the clock pulse φG is applied to transfer the data to the conversion register sections 2 and 3. Furthermore, the accumulated charges transferred to the first and second transfer register sections 2 and 3 during the T2 period are then transferred to the first and second transfer register sections 2 and 3 by clock pulses φ1 and φ2 during the T1 period. All data is transferred and read externally.

上述の従来の一次元撮像装置に於て、両転送レ
ジスタ部2,3の各電極x1…,x2…,y1
…,y2…の夫々を、説明の都合上第1図に一枚
構成で示したが、実際にはこの装置の厚み方向に
位置がずれた2段階の電極に依つて構成されてお
り、この転送レジスタ部2,3はすでに集積化の
限界にある。従つて、転送レジスタ2,3の電極
対x1,x2,y1,y2からなる1ビツト長に
は2個の受光素子a,aしか配置できない構成の
この装置全体を集積増設して単位長さ当りの受光
素子a,a…の数を増加する事には限界があつ
た。即ち斯る装置で得られる一次元画像の解像度
を増す事には限界があつた。
In the conventional one-dimensional imaging device described above, each electrode x1..., x2..., y1 of both transfer register sections 2, 3
..., y2... are each shown as a single-layer structure in Fig. 1 for convenience of explanation, but in reality, they are constructed by two stages of electrodes that are shifted in the thickness direction of this device. The transfer register sections 2 and 3 are already at the limit of integration. Therefore, this entire device, which has a configuration in which only two light-receiving elements a and a can be arranged in a 1-bit length consisting of the electrode pair x1, x2, y1, and y2 of the transfer registers 2 and 3, can be integrated and expanded to reduce the amount of light per unit length. There is a limit to increasing the number of light receiving elements a, a, . . . . That is, there is a limit to increasing the resolution of one-dimensional images obtained with such an apparatus.

本発明は斯る点に鑑みて為されたものであり、
転送レジスタ部2,3の1ビツト長に対して4個
の受光素子a,aを配置できるようにし、この両
転送レジスタ部2,3の移動方式を工夫する事に
移つてセンサ部1の受光素子a,a…の単位長さ
当りの数が倍増した一次元撮像装置を提供するも
のである。
The present invention has been made in view of these points,
By making it possible to arrange four light-receiving elements a and a for one bit length of the transfer register sections 2 and 3, and devising a movement method for both transfer register sections 2 and 3, the light reception of the sensor section 1 is The present invention provides a one-dimensional imaging device in which the number of elements a, a, . . . per unit length is doubled.

第3図に本発明の一次元撮像装置を模式的に示
す。同図に於て、11は第1図に示した従来装置
と同じく光センサ部であるが、この光センサ部1
1に一次元的に配列された受光素子b,b…の単
位長さ当りの数が第1図に示した装置の受光素子
a,a…の数の2倍となつている。即ち、転送レ
ジスタ部2,3の各ビツト長に対して4個の受光
素子a,a,a,a…が配列されている。12,
13も又、第1図の従来装置と同じく、第1転送
レジスタ部、第2転送レジスタ部であるが、第1
転送レジスタ部12はクロツクパルスφ1′が印
加される第1電極x1,x1…と上記光センサ部
11の4m+1番目(mは正整数)の第1受光素
子b1,b1…とが移送ゲート14を介して結合
されると共にクロツクパルスφ2′が印加される
第2電極x2,x2…と上記光センサ部11の
4m+3番目の第3受光素子b3,b3…とが移
送ゲート14を介して結合される構成となつてい
る。又、第2転送レジスタ部13も同様に第1電
極y1,y1…と4m+2番目の第2受光素子b
2,b2…とが移送ゲート14を介して結合され
ると共に第2電極y2,y2…と4m番目の第4
受光素子b4,b4…とが移送ゲート14を介し
て結合される構成となつている。14,14は基
本的に第1図の従来装置と同様の移送ゲートであ
り、上記受光素子b1,b1…から上記第1転送
レジスタ部12の第1電極x1,x1…へ並びに
上記受光素子b2,b2…から上記第2転送レジ
スタ部13の第1電極y1,y1…へ蓄積電荷を
移送せしめる為の正パルスP1と、上記受光素子
b3…から上記第1転送レジスタ部12の第2電
極x2…へ並びに上記受光素子b4…から上記第
2転送レジスタ部13の第2電極y2…へ蓄積電
荷を移送せしめる為の正パルスP2と、を交互に
含むクロツクパルスφG′が印加される。
FIG. 3 schematically shows a one-dimensional imaging device of the present invention. In the figure, reference numeral 11 denotes an optical sensor section similar to the conventional device shown in FIG.
The number of light receiving elements b, b, . . . arranged one-dimensionally per unit length is twice the number of light receiving elements a, a, . That is, four light receiving elements a, a, a, a, . . . are arranged for each bit length of the transfer register sections 2, 3. 12,
13 is also a first transfer register section and a second transfer register section, as in the conventional device shown in FIG.
In the transfer register section 12, the first electrodes x1, x1, . and the second electrodes x2, x2... to which the clock pulse φ2' is applied and the second electrodes x2, x2... of the optical sensor section 11
4m+3rd third light receiving elements b3, b3 . . . are connected via a transfer gate 14. Similarly, the second transfer register section 13 also has the first electrodes y1, y1... and the 4m+2nd second light receiving element b.
2, b2... are coupled via the transfer gate 14, and the second electrodes y2, y2... and the 4mth fourth electrode
The light receiving elements b4, b4, . . . are connected via a transfer gate 14. Reference numerals 14, 14 are transfer gates basically similar to those in the conventional device shown in FIG. , b2 . . . to the first electrodes y1, y1 . . . and a positive pulse P2 for transferring the accumulated charge from the light receiving element b4 to the second electrode y2 of the second transfer register section 13.

第4図は、上述の本発明装置に用いられるクロ
ツクパルスφ1′,φ2′,φG′のタイミング図
である。同図に於て、クロツクパルスφG′にON
状態の正パルスP1が現れた時には、クロツクパ
ルスφ1′がON状態であり、クロツクパルスφ
2′がOFF状態となつているので、光センサ部1
1の複数の受光素子b,b…の内第1、及び第2
受光素子b1…,b2…の蓄積電荷が開成状態の
移送ゲート14,14を介して夫々第1及び第2
転送レジスタ部12,13の電荷蓄積可能となつ
た第1電極x1…,y1…に導入される。又、ク
ロツクパルスφG′にON状態の正パルスP2が現わ
れた時には、クロツクパルスφ1′がOFF状態で
あり、クロツクパルスφ2′がON状態となつてい
るもので、上記複数の受光素子b,b…の内、第
3、及び第4受光素子b3…,b4…の蓄積電荷
が開成状態の移送ゲート14,14を介して夫々
第1、及び第2転送レジスタ部12,13の電荷
蓄積可能となつた第2電極x2…,y2…に導入
される。一方、T1′期間に於ては、光センサ部
11の全ての受光素子b,b…で光電変換が為さ
れると共に、第1、及び第2転送レジスタ部1
2,13ではこのT1′期間の直前の正パルスP
1がクロツクパルスφG′に現われるT4′期間に
第1、及び第2受光素子b1,b2…から移送さ
れた蓄積電荷の外部への転送読み出しがクロツク
パルスφ1′,φ2′に依つて行なわれる。又、T
3′期間に於ては、光センサ部11の全ての受光
素子b,b…でT1′期間と同様の光電変換が為
されると共に、第1、及び第2転送レジスタ部1
2,13ではこのT3′期間の直前の正パルスP
2がクロツクパルスφG′に現われるT2′期間に
第3、第4受光素子b3…,b4…から移送され
た蓄積電荷の外部への読み出しがクロツクパルス
φ1′,φ2′に依つて行なわれる。従つて、第1
転送レジスタ部12と、第2転送レジスタ部13
と、からの電荷信号を重ね合わせて得られる信号
を、更にT1′期間分と、T2′期間分と、を重ね
合せる事に依つて、光センサ部11の一列分の画
像信号となる。
FIG. 4 is a timing diagram of clock pulses φ1', φ2', and φG' used in the above-described device of the present invention. In the same figure, the clock pulse φG′ is turned on.
When the positive pulse P1 of the state appears, the clock pulse φ1' is in the ON state, and the clock pulse φ
2' is in the OFF state, so the optical sensor section 1
The first and second of the plurality of light receiving elements b, b...
The charges accumulated in the light receiving elements b1..., b2... are transferred to the first and second gates through the open transfer gates 14, 14, respectively.
The first electrodes x1, y1, etc. of the transfer register sections 12, 13 are introduced to allow charge accumulation. Also, when the positive pulse P2 in the ON state appears in the clock pulse φG', the clock pulse φ1' is in the OFF state and the clock pulse φ2' is in the ON state, and one of the plurality of light receiving elements b, b... , the third and fourth light receiving elements b3..., b4... can be stored in the first and second transfer register sections 12, 13, respectively, via the open transfer gates 14, 14. It is introduced into two electrodes x2..., y2.... On the other hand, in the T1' period, photoelectric conversion is performed in all the light receiving elements b, b... of the optical sensor section 11, and the first and second transfer register sections 1
2 and 13, the positive pulse P immediately before this T1' period
During the T4' period in which 1 appears on the clock pulse φG', the accumulated charges transferred from the first and second light receiving elements b1, b2, . Also, T
In the 3' period, photoelectric conversion similar to that in the T1' period is performed in all the light receiving elements b, b... of the optical sensor section 11, and the first and second transfer register sections 1
2 and 13, the positive pulse P immediately before this T3' period
During the T2' period in which 2 appears on the clock pulse φG', the stored charges transferred from the third and fourth light receiving elements b3, b4, . . . are read out to the outside by the clock pulses φ1', φ2'. Therefore, the first
Transfer register section 12 and second transfer register section 13
By further superimposing the signal obtained by superimposing the charge signals from and for the T1' period and the T2' period, an image signal for one row of the photosensor section 11 is obtained.

本発明の一次元撮像装置は、以上の説明から明
らかな如く、第1の電荷転送素子列の第1電極に
移送ゲートを介して結合された第1の受光素子
と、第2の電荷転送素子列の第1電極に移送ゲー
トを介して結合された第2の受光素子と、第1の
電荷転送素子列の第2電極に移送ゲートを介して
結合された第3の受光素子と、第2の電荷転送素
子列の第2電極に移送ゲートを介して結合された
第4の受光素子とからなる4素子が電荷転送素子
列のビツト周期と対応して周期的に配列され、第
1の受光素子群と第2の受光素子群とに貯えられ
た電荷を読み出し転送する前動作と、第3の受光
素子群と第4の受光素子群とに貯えられた電荷を
読み出し転送する後動作と、の2動作で一列の撮
像動作を完了するものであるので、電荷転送素子
列の1ビツトに対応して2個の受光素子しか配列
できなかつた従来装置に比べその1ビツトに対応
して4個の受光素子を配列する事が可能となる。
即ち、この電荷転送素子列を集積化したり増設す
る事なく単位長さ当りの受光素子数を倍増する事
ができる。従つて、本発明装置に依れば解像度の
優れた一次元画像を得る事ができる。
As is clear from the above description, the one-dimensional imaging device of the present invention includes a first light receiving element coupled to a first electrode of a first charge transfer element array via a transfer gate, and a second charge transfer element. a second light receiving element coupled to a first electrode of the column via a transfer gate; a third light receiving element coupled to a second electrode of the first charge transfer element column via a transfer gate; A fourth light-receiving element is coupled to a second electrode of a charge transfer element array through a transfer gate, and four elements are arranged periodically corresponding to the bit period of the charge transfer element array, and the first light-receiving element a pre-operation of reading and transferring the charges stored in the element group and the second light-receiving element group; a post-operation of reading and transferring the charges stored in the third light-receiving element group and the fourth light-receiving element group; Since the imaging operation for one row is completed with the following two operations, compared to the conventional device which could only arrange two light receiving elements corresponding to one bit of the charge transfer element row, four light receiving elements can be arranged corresponding to one bit of the charge transfer element row. It becomes possible to arrange the light-receiving elements.
That is, the number of light receiving elements per unit length can be doubled without integrating or increasing the number of charge transfer element arrays. Therefore, according to the apparatus of the present invention, a one-dimensional image with excellent resolution can be obtained.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来の一次元撮像装置を示す模式図、
第2図は従来の一次元撮像装置を用いられるクロ
ツクパルスのタイミング図、第3図は本発明の一
次元撮像装置を示す模式図、第4図は本発明の一
次元撮像装置に用いられるクロツクパルスのタイ
ミング図、である。 1,11……光センサ部、2,12……第1転
送レジスタ部、3,13……第2転送レジスタ
部、4,14……移送ゲート、b1,b2,b
3,b4……第1、第2、第3、第4受光素子、
x1,y1……第1電極、x2,y2……第2電
極。
FIG. 1 is a schematic diagram showing a conventional one-dimensional imaging device.
FIG. 2 is a timing diagram of clock pulses used in a conventional one-dimensional imaging device, FIG. 3 is a schematic diagram showing the one-dimensional imaging device of the present invention, and FIG. 4 is a timing diagram of clock pulses used in the one-dimensional imaging device of the present invention. This is a timing diagram. 1, 11... Optical sensor section, 2, 12... First transfer register section, 3, 13... Second transfer register section, 4, 14... Transfer gate, b1, b2, b
3, b4...first, second, third, fourth light receiving elements,
x1, y1...first electrode, x2, y2...second electrode.

Claims (1)

【特許請求の範囲】 1 一次元に配列された受光素子列と、該受光素
子列の両側辺に沿つて設けられた複数ビツト構成
の第1及び第2の電荷転送素子列と、両電荷転送
素子列と受光素子列間に設けられ一体的に動作す
る2本の移送ゲートとからなる一次元撮像装置に
於て、該両電荷転送素子列の夫々にはクロツクパ
ルスが相補的に印加され交互に電荷蓄積可能状態
となる第1電極と第2電極とが交互に配置され1
組の電極対が1ビツトを構成し、上記受光素子列
は、上記第1の電荷転送素子列の第1電極に上記
移送ゲートを介して結合された第1の受光素子
と、上記第2の電荷転送素子列の第1電極に上記
移送ゲートを介して結合された第2の受光素子
と、上記第1の電荷転送素子列の第2電極に上記
移送ゲートを介して結合された第3の受光素子
と、上記第2の電荷転送素子列の第2電極に上記
移送ゲートを介して結合された第4の受光素子と
からなる4素子が上記両電荷移送素子列のビツト
周期と対応して周期的に配列して構成され、 上記第1及び第2の電荷転送素子列の第1の電
極を電荷蓄積可能状態として上記移送ゲートを開
成せしめる事により、第1の受光素子群と第2の
受光素子群とに貯えられた電荷を導入し、これを
転送出力する前動作と、上記第1及び第2の電荷
移送素子列の第2の電極を電荷蓄積可能状態とし
て上記移送ゲートを開成せしめる事により、第3
の受光素子群と第4の受光素子群とに貯えられた
電荷を導入し、これを転送出力する後動作との2
動作で一列の撮像動作を完了する事を特徴とした
一次元撮像装置。
[Scope of Claims] 1. A one-dimensional array of light receiving elements, first and second charge transfer element arrays having a plurality of bits provided along both sides of the light receiving element array, and both charge transfer elements. In a one-dimensional imaging device consisting of two transfer gates provided between an element row and a light-receiving element row and operating integrally, clock pulses are applied complementary to each of the two charge transfer element rows and are alternately applied. The first electrode and the second electrode, which are in a state where charge can be accumulated, are arranged alternately.
A set of electrode pairs constitutes one bit, and the light receiving element array includes a first light receiving element coupled to a first electrode of the first charge transfer element array via the transfer gate, and a first light receiving element coupled to the first electrode of the first charge transfer element array via the transfer gate; a second light receiving element coupled to a first electrode of the charge transfer element array via the transfer gate; and a third light receiving element coupled to a second electrode of the first charge transfer element array via the transfer gate. Four elements, each consisting of a light receiving element and a fourth light receiving element coupled to the second electrode of the second charge transfer element row via the transfer gate, correspond to the bit period of both charge transfer element rows. By opening the transfer gate with the first electrodes of the first and second charge transfer element arrays in a charge storage enabled state, the first light receiving element group and the second light receiving element array are arranged periodically. A pre-operation for introducing charges stored in the light receiving element group and transferring and outputting them, and opening the transfer gate by setting the second electrodes of the first and second charge transfer element arrays in a state in which charges can be accumulated. Due to circumstances, the third
2. A post-operation in which the charges stored in the photodetector group and the fourth photodetector group are transferred and output.
A one-dimensional imaging device characterized by completing one row of imaging operations in one motion.
JP55145371A 1980-10-16 1980-10-16 Primary dimension image sensor Granted JPS5768971A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55145371A JPS5768971A (en) 1980-10-16 1980-10-16 Primary dimension image sensor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55145371A JPS5768971A (en) 1980-10-16 1980-10-16 Primary dimension image sensor

Publications (2)

Publication Number Publication Date
JPS5768971A JPS5768971A (en) 1982-04-27
JPS6129185B2 true JPS6129185B2 (en) 1986-07-04

Family

ID=15383668

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55145371A Granted JPS5768971A (en) 1980-10-16 1980-10-16 Primary dimension image sensor

Country Status (1)

Country Link
JP (1) JPS5768971A (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2539937B1 (en) * 1983-01-21 1986-11-07 Thomson Csf CHARGE TRANSFER PHOTOSENSITIVE DEVICE
JPS59190782A (en) * 1983-04-14 1984-10-29 Tech Res & Dev Inst Of Japan Def Agency Driving method of solid-state image pickup device

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5316529A (en) * 1976-07-30 1978-02-15 Oki Electric Ind Co Ltd Pattern input unit
JPS5454534A (en) * 1977-10-11 1979-04-28 Fujitsu Ltd Plurality line sensor

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5316529A (en) * 1976-07-30 1978-02-15 Oki Electric Ind Co Ltd Pattern input unit
JPS5454534A (en) * 1977-10-11 1979-04-28 Fujitsu Ltd Plurality line sensor

Also Published As

Publication number Publication date
JPS5768971A (en) 1982-04-27

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