JPS61288565A - Halftone digital picture processing device - Google Patents

Abstract

PURPOSE:To obtain the result of processing with most excellent gradation to a data not including edge information and with high resolution to a character or a line drawing including the edge information by using plural threshold matrixes having different threshold arrangement patterns so as to switch the arrangement pattern in response to the presence of edge information. CONSTITUTION:A threshold table used at each unit area of gradation processing consists of plural kinds of tables having different arrangement patterns and whether or not the edge information is included in an input data is discriminated at each unit area of gradation processing and the type of utilized arrangement pattern is switched in response to the presence of the edge information. That is, the 1st processing system is provided with an 8X8 averaging circuit 150 and a density pattern processing circuit 153. The gradation processing by the density pattern method is applied in this processing system. An edge emphasis circuit 152 in the 2nd gradation processing system is a 2-dimension space filter and amplifies the density change of the data of the area to emphasize the edge when the input data has a density level change, that is, when edge information exists.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of the Invention] The present invention relates to a halftone digital image processing device, and in particular to a halftone digital image processing device that expresses halftones using an area gradation method.
Related to improving the resolution of information such as line drawings.

[Prior Art] When recording an image using the dot matrix method, a normal recording device can adjust the density level of each dot in only four levels at most. However, for example, digital color copying machines generally require 64 levels of gradation expression for each basic recording color such as yellow (Y), magenta (M), cyan (C), and black (BK). There is.

When performing such multi-tone expression, conventionally, a relatively large dot area consisting of multiple dots (for example, 8 x 8) is used as a unit of gradation processing area, and the number of recording dots and the number of recording dots are calculated for each dot area. The density level of each gradation processing area is expressed by adjusting the number of non-recorded dots. This type of halftone expression method is called area gradation method.

However, if, for example, an 8 x 8 dot area is used as the unit of gradation processing, ■ 1/
The recording resolution decreases to 8. For example, in an image such as a photograph, even if the resolution is low, if the intermediate tone, that is, the density of each pixel is accurately expressed, the recording quality will be highly evaluated. However, in the case of line drawings and characters, a decrease in resolution immediately leads to a decrease in recording quality.

Generally, for images that include line drawings or text, black/white, etc.
In many cases, gradation expression is not necessary. Therefore, it has been proposed to switch the single-picture information processing to either binary processing or gradation processing depending on the content of the image to be handled. However, when dealing with multicolor images, for example, it is necessary to treat each pixel information of characters and line drawings as halftone data in order to reproduce each color. Furthermore, even in black/white recording, there are cases where it is desired to express characters and line drawings in intermediate tones such as gray.

[Object of the Invention] An object of the present invention is to improve the resolution of an image when gradation is expressed using the area gradation method.

[Structure of the Invention] In order to achieve the above object, the present invention improves the resolution of each unit area of gradation processing made up of a plurality of pixels. In order to achieve this, in the present invention, the threshold table used for each unit area of gradation processing is configured with a plurality of types of threshold values having different arrangement patterns, and each unit area of gradation processing is First, it is determined whether edge information is included in the input data, and the type of array pattern to be used is switched depending on the presence or absence of edge information.

Gradation expression using the area gradation method can be roughly divided into two types: the density pattern method and the dither method. In the density pattern method, the average density within a predetermined processing area (for example, 8 x 8) is calculated, and the result is compared with each point in a threshold table in which thresholds are determined for each pixel in the processing area in advance. Based on the result, binary data of rlJ or rOJ is generated for each pixel.

In the dither method, the input data of each pixel is directly compared one-on-one with that of the corresponding position in the threshold table, and binary data of rlJ or "0" is generated based on the result.

The threshold value is for an 8x8 matrix table.

Generally Os 1+ 2s 4t...62 and 63
The 64 types of thresholds are arranged at 64 pixel positions, and the order in which the thresholds are arranged, that is, the pattern types, can be roughly divided into two types: systematic patterns and random patterns. The one shown in FIG. 10e is a typical random pattern, which is called the Bayer (BAT/ER) type.

The one shown in FIG. 10e is representative of one structural pattern, which is generally called a spiral pattern.

Here, one example will be explained. Figure 10a shows 8
A certain original image corresponding to a pixel area of x8 is shown. In this, the hunting portion has a density of 44, and the other portions have a density of 14. In other words, it shows a portion where the density changes rapidly with the diagonal edge as the boundary. FIG. 10b shows density data for each pixel read from the image of FIG. 10a.

Figure 10d shows the result of processing the density data in Figure 10b by the dithering method using the random pattern shown in Figure 10C, and Figure 10f shows the result of processing the same density data in Figure 10e.
The result of processing by the dither method using the systematic pattern shown in the figure is shown, and FIG. 10g shows the result of processing by the density pattern method using the systematic pattern of FIG. 108.

The hatched pixels are data “l” (recorded pixels)
Show.

Other pixels indicate data "0" (non-recorded pixels).

Comparing the results of each process, the average density, that is, the gradation, is 31.5 for the input data (Figure 10b);
Figure 10d is 33, Figure 10f is 32, Figure 10g is 3
1, it can be seen that the systematic pattern is superior to the random pattern as the threshold arrangement pattern.6 Next, if we focus on the arrangement of "1" and "0" in the 8x8 matrix, In FIG. 10d, it can be seen that the distribution of "1" and "0" is biased with the edge of the original data as the boundary. In other words, information other than the concentration in the 8×8 matrix,
In other words, information about neighboring countries of the original data is reflected in the output data. However, in FIGS. 10f and 10g, according to the threshold array shape of the threshold table,
It can be seen that "1" is distributed in the center, and information about neighboring countries in the original data hardly appears in the output data. In other words, it can be seen that random patterns are superior to systematic patterns in terms of resolution.

Therefore, by using multiple types of patterns, such as using random patterns for images where resolution is important and using systematic patterns for images where gradation is important, it is possible to improve resolution. Both requirements for gradation can be met. For images where resolution is important, for example 1st
Since edge information as shown in Figure 0a is included, by switching the pattern type depending on the presence or absence of this image edge, a preferred pattern type can be automatically selected.

As mentioned above, even when using random patterns,
Since the gradation difference between the original data and the output data is not so large, for example, even if character information is input as a halftone, the gradation will not change significantly. In other words, even if the text information is in multiple colors, for example, the colors can be recorded accurately, and since the resolution is high, the recorded characters can be easily identified.

By the way, in identifying a single character or line drawing, the edge area of the information plays an important role. In other words, if the loss of information in the edge region is prevented, the resolution can be substantially improved.6For example, for the image in FIG.
As shown in Figure 1a, "1" and "0" are placed in the pixels at both ends of the edge area.

Then, for the remaining pixel positions, if we place 19 "1"s below the edges and record 5 "1s" above the edges, the average density of the entire image will be 32, which is equal to the original data. , and the average density of each region on both ends of the edge also becomes close to the original data.

Edge regions can be extracted by spatial filters.

For example, assuming a local area of 3×3 pixels adjacent to each other, each pixel position A, B, C, D, E, F.

The weighting of G, H, and I as shown in each pattern in FIG. 12, and the weighting of each density data corresponding to these nine pixels and outputting the sum of the data, are equivalent to the function of a filter. The characteristics of this type of spatial filter are determined depending on the weighting of each pixel. The filter pattern PA shown in FIG.

PB, PC, FD and PE function as edge extraction filters, and other patterns PF, PG and PH.

PT and PJ function as edge enhancement filters.

FIG. 11b shows the data shown in FIG. 10b as a pattern FD.
Figure 1.id shows the result of processing the data shown in Figure .tob using the edge enhancement filter of pattern PI.

However, in order to process the data at the edge of the 8×8 pixels in FIG. 10b, the results are obtained assuming that the density outside the data at the edge is the same as the data at the edge. In FIG. 11d, negative processing results are replaced with 0, and processing results of 64 or more are replaced with 63.

In Figure 1ie, the data in Figure 11b is combined with a fixed threshold value 32.
Shows the results of binarization. Referring to FIG. 1ie, it can be seen that the edge information of the image is extracted. however,
Since the average density (the number of hatched pixels) in FIG. 11e is 9, it is far different from the original data of 32, and as it is, it cannot be used in terms of gradation.

Therefore, when the result of dithering using the random pattern threshold table (FIG. 10d) and the result of FIG. 11C are computed, the result is as shown in FIG. 11g. According to this, the error in the average gradation is improved, and the edge information is reliably reflected in the processing result.

Fig. 1ie shows the data obtained by dithering the data in Fig. 1id using the threshold table (random pattern) shown in Fig. 10c and binarizing it, and Fig. 11f shows the data.

The data in Figure 1id is converted to the threshold table in Figure 10e (
This shows data that has been dithered and binarized using a systematic pattern. Referring to Figures 1ie and 11f, the original data (first
It can be seen that the information on the concentration distribution in Figure 0b) is reflected to a relatively large extent. In other words, the edge enhancement processing improves the resolution in the unit gradation processing area (8×8 pixels). However, when comparing the average density, that is, the gradation, the 11th
The figure is 32. Since the value shown in FIG. 11f is 25, it is preferable to use a random pattern as the threshold value table.

FIG. 11h shows a pattern in which the matrix size of the threshold table is different from that described above. In this,
The size of the table is 4×4, and a threshold value of 16 $fA is arranged in a random pattern in each of 16 pixel areas. In addition, in FIG. 11h, four threshold tables are shown arranged consecutively in order to correspond to an 8×8 pixel area.

The result of dithering the data in FIG. 10b using the threshold value table in FIG. 11h and the logical sum of the contents in FIG. 11c is shown in FIG. 1Li. According to this, it can be seen that the edge information of the original data is sufficiently reflected in the processing result, and the average density within the 8×8 pixels is 33, indicating that the gradation is excellent.

Based on the above considerations, it is possible to achieve both accurate gradation expression and high resolution at the same time by selecting a preferable threshold table or by combining multiple processing results. I understand.

[Example〕 Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 1 shows the structural components of a mechanical section of one type of digital color copying machine embodying the present invention, and FIG. 2 shows an outline of the configuration of the electrical section.

First, referring to FIG. 1, an original l is placed on a platen (contact glass) 2, and a fluorescent lamp 31+3 for illuminating the original is placed on a platen (contact glass) 2.
2, the reflected light is illuminated by a movable first mirror 41. It is reflected by the second mirror 42 and the third mirror 43 and passes through the imaging lens 5.

Enters the dichroic prism 6, where the three wavelengths of light, red (R), green (G) and blue (B)
It is spectrally separated into The separated light is captured by a solid-state image sensor
incident on OD 7 r, 7 g and 7b, respectively. That is, red light enters C0D7r, green light enters CCD7g, and blue light enters C0D7b.

The fluorescent lamps 31 and 32 and the first mirror 41 are connected to the first carriage 8.
The second mirror 42 and the third mirror 43 are mounted on the second carriage 9, and by moving the second carriage 9 at half the speed of the first carriage 8, the original 1
The optical path length from to COD is kept constant, and the first and second carriages are scanned from right to left when reading the original image. The first carriage 8 is connected to a carriage drive wire 12 that is wound around a carriage drive pulley 11 fixed to the shaft of a carriage drive motor IO, and the wire 12 is wound around a movable pulley (not shown) on a second carriage 9. As a result, by rotating the motor 10 in the forward and reverse directions,
The first carriage 8 and the second carriage move forward (original image reading and scanning) and backward (return), and the second carriage 9 moves at 1/2 the speed of the first carriage 8.

When the first carriage 8 is at the home position shown in FIG. 1, the first carriage 8 is detected by the home position sensor 39, which is a reflective boot sensor. This detection mode is shown in FIG. When the first carriage 8 is driven to the right during exposure scanning and moves away from the home position, the sensor 39 does not receive light (carriage non-detection). When the first carriage 8 returns to the home position, the sensor 39 receives light ( (carriage detection), and the carriage 8 is stopped when the state changes from non-light reception to light reception.

Referring to FIG. 2, the outputs of the CCDs 7r, 7g*7b are analog/digital converted and subjected to necessary processing in the image processing unit 100.

Recorded color information: black (BK), yellow (Y),
The signals are converted into binary signals for magenta (M) and cyan (C) recording activation. The laser driver 112bk is responsible for the binary signal.

112y, 112m and 112c, and each laser driver outputs a semiconductor laser 113bk, 113y,
By energizing 113m and 113c, laser light modulated with a recording color signal (binarized signal) is emitted.

Referring again to FIG. The emitted laser beams are reflected by rotating polygon mirrors 13bk, 13y, 13m and 13c, respectively, and are then reflected by f-θ lenses 14bk, 14y.
.

After passing through 14m and 14c, the fourth mirror 15bk.

15yt15m and 15c and 5th mirror 16bk.

Reflected by 15y, 15m and 16c, polygonal mirror surface tilt correction cylindrical lens 17 bk t 17 y
- Via 17m and 17c, photosensitive drum 18bk.

113y, 18m and 18c are imaged and irradiated.

Rotating polygon mirrors 13bk, 13y, 13m and 1
3c is a polygon mirror drive motor 4 lbk, 41y, 4
The motors are fixed to rotating shafts 1m and 41c, and each motor rotates at a constant speed to rotate the polygon mirror at a constant speed.

As the polygon mirror rotates, the laser beam is scanned in a direction perpendicular to the rotation direction (clockwise) of the photoreceptor drum, that is, in a direction along the drum axis.

The laser scanning system of the cyan color recording apparatus is shown in detail in FIG. 4, where 43c is a semiconductor laser. A sensor 44c made of a photoelectric conversion element is arranged to receive the laser beam at one end of the laser scan (double-dot chain line) in the direction along the axis of the photoreceptor drum 18c, and this sensor 44c detects the laser beam. The starting point of one line scan is detected at the time when the detection changes from detection to non-detection. That is, the laser light detection signal (pulse) from the sensor 44c is processed as a line synchronization pulse for laser scanning. Magenta recording device i! .

The configuration of the yellow recording device and the black recording device is also the fourth one.
The configuration is exactly the same as that of the cyan recording apparatus shown in the figure.

Further, referring to FIG. 1, the surface of the photoreceptor drum is uniformly charged by charge scorotrons 19bk, 19y, 19m and 19c connected to a negative high voltage generator (not shown). When a laser beam modulated by a recording signal is irradiated onto the uniformly charged surface of the photoreceptor, the electric charge on the surface of the photoreceptor flows to the equipment ground of the drum body and disappears due to a photoconductive phenomenon. Here, the laser is not turned on in areas where the original density is high, and the laser is turned on in areas where the original density is low. As a result, the portions of the surfaces of the photoreceptor drums 18bk, 18yy, 18m and 18c, which correspond to areas with high original density, have a voltage of -800V.
The potential of the part corresponding to the light density part of the original is -10
The voltage becomes approximately 0 V, and an electrostatic latent image is formed corresponding to the density of the original. This electrostatic latent image is transferred to the black developing unit 20bk, yellow developing unit 20y, magenta developing unit 20I11, and cyan developing unit 20, respectively.
Developed using photosensitive drums 18bk and 18y.
, black on the surface of 18m and 18c respectively,
Forms yellow, magenta and cyan toner images.

“The toner in the developing unit is positively charged by stirring, and the developing unit is biased to about -200V by a developing bias generator (not shown), and the toner adheres to the area where the surface potential of the photoreceptor is higher than the developing bias, and the original A toner image corresponding to the image is formed.

On the other hand, the recording paper 267 stored in the transfer paper cassette 22 is fed out by the paper feeding operation of the feed roller 23, and transferred to the transfer belt 267 by the registration roller 24 at a predetermined timing.
Sent to 5. The recording paper placed on the transfer belt 25 is
Due to the movement of the transfer belt 25, the photosensitive drum 18bJ
The black, yellow, magenta, and cyan toners are transferred to the lower part of the transfer belt by the action of the transfer corotron while passing sequentially through the lower part of L 8yt 18m and 18c and passing through each photoreceptor drum 18bk, 18yp 18m and 18c. The images are sequentially transferred onto the recording paper.

The transferred recording paper is then sent to a thermal fixing unit 36, where the toner is fixed to the recording paper, and the recording paper is discharged to a tray 37.

On the other hand, residual toner on the surface of the photoreceptor after transfer is removed by cleaner units 2 lbk, 21y, 21m and 21c.

A cleaner unit 21bk and a black developing unit 20bk that collect black toner are connected to a toner collection pipe 42.
The black toner collected by the cleaner unit 21bk is collected by the developing unit 20bk. Note that the cleaner unit 21y is caused by reverse transfer of black toner from the recording paper during transfer to the photoreceptor drum 18y.

The yellow, magenta, and cyan toners collected at 21m and 21c are not collected for reuse because they are mixed with toners from different color developing devices in the preceding stages of these units.

FIG. 5 shows the inside of the toner recovery pipe 42.

Inside the toner recovery pipe 42, a toner recovery auger 4 is installed.
Contains 3. The auger 43 is formed of a coil spring and is freely rotatable inside the toner collection pipe 42 bent into a channel shape.

The auger 43 is rotationally driven in one direction by a driving means (not shown), and the toner collected in the unit 21bk is transferred to the developing unit 20b by the spiral pump action of the auger 43.
sent to k.

The transfer belt 25, which transports the recording paper in the direction from the photoreceptor drums 18bk to 18c, includes an idle roller 26° and a drive roller 7. It is stretched between an idle roller 28 and an idle roller 30, and is rotated counterclockwise by a drive roller 27. The drive roller 27 is pivotally connected to the left end of a lever 3 that is pivotally connected to the shaft 32. A plunger 35 of a black mode setting solenoid (not shown) is pivotally attached to the right end of the lever 31. A compression coil spring 34 is disposed between the plunger 35 and the shaft 32, and this spring 3
4 applies clockwise rotational force to the lever 31.

When the black mode setting solenoid is de-energized (color mode), as shown in FIG. 1, the transfer belt 25 on which the recording paper is placed is the photosensitive drum 44bk, 44y.

It is in contact with 44m and 44c. In this state, when recording paper is placed on the transfer belt 25 and toner images are formed on all drums, multiple toner images are transferred onto the recording paper as the recording paper moves (color mode), and the black mode setting solenoid is energized. (black mode), the lever 31 rotates counterclockwise against the repulsive force of the compression coil spring 34, the drive roller is lowered by 5 mm, and the transfer belt 25 is moved toward the photoreceptor drum 44y.

44m and 44c, and remains in contact with the photosensitive drum 44bk. In this state, the transfer belt 25
Since the upper recording paper only contacts the photosensitive drum 44bk, only the black toner image is transferred to the recording paper (black mode). Since the recording paper does not come into contact with the photoreceptor drums 44y, 44m, and 44c, the toner (residual toner) attached to the photoreceptor drums 44y, 44m, and 44c does not stick to the recording paper, and no yellow, magenta, cyan, or other stains appear on the recording paper. do not have. In other words, when copying in black mode, copies similar to those produced by a normal monochromatic black copying machine can be obtained.

The console board 300 includes a copy start switch, a color mode/black mode designation switch 302 (immediately after the power is turned on, the switch key is off and the color mode is set;
When the switch is closed twice, the switch key lights up and the black mode is set, and the black mode setting solenoid is energized; when the switch is closed the second time, the switch key goes out and the color mode is set, and the black mode setting solenoid is de-energized.) It is also equipped with other input key switches, character displays, indicator lights, etc.

Next, the operation timing of the main parts of the copying mechanism will be explained with reference to the time chart shown in FIG. FIG. 6 shows the case when two identical full-color copies are made. 1st
At approximately the same timing as the start of exposure scanning of the carriage 8, modulation energization of the laser 43bk based on the recording signal is started, and the lasers 43y, 431, and 43c are activated, respectively.
Photosensitive drums 44bk to 44y, 44m and 44c
Modulation energization is started after a delay of travel times Ty, Tm, and Tc of the transfer belt 25 corresponding to the distance. Transfer corotrons 29bk, 29y, 29m and 29c are lasers 43bk, 43y, 43m and 43, respectively.
It is energized after a delay of a predetermined time (time for the laser irradiation position on the photosensitive drum to reach the transfer corotron) from the start of the modulated energization in step c.

See Figure 2. The image processing unit 100 is a COD
7r + 7g and 7b, the three color image signals are converted into black (BK) and yellow (required for recording).
Y), magenta (M), and cyan (C) recording signals. The BK recording signal is sent directly to laser driver 1.
12bk, the Y, M, and C recording signals are stored in buffer memories 108y, 108m, and 108c, respectively, and then the Y, M, and C recording signals are stored in buffer memories 108y, 108m, and 108c. After the time delay of later reading out and converting into a recorded signal,
Laser driver 112y.

112m and 112c. Note that the image processing unit 100 has a C0D7r as described above in the copying machine mode.
, 7g and 7b. In the graphics mode, the three-color signals are provided from outside the copying machine through the external interface 117.

Shading correction circuit 10 of image processing unit 100
1 is color gradation data obtained by A/D converting the output signals of CCDs 7r, 7g, and 7b into 8-pips 1-.

The read color gradation data is created by correcting optical illuminance unevenness, sensitivity variations of the internal unit elements of the CCDs 7 rl 7 g and 7 b, and the like.

The multiplexer 102 is a multiplexer that selectively outputs either the output gradation data of the correction circuit 101 or the output gradation data of the interface circuit 117.

The γ correction circuit 103 that receives the output (color gradation data) of the multiplexer 102 changes the gradation (input gradation data) according to the characteristics of the photoreceptor, and also changes the gradation arbitrarily using the operation button of the console 300. Change the gender and input 8 pins 1
- Change the data to output 6-bit data. Since the output is 6 bits, data representing one of 64 gradations will be output. Three-color gradation data of 6 bits each indicating the gradation of red (R), green (G), and blue (B) outputted from the γ correction circuit 103 is provided to the complementary color generation circuit 104.

Complementary color generation is the conversion of the name of each color read signal to the recorded color signal, red (R) WI tone data becomes cyan (C) tone data, and green (G) tone data becomes magenta (M) tone data. data and also blue gradation data (
B) is converted (replaced) with yellow gradation data (Y).

The Y, M, and C data output from the complementary color generation circuit 104 are provided to a masking processing circuit 106.

Next, masking processing and UCR processing will be explained. The calculation formula for masking processing is generally Yi, Mi, Ci
: Data before masking.

Yo, Mo, co: data after masking.

In addition, the general formula for UCR processing is It can be expressed as

Therefore, in this embodiment, a new coefficient is obtained by using these equations and using the product of both coefficients to calculate the following. The coefficients (a, 1n, etc.) of the above calculation formula that perform both the masking process and the UCR/black generation process at the same time are calculated in advance and substituted into the above calculation formula to obtain the scheduled input Yi of the masking processing circuit 106,
Calculated values associated with Mi and Ci (6 bits each)
Yo', etc.: Output of UCR processing circuit 107)
is stored in ROM in advance. Therefore, in this embodiment, the masking processing circuit 106 and the UCR processing/black generation circuit are constituted by a set of ROMs, and the data at the address specified by inputs Y, M, and C to the masking processing circuit 10G is UCR. Buffer memories 108y, 108m, 108c are used as the output of the processing/black generation circuit ■07.
and the gradation processing circuit 109. In addition, generally speaking, the masking processing circuit 106 performs Y processing according to the characteristics of the spectral reflection wavelength of the toner for forming a recorded image.

The UCR processing circuit is for correcting the M and C signals, and the UCR processing circuit is for correcting the color balance in the superposition of the 1-toner of each color. After passing through the U CR processing/black generation circuit 107, black component data BK is generated by combining the input three color data of Y, M, and C, and the output data of each color component of Y, M, and C is , the value is corrected by subtracting the black component.

Next, the buffer memory 108y of the image processing unit 100
, 108m and 108c. These simply generate a time delay corresponding to the distance between the photoreceptor drums. The write timing of each memory is the same, but the read timing is as shown in Figure 6.
The memory 108y is activated in accordance with the modulation activation timing of the laser 43y, the memory 108m is activated in accordance with the modulation activation timing of the laser 43m, and the memory 108c is activated in accordance with the modulation activation timing of the laser 43c. . The capacity of each memory is when A3 is the maximum size,
24% of the maximum amount required for a minimum A3 document with 108y of memory
, 48% with 108m memory, 72% with 108c memory
It is sufficient if it is about %. For example, if the COD reading pixel density is 400 dpi (dots per inch: 15.75
dots/mm), the memory 108y has approximately 87 bytes, the memory 108m has approximately 174 bytes, and
The memory 108c only needs to have a capacity of approximately 261 bytes. In this embodiment, since 64 gradations and 6-bit data are handled, memories l08y, 108m and 108m are used.
The capacities of c are 87, 174, and 261 bytes, respectively. When calculating the memory address in units of 6 bits instead of units of bytes (8 bits), the memory address is 108y: 116K x 6 bits.
Memory 108m: 232K x 6 bits and memory 108c: 348K x 6 bits.

FIG. 9 shows the configuration of the memory 108c, which has the largest capacity. Note that the other memories 108y and 108m have similar configurations. However, the memory capacity is small.

To explain the outline of the memory configuration with reference to FIG. 9, three 64K x 1-bit memories are used as input data memory.
Six pieces are used to create a 384K x 6 bit configuration.

These are DRAMs 1 to 6 shown in FIG.

The data for which UCR processing has been completed is stored in FiF, which is a first-in/first-out (FiFo) memory.

Write to RAMI, 2. This is for correcting the difference between the output timing of the output data of the UCR process and the write timing of the memories DRAMs 1 to 6, and is a buffer for approximately one line. FiF.

The data written to RAMI, 2 is stored in DRAMs 1 to 6 at addresses sequentially determined by counter 1 starting from address O.
written to. Next, the address of counter 1 is incremented by 1 and the next data is written. In this manner, data is sequentially written into DRAMs 1 to 6, and when it reaches 384K, it is reset and data is written again starting from address 0. When counter 1 advances the address to 384 from the start of writing, DRAM1-6
Writing of data to the FiFo RAMs 1 and 2 is started (reading from DRAMs 1 to 6). At the start, counter 2 is reset and the data at address 0 is first FiF.

The data is written to RAMI, 2, counter 2 becomes address 1, and the data is sequentially read out in the same manner as writing. This counter 2 is also 384
When it reaches K, it is reset and written starting from address 0. Fi
The data written in Fo RAM 1, 2 is output to the density pattern processing circuit 109 based on the synchronization signal from the laser driver 112c.

The data selector 1 selects the address (count data) of counter 1 or counter 2.

When writing data to DRAMs 1 to 6, the address data of counter 1 is output, and when reading data, the address data of counter 2 is output.

Data selector 2 is 64K x 1 bit DRAM
Since addresses 1 to 6 are determined by multiplexing the upper 8 bits and the lower 8 bits, they are used to select the upper/lower bits of the 16-bit address. Also, the decoder is 38
6 blocks of DRAM1 every 64 to 4 addresses
This is an address decoder for selecting 6 to 6.

Next, the tone processing circuit 109 of the image processing unit 100 will be explained. This circuit 109 converts each multivalued input data of Y, M, and C into binary data, and performs area gradation processing to make the gradation of the input data react to the output data. .

The 6-bit gradation data can represent density information of 64 gradations. Ideally, if the dot diameter of one dot could be varied in 64 steps, there would be no need to reduce the resolution, but in the laser beam electrophotography method, the dot diameter modulation only stabilizes the gradation by about 4 steps at most, and generally the area There are many combinations of gradation method, area gradation method, and beam modulation. Here, area gradation processing is performed for each 8×8 pixel matrix to express 64 gray levels of halftones.

The gradation processing circuit 109 includes four sets of units that process data of each color component of Y, M, C, and BK. The configuration of each unit is approximately the same. One configuration thereof is shown in FIG. 7, and the details of each circuit are shown in FIGS. 8all, 8c, and 8d.

Referring first to FIG. 7, this circuit includes an 8×8 averaging circuit 150. Edge extraction circuit 151. Edge emphasis circuit 15
2. Density pattern processing circuit 153° Edge determination circuit 15
4. Data correction circuit 155° random dither processing circuit 1
56 etc. are equipped.

Roughly speaking, this gradation processing unit includes two types of gradation processing circuits, and automatically selects one of the processing systems depending on the state of input data.

The first processing system includes an 8×8 averaging circuit 150 and a density pattern processing circuit l! 4153. This processing system performs gradation processing using the density pattern method. In this example, the unit of gradation processing is an area of 8 consecutive pixels in each of the main scanning direction and the sub-scanning direction, that is, an 8×8 matrix area, and one gradation is expressed by 64 pixels.

In the density pattern method, the density is calculated by averaging input data for 64 pixels corresponding to a unit processing area (8x8 area), and the density is compared with the value at the corresponding position in the threshold matrix table to determine the magnitude relationship between them. “1” or rO depending on
Generate binary data of J.

FIG. 8a shows an 8×8 averaging circuit 150, and FIG. 8b shows the operation timing of the circuit 150. The images are averaged in the sub-scanning direction (the exposure scanning direction of the first carriage 8) x 8 pixels in the main scanning direction (direction perpendicular to the exposure scanning direction: CCD
(electronic circuit scanning direction) 8 pixel data, a total of 64 pixels. Also, when averaging 64 pieces of 6-bit data, if you add all the data and then set it to 1/64, the adder will function as 1
A 2-bit adder is required, but in this embodiment, an 8-bit adder is used. First, sub-scanning direction 8
To explain the addition of pixels, the 1'th data is stored in latch l.
The second data is added to the second data in adder 1, and the added value data is latched in latch 2. The third data is latched in latch 1, added to the fourth data by adder l, and then added to the data in latch 2 by adder 2, and the sum of 4 pixel data (gradation data) is output from adder 2. Output. This data is latched into latch 3.

Similarly, when the fifth to eighth data are added and output from the adder 2, they are added to the data in the latch 3 by the adder 3, and data for every eight pixels in the sub-scanning direction is output.

Note that the output of adder 1 becomes 7 by adding 6-bit data.
The output of adders 2 and 3 is 8 bits, and the output of adders 2 and 3 is 8 bits, but the output is 17 bits by taking the upper 7 bits.
The value is set to 2.

Next, addition in the main scanning direction will be explained. The average value of the 8 pixels output from the adder 3 is for l main scanning lines.

It is stored in RAM1. When the second line is output from adder 3, it is added to the contents of RAM 1 by adder 4 and R
It is stored in AM2. By this addition, the first and second line data are stored in RAM 2.

When the third line is output from adder Ia3, adder 4 adds it to the contents of RAMI and stores it in RAM2.

This addition causes l+2 line data to be stored in the RAM2. When the third line is output from adder 3, adder 4
is added to the contents of RAM2 and stored in RAMI. Similarly RAM 1.

2 alternately serves as addition data output (reading) and storage,
When the 8th line is output from the adder 3, the adder 4 adds it to the contents of RAMI and outputs 8 lines of added data. Here, like adders 2 and 3, adder 4 also outputs averaged (1/2) data by outputting the upper 7 bits of 7-bit data addition. In this embodiment, two 4-bit binary full adders (7428'3) are used in parallel as adders.

The data averaged as described above is input to the density pattern processing circuit 153. Density pattern processing circuit 1
53 is one memory ROM3 (read-only memory) 361 shown in FIG. 8d. This memory RO
M3 stores in advance the predetermined threshold value 71 - the threshold value at each position of the Rixtable, and the comparison results for each of the densities 0 to 63. Therefore, when averaged density data and main scanning position are applied to the address line, binary data is immediately output to the output terminal. As for the output data, eight pixels in the sub-scanning direction are simultaneously outputted as 8-bit data, and then converted into serial data by the connected shift register 362.

The threshold matrix tilt pull is 8 in the gradation processing unit area.
There are 64 threshold values set for each pixel of a ×8 matrix. In this example, values ranging from 1 to 63 are arranged in a spiral systematic pattern arrangement, as shown in Figure 10e. Therefore, for example, when the data shown in FIG. 10b is input, the data shown in FIG. 10f is output. In Fig. 10f, the hatched part corresponds to the data "1: Record", and the other parts correspond to the data "1: Record".
0: Not recorded.

Next, the second gradation processing system will be explained. The edge enhancement circuit 152 shown in FIG. 7 is a two-dimensional spatial filter, and when there is a change in density level in the input data, that is, when there is edge information, it amplifies the density change in the data in that area and emphasizes the edge. do. In this example, the pattern PT shown in FIG. 12 is used.

That is, assuming a 3×3 pixel matrix area consisting of A, B, C, D, E, F, G, H, and I, the data of the center pixel E is replaced with the value E' of the following equation.

E' = 13・E-2(B+D+F+l+)-(A+C
+G+I) However, when this process is performed, the result is O~63
Since some data may be outside the range, the data correction circuit 15
If 5 becomes 64 or more, replace it with the fixed value 63,
Replace negative values with 0. For example, when the data shown in FIG. Job is input to the edge enhancement circuit 152, the data shown in FIG. 11d is obtained as the output of the data correction circuit 155.

The edge extraction circuit 1.51 is a spatial filter similar to the edge enhancement circuit 152, but the coefficients assigned to each pixel of the filter are different. When the data is passed through this filter, the processing result becomes mostly O in the portions other than the edges of the data, thereby extracting only edge information.

In this example, the edge extraction circuit 151 employs the pattern FD shown in FIG. Therefore, when passed through this filter, the data of the center pixel E is converted into E n of the following equation.

E''=12・E-2(11+D1F+H)-(A+C+
G+I) Edge enhancement circuit 152 and edge extraction circuit 151
have similar circuit configurations, so in this example most of their circuits are shared by both.

In order to configure a spatial filter of 3×3 pixel matrix, it is necessary to refer to all the two-dimensional data of 3×3 pixels at the same timing. but.

Since the data input to the filter is in time series, in order to match the cursed time of these 9 pixel data,
A matrix register 210 shown in FIG. 8c is provided. This register 210 consists of nine latches 211 to 219.
and two sets of 1-line buffers (memories) 220 and 221
It is equipped with

That is, each of the latches 211 to 219 holds data for one pixel, and the one-line buffers 220 and 221 each store data for one line. m columns (hereinafter,
Cn, m)), each latch 211, 212゜213.214.2]6
, 217, 218 and 219, respectively, (n
+1. m +1), (n +1. m), (n
+L, m −1).

(rz m+ IL Cr++ m-IL [n-1,
m+1).

The pixel data of (n-1, m) and (n-1, m-13) are cursed.

In other words, the data of each picture MA, B, C, D, E, F, G, H, and I constituting the 3X3 matrix shown in FIG.
15. Appears at the output terminals of 214, 213, 212 and 211 at the same timing.

Referring to FIG. 8c, an arithmetic unit 230 is connected to the output of the matrix register 210.

This arithmetic unit 230 includes seven adders 231, 23
2. It is composed of 233, 234, 235, 236 and 237. Latch 2 is connected to the two input terminals of adder 231.
11 and the output of latch 213 are connected, and adder 2
The output of latch 214 and the latch 2 are connected to the two input terminals of 32.
The outputs of latch 217 and latch 219 are connected to the two input terminals of adder 233, and the outputs of latch 212 and latch 218 are connected to two input terminals of adder 234. has been done.

Therefore, adders 231, 232, 233 and 234 are
Output the values of G+I, D+F, A+C: and B+H, respectively. Since the adder 235 adds the output data of the adder 231 and the output data of the adder 233, A+C+G+I
Outputs the value of . Further, since the adder 236 adds the output data of the adder 232 and the output data of the adder 234, it outputs a value of B+D+F+H. The outputs of adders 235 and 236 are connected to two input terminals of adder 237. However, the output of the adder 236 is connected to the adder 237 in a state where it is shifted to the higher order digit by one bit. Therefore, the output terminal of the adder 237 has 2.(B+
The value of D+F10H)+A+C101I appears.

The 6-bit signal line SE connected to the output of the latch 215 and the 10-bit signal line Sx connected to the output of the adder 237 are connected to the memory 320A (ROM
It is commonly connected to the input (address) terminals of I) and 310 (ROM4).

The memory 320A is a read-only memory, and 13.
The calculation result of E+X is stored in advance at the corresponding memory address (X is the value of the signal line SX). However, if the calculation result is negative, 0 is stored instead of the calculation result, and if the calculation result is 64 or more, 63 is stored instead of the calculation result. Therefore, the output of memory 320A will be 6 bits. That is, the output of the memory 320A corresponds to the output of the data correction circuit 155 which is the output of the edge emphasis circuit 152 shown in FIG. Here, data correction is performed in memory 320A.
It is carried out inside.

Further, the memory 310 is a read-only memory, and the memory 310 is a read-only memory, and
- The result of comparing the calculation result of E×X with the fixed threshold value 32 is stored in advance in a memory address corresponding to the input data. That is, if the edge extraction result is 32 or more, "l" is output, otherwise "0" is output. Therefore, 1, for example, the data shown in the first ob figure is the gradation processing circuit 1.
09, the output of the memory 310 contains the 11th
Binary data shown in figure c (the hatched pixels are
1) will appear.

The 6-bit density data obtained by edge enhancement and data correction is applied to a random dither processing circuit 156.

This circuit 156 is connected to the memory (ROM2) 33 in FIG. 8d.
1. The digital comparator consists of a 332° 8-line buffer (memory), etc. The memory 331 is a read-only memory, and has 64 kinds of threshold values in the range of 0 to 63 stored in advance in a Bayer type random pattern arrangement as shown in FIG. 10c. By applying the pixel position in the main scanning direction and the sub-scanning direction to the address terminal of the memory 331, the threshold value at that pixel position is automatically set in the memory 331.
31. The threshold value and memory 320A
The result of comparing with the output value of.

That is, a binary signal is obtained at the output of digital comparator 332. This binary signal is used to match the timing with the output data of the edge determination circuit 154.

After being delayed by 8 lines by the 8-line buffer 350, it is applied to the AND gate 373.

On the other hand, the binary signal obtained at the output of the memory 310, ie, data indicating the presence or absence of an edge for each pixel, is applied to the accumulator circuit 340 in FIG. 8d. The edge determination circuit 154 shown in FIG. 7 includes a part of the memory 31O and an accumulation circuit 340.
It consists of Accumulator circuit 340 includes latches 342 .
Random access memory 345, 346, 347. It consists of a bus driver 344, etc.

FIG. 8e shows a schematic operation of the accumulation circuit 340 shown in FIG. 8d. The operation of the accumulation circuit 340 will be explained with reference to FIG. 8e. The latch 342 latches a single input signal in synchronization with the generation timing of each pixel signal. In addition, the latch 34
2 resets the latched data at a timing of every 8 pixels. The accumulation circuit 340 repeats the same operation every 8 lines of sub-scanning.

First, a description will be given of the state in which the latch 342 has been reset in the first line (line n in FIG. 8e). Edge data corresponding to the first pixel is applied to the latch 342 via the OR gate 341 and held in the latch 342 at the first latch timing. Similarly, the second pixel,
The latch 342 holds input data at the timing of each data of the third pixel, the fourth pixel, and so on. The data held in latch 342 is applied to one input terminal of OR gate 341. Therefore, if some data "1" is input to the latch 342 after completing the reset, the input data of the latch 342 will always be "1" thereafter. When latching for 8 pixels is completed after reset, the output data of the latch 342 is transferred to the memory 34 via the bus driver 344.
5 and stored therein.

Immediately after that, the latch 342 is reset, and then data processing for eight pixels is performed again in the same manner as above. However, the address of the memo 345 that stores the data of the latch 342 is updated each time it is stored.

In other words, the edge information (whether or not rlJ is present among the 8 pixels) of the first line of each 8×8 matrix having a large number in the main scanning direction is stored in the memory 345.

In the second line, as in the case of the first line, each time the latch 342 is reset, it is checked whether there is a "1" in the data for eight pixels.

However, when results for 8 pixels are obtained, the data of the memory 345 that stores the data of the first line is read out, and the logical sum (output of the OR gate 343) between it and the result of the second line is sent via the bus driver 344. and stored in memory 346.

In the third line, when data for 8 pixels is obtained, the data of the memory 346 that stores the data of the first line and the second line is read out, and the logical sum (output of the OR gate 343) of this and the result of the third line is read out. ) is stored in the memory 345 via the bus driver 344.

Similarly, the fourth line, the fifth line, the sixth line and the seventh line
In the line, reading data from the memory 345 and writing data from the memory 346, and reading data from the memory 346 and writing data from the memory 345 are performed alternately.

In the 8th line, when data for 8 pixels is obtained, the memory 3 that stores the data of the 1st to 7th lines
45 is read out, and the logical sum (output of the OR gate 343) between it and the result of the 8th line is stored in the memory 347. In other words, unit pixel area (8x8 matrix)
If there is one or more edge data "1" in the memory 347, "1" is stored in the corresponding address of the memory 347, and if there is not, "0" is stored in the corresponding address of the memory 347.

The final edge information stored in the memory 347 is read out at a predetermined timing and applied to the inverter 371 and the AND gate 373. This final edge information is “1”
That is, if there is an edge, the AND gate 373 is opened and the AND gate 372 is closed, and binary data dithered in a random pattern is output via the OR gate 374.

When the final edge information is "0", that is, there is no edge, the AND gate 372 is opened and the AND gate 373 is closed, and the binary data subjected to the density pattern processing using the systematic pattern is
It is output via OR gate 374.

Each color (Y, M, C) is binarized in this way.

The data for each color (BK) is the laser driver 43y for each color.

Given to 43m, 43c and 43bk.

The synchronization control circuit 114 determines the activation timing of each of the above elements and matches the timing between each element. 200 is a microprocessor system that controls all the elements shown in FIG. 2 described above, that is, controls the copying machine. This processor system 200 controls copying in various modes set on the console, and includes not only the image reading and recording system shown in FIG. 2, but also the photoconductor power system and the exposure system.

Sequences such as charger system, developing system, fixing system, etc. are performed.

FIG. 13 shows an interface between the polygon mirror driving motor and the microprocessor system (200: FIG. 2). The input/output boat 207 shown in FIG. 13 is connected to the bus 206 of the system 200.

In addition, in FIG. 13, 45 is the photosensitive drum 18bk.
, l 8y, 18m and 18c, and is energized by a motor driver 46.

In addition, the input/output board 20 is equipped with a driver that energizes each part of the copying machine, a processing circuit connected to the sensor, etc.
7 or other input/output boats connected to the system 20
Although it is connected to 0, the illustration of 1 is omitted.

Next, the operation timing of each part based on the control operations of the microprocessor system 200 and the synchronous control circuit 114 will be explained.

First, when a power switch (not shown) is turned on, the device starts a warm-up operation.

・Increasing the temperature of the fixing unit 36, ・Starting the polygon mirror at a constant speed, ・Home positioning of the carriage 8, ・Generating the line synchronization clock (1, 26Ktlz), ・Generating the video synchronization clock (8, 42M) )Iz).

・Perform operations such as initializing various counters. The line synchronized clock is supplied to the polygon mirror motor driver and the CCD driver, and the former uses this signal as a reference signal for a phase-locked loop (PLL) servo, and the feedback signal to the beam sensor 4.
So that the beam detection signals of 4bk, 44y, 44m and 44c have the same frequency as the line synchronization clock.
Further, it is controlled to have a predetermined phase relationship. The latter is
It is used as a main scanning start signal for CCD reading. Note that the detection signals (pulses) of the beam sensors 44bk, 44y, 44m, and 44c are output for each color (each sensor) and are used as the signal for synchronizing the start of laser beam main scanning. Note that the frequency of the line synchronization signal and the detection signal of each beam sensor are locked by PLL and are the same, but there may be a slight phase difference, so the scanning reference is not the line synchronization signal but the frequency of each beam sensor. The detection signal is used.

The video synchronization clock has a frequency of 1 dot (1 pixel).

It has a wave number and is supplied to the CCD driver and laser driver.

Various counters are (1) Reading line counter.

(2) BK, vlM, C, 8, f mill line counter, (3) reading dot counter, and (4) BK
, Y, M, C storage dot counters, but the above (1) and (2) are implemented in the microprocessor system 20.
This is a program counter substituted by the operation of the CPU 202 of 0, and (3) and (4) are provided individually on the hardware, although not shown.

Next, the timing of the print cycle is shown in Figure 14,
Let me explain this. When the warm-up operation is completed, the state becomes ready for printing, and when the copy start key switch 301 is turned on, the CPU 2 of the system 200
02, the first carriage 8 drive motor (first
Carriages 8 and 9 (1/2 of 8) begin to rotate (Figure 3).
speed) starts scanning (exposure scanning) to the left. When the carriage 8 is at the home position, the output of the home position sensor 39 is 1 (soon after the start of exposure scanning (sub-scanning).If the reading line counter is cleared at the time when it changes from H to L, At the same time, the count is enabled.The time point when 11 changes to L is the position where the leading edge of the document is exposed.

With the line synchronization clock that comes in after the sensor 39 goes low, the read line counter is counted up every pulse. Also, when the line synchronization clock comes in, the reading dot counter is cleared at the rising edge of the clock to enable counting.

Therefore, the first line is read in 1 pixel, 12 pixels, 2... after the home position sensor 39 becomes L, in synchronization with the video synchronization clock immediately after the input of the first line synchronization clock. . . . Pixel 4667 is read sequentially. still,
Pixel counting is done by a read dot counter. Further, the content of the read line counter at this time is 1.

Similarly, for the second and subsequent lines, the reading line counter is incremented by the next line synchronization clock, the reading dot counter is cleared, and synchronized with the next video synchronization clock, the reading counter is incremented, and pixels are read. Do the following.

In this way, the lines are sequentially read, and when the reading line counter counts up to 6615 lines, the last reading is performed on that line, and the carriage drive motor is reversely energized to return the carriages 8 and 9 to their home positions.

The pixel data read in the above manner is sequentially sent to the image processing unit 100 and subjected to various image processing. How long does it take to process this image?

At least two clocks of the line synchronization clock signal are required.

Next, in writing, first clear the write line counter and enable the count: When the read line counter is 2, the BKl write counter is set; when the read line counter is 1577, the Y write counter is set; when the read line counter is set to 3152, the Y write counter is set; When the M write counter is 4727 and the read line counter is 4727, the C write counter is cleared and enabled to count, respectively.

These count ups are calculated by each beam sensor 4.
This is done at the rising edge of the detection signals 4bk, 44y, 44m and 44c. Further, the 1F dot counters (BK, Y, M, C) are cleared at the rising edge of the detection signal of each beam sensor, and counting up is performed by the video synchronization signal.

Writing for each color begins when the content of the reading counter reaches a predetermined value, the writing line counter for each color becomes counting enable, and counting starts with the first beam sensor detection signal (content 1). When the dot counter reaches a predetermined value, the laser driver is driven to perform writing. Dot count is 1-4
Between 00.

As dummy data, values 401 to 5077 (4677 pieces) are writable. Here, the dummy data includes the beam sensors 44bk, 44y, 44m and 44c and the photosensitive drum 18 bk v 18 y T 18 @I
Also, the write data (1 or 0) is captured at the falling edge of the video sync signal, which is to adjust the physical distance of I and 18c. The writing range in the line direction is when each writing line counter is 1 to 6615 lines.

Now, as shown in FIG. 14, after starting the exposure scan,
Since BK recording data is obtained from the time of scanning the third line of OD, the recording activation of the BK recording apparatus is started in synchronization with the acquisition of BK data. Therefore, the frame buffer memory is omitted in the BK signal processing line. On the other hand, since the Y, M, and C recording devices are shifted in the paper feeding direction, the recording start delay time rIIITy corresponding to the amount of shift from the BK recording device,7. ．． and T
It is necessary to store the recorded signal between 87 and 87 bytes of the frame memory 108) l,
174 bytes of frame memory 108m and 26
1 is equipped with a byte frame memory 108c,
In order to reduce the storage capacity of these memories,
The stored data is gradation data before being converted into a density pattern. Therefore, since a frame memory for BK is not required, the amount of memory can be reduced, and furthermore, the capacity of the separate frame memory for storing gradation data can be reduced. The photoreceptor drum has a length (2πr) that is much shorter than the long side length of the maximum size A3 set in this copying machine, and therefore the arrangement pitch of the photoreceptor drum is also extremely short.

Next, other embodiments and modifications of the present invention will be described.

FIG. 15a schematically shows one gradation processing circuit.
Figure 5b shows some details of the circuit.

Referring first to FIG. 15a. In this example, the input of 8x8 averaging circuit 150 is connected to the output of edge enhancement circuit 152. That is, in a general image processing device, an MTF correction circuit is provided immediately after the image reading device, but in this example, an MTF correction circuit is provided.

It is included in the gradation processing circuit 109 that processes a signal that has undergone color correction processing including γ correction processing, complementary color generation processing, masking processing, UCR processing, and black generation processing. As a result, the MTP correction circuit and the edge enhancement circuit used for gradation processing are integrated, so the circuit configuration becomes simple. Moreover, since errors caused by edge enhancement processing (and MTF correction) (errors caused by overflow and underflow correction) are not amplified by color correction processing, errors related to color reproduction are reduced.

Further, in this embodiment, the presence or absence of edges in input information is determined based on the result of edge enhancement. In other words, when edge enhancement processing is performed, if the input data contains edge information, it will be amplified, so for example, if the input data is in the range of 0 to 63, the processing result will include edge information of 64 or more. and negative ones occur. In other words, if overflow or underflow occurs in the edge enhancement result, it can be determined that edge information exists, and if no overflow or underflow occurs, it can be determined that edge information does not exist. The other configurations are the same as those of the previous embodiment.

Next, the specific configuration and operation of the gradation processing circuit will be explained. The edge emphasis circuit 152 includes the circuit shown in FIG. 8c of the embodiment described above, and since the circuit shown in FIG. 8c has already been explained, the description will be made with reference to FIG. 15b.

The signal lines SE and SX drawn from the matrix register 210 and the arithmetic unit 230 are connected to the memory 320
It is connected to the B address signal line. memory 32
0B is a read-only memory, and the calculation result of 13・E+X and information on the presence or absence of overflow and underflow are stored in advance at the address corresponding to the input data (
E and X are the values of signal lines SE and SX, respectively).

If an overflow occurs as a result of edge enhancement processing, the output signal lines 322 and 323 are set to high level H and low level L, and the 6-bit signal line 32! Set the correction value 63 to . Further, when an underflow occurs, the output signal lines 322 and 323 are set to a low level L and a high level H, and the signal line 321 is set to a correction value 0. If no overflow or underflow occurs, the calculation result is sent directly to the signal line 3.
21, and low level L is output to both signal lines 322 and 323.゛The output signal lines 322 and 323 of the memory 320B are
It is connected to the accumulation circuit 340B. Accumulation circuit 340B
is identical to circuit 340 of FIG. 8d, except that OR gate 341B is of the three-person type. Therefore,
If at least one of overflow and underflow occurs as a result of the edge enhancement processing, "l" is stored at a predetermined address in the memory 347, and if neither of these occurs, "0" is stored at a predetermined address in the memory 347.

The 6-bit data output line of memory 320B is connected to the input terminals of the digital comparator 332 of the random dither processing circuit and the 8.times.8 averaging circuit.

The other configurations and operations are the same as those of the previous embodiment.

FIG. 16a shows another embodiment of the gradation processing circuit. See Figure 16a. In this embodiment, an OR gate 165 performs an OR operation on first data obtained by binarizing the edge extraction result and second data obtained by performing random dither processing on the input data as is, and outputs the result. Of course, when edge information is not included, data from the density pattern processing system is output.

Next, the specific configuration and operation will be explained with reference to FIG. 16b. The signal line SE drawn out from the matrix register 210 is connected to a part of the address signal line of the memory 320C and the random dither processing circuit 330,
The signal line SX drawn out from the arithmetic unit 230 is connected to the remaining address signal lines of the memory 320C.The memory 320G is a read-only memory and compares the result of the operation of 12·E+X with the fixed threshold value 32. The result is stored in advance at an address corresponding to the input data (E and X are the values of the signal lines SE and SX, respectively).

Therefore, on the output signal line 325 of the memory 320C,
Binary data is obtained as a result of edge extraction of input data. For example, if the data in FIG. 10b is input, the data in FIG. 1ie is output on signal line 325. In FIG. 11c, the hatched pixels correspond to data "1" and the other pixels correspond to data "0". The other configurations and operations are the same as those of the previous embodiment.

FIG. 17a shows another embodiment of the gradation processing circuit. See Figure 17a. In this embodiment, a large number of gradation processing systems are provided, and depending on the situation at the time,
The processing system that provides the most favorable results is automatically selected.

Specifically, there are seven processing systems.

The first processing system includes an 8×8 averaging circuit wI 401 and a density pattern processing circuit 410, and the second processing system includes an edge emphasis circuit (A) 402. The third processing system includes an edge emphasis circuit (A) 402, a correction circuit 405. and a random dither processing port N(8) 412, and a fourth
The processing system is the edge enhancer M(B) 403. Correction circuit 40
6. and a random dither processing circuit (A) 413, and the fifth processing system is an edge emphasis circuit (B) 403. Correction circuit 406° and random dither processing circuit (B) 414
The sixth processing system is a random dither processing circuit (
C) 408 and an OR gate 416, and the seventh processing system consists of a random dither processing circuit (D) 409 and an OR gate 417.

Edge enhancement circuit (A) 402 and edge enhancement circuit (B)
403 has a similar configuration, but the filter coefficients, that is, the degree of edge enhancement are different. Random dither processing circuits (A) 411 and 413 have the same configuration. Also,
Random dither processing circuits (B) 412 and 414 have the same configuration. Random dither processing circuit (A), (
B), (C) and CD> have similar configurations, but have different threshold matrix tables. The difference between these threshold matrix tenables is that the size of the threshold matrix is 8×8 and 4×4, etc.) and
There are threshold arrangement patterns (random arrangement, systematic arrangement, etc.). Note that these parameters can be arbitrarily selected as necessary.

In other words, since each of the seven processing systems has different processing contents, different processing results may occur. The processing content (parameters) to obtain a desirable processing result changes depending on the input data, so it is difficult to judge in advance which processing parameters are the most desirable, but it is possible to prepare a number of processing systems with different parameters. However, by comparing the processing results of each system and selecting the most preferable result, only the advantages of each processing system can be utilized.

The configuration and operation of the first processing system are similar to the density pattern processing system of the previous embodiment. The outputs of the second processing system to the seventh processing system include gradation number counting times wI41g and 41g, respectively.
9, 420, 421, 422 and 423 are connected. Roughly speaking, these accumulate binary data output by each processing system within each matrix to generate its gradation value. These six gradation number counting circuits all have the same configuration. One configuration of the gradation number counting circuit is shown in FIG. 17b.

Referring to FIG. 17b, this circuit includes a counter 601
, adder 602. Bus driver 603, 604, 605
．． It consists of memories 606, 607 and 608. This circuit repeats the same operation every 8 lines of sub-scanning.

A counter 601 counts the binary data output by each gradation processing system. Further, the count value of the counter 601 is cleared at the timing of every 8 pixels in the main scanning direction. Therefore, the counter 601 counts the number of "1"s included in the data for eight pixels that appear between when it is cleared and when it is cleared next time. The data counted by the counter 601 is transferred to and stored in memory as follows before it is cleared.

In the first line of sub-scanning, the output data of the counter 601 is sent to the memory 606 via the bus driver 603.
It is stored at a predetermined address according to the position in the main scanning direction. In the second line of sub-scanning, the data of the memory 606 storing the result of the first line is read out, and the result of adding the data and the count value of the counter 601 by the adder 602 is stored in the memory 607.

In the third line of sub-scanning, the data of the memory 607 that stores the accumulated values of each eight pixels of the first line and the second line is read out, and the result of adding this and the counted value of the counter 601 with the adder 602 is added. , stored in memory 606. Similarly, data reading from the memory 606 and memory 60
7 data writing, and data reading of the memory 607 and data writing of the memo IJ 606 are repeated alternately to process the data of the fourth, fifth, sixth, and seventh lines.

In the 8th line, the data of the memory 606 that stores the cumulative value of the data of the 1st line to the 7th line is read out, and the result of adding the data and the counted value of the counter 601 by the adder 602 is stored in the memory 608. do. Therefore, the memory 608 stores 8X of each of the gradation-processed input data.
The number of rlJ included in the 8 matrix, that is, the tone value is held.

Referring again to FIG. 17a, the output of each gradation processing system and the output of each gradation number counting circuit are connected to a data selector 424. Each input terminal DX, DA, DB, DC of this data selector 424.

DD, DE, and DF are provided with the first to seventh gradation processing systems, respectively.
The data processed by the gradation processing system is input, and the data output from the second to seventh gradation processing systems is input to each input terminal CA, CB, CC, CD, CE, and CF. gradation values are input.

In addition, the input terminal Sl of the data selector 424 has an 8×8
The average value of the input data of each pixel matrix before gradation processing is input, and the input terminal S2 receives binary data indicating the presence or absence of an edge in each 8×8 pixel matrix (1 for edge presence, 1 for no edge). 0) is input.

The configuration of the data selector 424 is shown in FIG. 17c. Referring to FIG. 17c, this data selector 424 is
Memories 501-509. Nantes Gate 510-515.
Inverter 516. It consists of Nantes Gate 517 and Or Gate 518.

Memories 501-509 are read-only memories.

Memories 501, 502, 503, 504, 505 and 5
Some address terminals A'l of 06 have 2nd, 3rd, . 4th. Fifth. The gradation values of data processed by the sixth and seventh gradation processing systems are input.

The average gradation value of the input data is commonly input to the other address terminals A2 of the memories 501 to 506.

In each of the memories 501 to 506, the absolute value of the difference between the input value of the address terminal A1 and the input value of the address terminal A2 is stored in advance at the corresponding memory address.

Therefore, if the processing results of the second to seventh gradation processing systems are A, B, C, D, E, and F, respectively, and the average gradation of input data is X, then from each memory will output data like the following:

501: IA-Xl 502: IB-Xl 503: Ic-Xl 504: ID-Xl 505: IE-Xl 506: IF-Xl In other words, 1 from each of the memories 501 to 506, the results of processing by each gradation processing system and the average gradation of the input data,
That is, the gradation error is output. However, if the error is 8 or more, it is replaced with 7 and converted to 3-bit data.

The output data of memories 501, 502 and 503 are as follows.

Address terminals Al, A2 and A of memory 507, respectively.
3 and the output data of memories 504, 505 and 506 are respectively input to address terminals AI and 508 of memory 508.
Input to A2 and A3.

Memories 507 and 508 have address terminals AI.

3, which is the same as the smallest input value of A2 and A3
bit data and the address group in which it was input (
2-bit data indicating AI, A2, or A3) is stored in advance at the corresponding memory address.

Therefore, the output terminal of the memory 507 stores the gradation level of the one that outputs the result with the smallest gradation error among the second gradation processing system, third gradation processing system, and fourth gradation processing system. error and
A value indicating the processing system is outputted to the output terminal of the memory 508, and the value with the largest gradation error among the fifth gradation processing system, the sixth gradation processing system, and the seventh gradation processing system is output. The gradation error of the output with a small result and a value indicating the processing system are output.

The 5-bit data output from the memory 507 is sent to the memory 509.
The 5-bit data inputted to the address terminal AI of the memory 508 and outputted from the memory 508 is inputted to the address terminal A2 of the memory 509. In the memory 509, data indicating the results of the following processing is stored in advance at corresponding memory addresses. That is, among the data at address terminals AI and A2, 3-bit data corresponding to the gradation error are compared with each other,
From the information indicating the address terminal with the smallest error and the 2-bit processing system identification information input to it, it is possible to determine which of the six gradation processing systems outputs the value with the smallest gradation error. It makes a judgment and generates 6-bit data.

In this 6-bit data, one bit is at high level H and all other bits are at low level L. Each bit of this 6-bit data is
is applied to one input terminal of . For example, 2nd to 7th
If the second gradation processing system outputs data with the smallest gradation error among the six gradation processing systems, a high level H is applied to the Nant gate 510, and the second gradation processing system outputs data with the smallest gradation error.
~515, a low level L is applied.

In this case, if the input signal S2 is at a high level H, only the data DA output by the second gradation processing system is output to the output terminal of the data selector 424 via the Nant gate 510 and the OR gate 518. If edge information is not included in the 8×8 matrix, the signal S2 will be at a low level L, regardless of the magnitude of the gradation error in the data output by the second to seventh gradation processing systems. The output data DX of the first gradation processing system is outputted to the output terminal of the data selector 424 via the Nant gate 517 and the OR gate 518.

That is, in this embodiment, if there is no edge information in the 8×8 matrix, the result of performing the density pattern processing (threshold table is a systematic pattern) that is most excellent in terms of gradation is output. , if there is edge information, the results of a plurality of dither processes with different processing parameters are compared, and the one with the smallest gradation error is automatically selected and output. This makes it possible to output data with excellent resolution and the best gradation for all input data.

[Effects] As described above, according to the present invention, a plurality of threshold matrices having different threshold array patterns are used and the array pattern is switched depending on the presence or absence of edge information, so that characters and line drawings containing edge information are For data, a processing result with high resolution can be obtained, and for data that does not include edge information, a processing result with the best gradation can be obtained.

[Brief explanation of the drawing]

The first @ is a cross-sectional view mainly showing the configuration of the main mechanical parts of one type of digital color copying machine embodying the present invention. Figure 2 is a block diagram showing the configuration of the electrical image processing section;
3 is an enlarged perspective view of a part of the first carriage 8 shown in FIG. 1, FIG. 4 is an exploded perspective view of the BK recording device section shown in FIG. 1, and FIG. 5 is an exploded perspective view of the BK recording device section shown in FIG. FIG. 3 is an enlarged perspective view showing a toner recovery pipe in a broken state. FIG. 6 is a time chart showing the relationship between original reading scanning timing, recording biasing timing, and transfer biasing timing in the above embodiment. FIG. 7 is a block diagram showing the configuration of the gradation processing circuit 109 shown in FIG. 2. FIGS. 8a, 8c, and 8d are block diagrams showing the configuration of each part of the circuit shown in FIG. 7. Figures 8b and 8e illustrate circuits 150 and 34, respectively.
3 is a time chart showing a data processing sequence of 0; FIG. 9 is a block diagram showing the configuration of buffer memory 108c shown in FIG. 2. Figure 10a is a plan view showing an example of a partial area of a document image corresponding to a unit area of 1-gradation processing, and Figure iob is a two-dimensional expansion of multivalued data obtained by reading the image in Figure LOa. FIG. FIG. 10c, FIG. 10e, and FIG. 11h are plan views showing two-dimensional expansion of the contents of three types of threshold tables used in gradation processing. Figures 10d and 10f show the data in Figure 10b,
A plan view showing the two-dimensional development of the results of dither processing using the threshold data shown in Fig. 10c and LOe, respectively, and Fig. 1og is a plan view showing the result of dither processing using the threshold data shown in Fig. FIG. 3 is a plan view showing a two-dimensional development of the pattern processing results. FIG. 11a is a plan view showing a state in which data indicating characteristics of edges are arranged on both sides of the edge area of the data shown in FIG. 1Ob. FIG. 11b and FIG. 11B are plan views showing the results of edge extraction processing and edge enhancement processing, respectively, of the data shown in FIG. 11B. FIG. 11c is a plan view showing the result of binarizing the data in FIG. 11b using a fixed threshold. Figures 1ie and 11f show the data in figure 1id,
10e and 10c are plan views showing the results of dither processing using the thresholds shown in FIG. 10e and FIG. 10c, respectively. FIG. 11g is a plan view showing the result of the logical sum operation of the data in FIG. 11c and the data in FIG. 1ie. FIG. 11i is a plan view showing the result of dithering the data of FIG. 10b using the threshold value of FIG. 11h and the result of the logical sum operation of the data of FIG. 11c. FIG. 12 is a plan view showing several patterns of spatial filters. FIG. 13 is a block diagram illustrating some of the copying mechanism elements connected to microprocessor system 200. FIG. 14 is a time chart showing the relationship between exposure scanning and recording energization of the copying machine shown in FIG. FIG. 15a, FIG. 16a, and FIG. 17a are block diagrams showing gradation processing circuits in other embodiments of the present invention, respectively. FIG. 15b is a block diagram showing a part of the circuit in FIG. 15a in detail, FIG. 16b is a block diagram showing a part of the circuit in FIG. 113a in detail, and FIGS.
7a is a block diagram showing in detail a portion of the circuit of FIG. 7a; FIG. l: Manuscript 2 Nibraten 31 +32
'Fluorescent lamps 41 to 43: Mirror 5: Variable magnification lens unit 6: Dichroic prisms 7r, 7g, 7b: CCD 8: First carriage 9: Second carriage 10: Carriage drive motor 11 Pulley 12: Wires 13bk, 13
y, 13m, 13c: polygon mirror 14bk, 14y, 14
m, 14c: f-θ lens 15bk, 15y, 15
m, 15c, 16bk, 16y, 16m, 16c: Mirror 17bk, 17y, 17m, 17c Rainbow trigonal lens 18bk, 18y, 18m, 18c: Photosensitive drum 19bk, 19y, 19m, 19c:
Charge Scorotron 20bk, 20y, 20
m, 20c: developing devices 21bk, 21y, 21m,
21c: Cleaner 22: Paper feed cassette 23: Paper feed roller 24 Ni registration roller 25: Transfer belt 26
．． 2g, 30: Idle roller 27: Drive roller 29bk, 29y, 29m, 29c: Transfer corotron 31 ni lever 32: Shaft 33: Pin 34: Compression coil spring 3
5: Black copy mode setting solenoid plunger 36:
Fixing device 37: Tray 39: Home position sensor 4o: Carriage guide bar 41bk, 41y, 41111, 41c: Polygon mirror drive motor 42: Toner collection pipe 43bk, 43y, 43+m, 43c: Laser 44b
k, 44y, 44m, 44c: Beam sensor 45: Photosensitive drum drive motor 46: Motor driver 100: Image processing unit 109: Gradation processing circuit 15
0: 8x8 averaging circuit 151: Edge extraction circuit 15
2: Edge emphasis circuit 153: Density pattern processing circuit 154: Edge determination circuit (pattern switching means) 155:
Data correction circuit 156: Rashidum dither processing circuit 200: Microprocessor system 210: Matrix register 230: Arithmetic unit 331.361: Memory (threshold table means) 3
40: Accumulation circuit

Claims (8)

[Claims] (1) Convert input multivalued data to binary data by referring to a threshold table in which different thresholds are set for each pixel position in a gradation processing unit area consisting of multiple pixel positions. In a halftone digital image processing device having a halftone processing means for expressing a halftone by adjusting the number of recorded pixel data and non-recorded pixel data within a unit area of gradation processing; a threshold array pattern; threshold table means having a plurality of types; and determining whether or not edge information is included in the input data for each unit area of gradation processing, and using the threshold table means in accordance with the presence or absence of the edge information. A halftone digital image processing device comprising: pattern switching means for switching a threshold array pattern. (2) The threshold table means has both a random pattern and a systematic pattern as threshold arrangement patterns, and the pattern switching means selects a random pattern when an edge is detected, and otherwise selects a systematic pattern. The halftone digital image processing device according to claim 1, wherein the halftone digital image processing device selects a target pattern. (3) When the pattern switching means detects edge information,
Claim (1): outputting data obtained by combining data obtained by extracting the edge information and converting it into a binary value, and data obtained by converting the input data into a binary value by referring to a threshold table. The halftone digital image processing device described. (4) The pattern switching means includes an edge emphasis filter means, and compares the result of edge emphasis processing of the input data with predetermined upper and lower limit values, and determines the presence or absence of edge information based on the results of the halftone digital image. Processing equipment. (5) The pattern switching means includes an edge emphasis filter means, and when the input data has edge information, the result of performing edge emphasis processing on the input data is compared with the value of the threshold table, and the result is output data; A halftone digital image processing apparatus according to claim (1). (6) The halftone digital image processing apparatus according to claim 1, wherein the pattern switching means includes an edge emphasis filter means and a color correction means arranged before the means. (7) Color correction means includes γ correction processing, masking processing, U
A halftone digital image processing apparatus according to claim 6, which performs at least one of CR processing and black generation processing. (8) The halftone processing means includes a plurality of dither processing systems that differ from each other in at least one of the parameters of the edge enhancement filter, the type of the random array threshold table, and the size of the random array threshold table, and When the edge information is included in the input data, the switching means
Claims (1) and (2) above select the output data of each dither processing system whose gradation is closest to the average gradation of the input data as the final output data. Section (3), Section (4), Section (5), Section (
The halftone digital image processing device according to item 6) or item (7).