JPS6128269B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a horizontal synchronizing signal separation circuit, and in particular to a transmission line in which a reproduced image is obtained by switching each field, for example, time axis correction in a reproduction system of a U-matic VTR such as a 2-head VTR. The present invention relates to a horizontal synchronizing signal separation circuit suitable for use in the present invention.

In a transmission line that normally transmits information signals, a control signal attached to the information signal passing through this transmission line is detected, and a predetermined signal correction process is performed based on the detected signal to obtain accurate desired information. You may get a signal. For example, in the playback system of a 2-head VTR, a horizontal synchronization signal is extracted from the reproduced video signal in order to correct the time axis of the playback signal, and a write signal synchronized with the horizontal synchronization signal of the video signal containing this jitter is used to correct the time axis. The reproduced video signal is written in a memory device of the circuit, and is read out from the memory device using a separate readout signal that does not contain a jitter component.

By the way, in the playback system of a two-head VTR that uses a horizontal synchronization signal as a pilot signal for time axis correction, if the frequency characteristics between fields differ due to head resonance or the playback amplifier, the falling or rising portion of the horizontal synchronization signal for each field may change. This is particularly noticeable when dubbing is repeated. Further, the horizontal synchronization signal is generally phase-modulated for each field when it is synchronized and separated from the video signal. Therefore, if such a horizontal synchronization signal is used as a pilot signal for time base correction, a time base error equal to the amount by which the horizontal synchronization signal is phase modulated will occur, and as a result, the video signal obtained at the output side of the time base correction circuit will be This results in flickering, which significantly degrades the image quality.

In view of this, the present invention detects the slope of a horizontal synchronizing signal included in a video signal, obtains a detection voltage corresponding to this slope, and improves the electrical characteristics in a transmission system based on this detection voltage. The present invention provides a versatile horizontal synchronization signal separation circuit as described above.

An embodiment in which the present invention is applied to, for example, a reproduction system of a two-head VTR will be described in detail with reference to FIGS. 1 to 6.

FIG. 1 shows a circuit configuration of an embodiment of the present invention. In FIG. 1, 1 is an input terminal to which the input information of the transmission path is supplied, in this example a reproduced video signal, and 2 is a video signal from which high frequency components such as a carrier color signal have been removed, such as a luminance signal including a horizontal synchronization signal. This variable LPF 2 is a variable low frequency filter (hereinafter referred to as variable LPF) that passes the high frequency band.This variable LPF 2 has a circuit configuration as shown in FIG. The cutoff frequency changes to vary the waveband. 3 is a pedestal clamp circuit, which is variable
The pedestal level portion of the video signal from which the high frequency component derived from LPF 2 has been removed is clamped. 4
is a window comparator, which includes a plurality of voltage dividing resistors 7 connected between reference power terminals 5 and 6.
From the first and second reference voltages obtained from ~9, respectively, and the slope of the horizontal synchronizing signal inserted into the clamped pedestal level section as described above,
A pulse signal is generated according to this slope. Two pulse signals are obtained corresponding to the falling and rising slopes of the horizontal synchronizing signal, but one of the pulse signals is removed in order to match the falling or rising edge of the horizontal synchronizing signal. , only the remaining pulse signal is used for the detection voltage.

10 is a monostable multivibrator for generating an output in response to, for example, a falling edge of the first pulse signal of each field from the window comparator 4; 11 is a logic circuit that connects the output of the window comparator 4 and the inverted output of the monostable multivibrator 10; A gate circuit for processing, for example an AND gate, 12
is a switch circuit for switching between fields. This switch circuit 12 switches between a plurality of fields, for example, between the A field and the B field, in synchronization with a field switching signal, such as a vertical synchronizing signal, supplied to an input terminal 13. Integrating circuits 14 and 15 are provided corresponding to each field, and integrate the output of the AND gate 11 distributed for each field and convert it into a DC signal. 16 is a difference detection circuit such as an operational amplifier for detecting the level difference between the DC signals supplied from the integrating circuits 14 and 15, amplifying the signal, and sending the output as a detection voltage; 17 is the input terminal 1;
The switch circuit is a switch circuit that opens and closes for each field in synchronization with the vertical synchronization signal from the switch circuit 1.
7 is open when it is the A field, but is closed when it is the B field, and serves to supply the detected voltage from the difference detection circuit 16 to the adder 18. The adder 18 adds the detected voltage fed back from the DC power supply 19 via the fixed voltage switch circuit 17 to make it variable.
Depending on the setting conditions described above, the adder 18 supplies the fixed voltage from the DC power supply 19 to the variable LPF 2 when it is the A field, and adds the fixed voltage and the detected voltage when it is the B field. Supply to variable LPF2. Therefore, the fixed voltage of the DC power supply 19 is set to be at the center of the wave band of the variable LPF 2. Further, a synchronization separation circuit 30 and a time base correction circuit 31 are provided on the output side of the pedestal clamp circuit 3, and the time base correction circuit 31 receives a clock signal whose phase is locked to the horizontal synchronization signal synchronously separated by the synchronization separation circuit 30. to control writing to that memory.

Next, the operation of this embodiment will be explained with reference to the signal waveforms shown in FIG.

The reproduced video signal from input terminal 1 is variable
The high frequency component is removed by LPF 2, and the pedestal level part in pedestal clamp circuit 3 is shown in Figure 2A.
A horizontal synchronizing signal S ₁ that is clamped as shown in FIG. Further, as shown in FIG. 2A, the window comparator 4 is supplied with reference voltages V ₁ and V ₂ that can be varied as necessary, and the window comparator 4 performs horizontal synchronization using these reference voltages V ₁ and V ₂ . Pulse signals _S2 and S'2 as shown in FIG. 2B are generated corresponding to the sliced portion of the slope of the signal _S1 , but in this example, the pulse signal _S2 corresponding to the falling edge of the horizontal synchronizing signal _S1 is generated. Only ₂ shall be used for detection voltage. Pulse signal S ₂ from window comparator 4
is supplied to the monostable multivibrator 10, and an inverted signal _S3 is generated at the falling edge of the pulse signal _S2 at its inverted output terminal as shown in FIG. 2C. This logic state is at least a pulse signal following the pulse signal _S2 from the window comparator 4.
It is retained longer than the time that S′ ₂ occurs, e.g. 4.5
Lasts for more than μs. Therefore _, at the output side of the AND gate ₁₁ , a pulse signal _S4 as shown in FIG. Since the gate remains closed, the pulse signal _S'2 is removed here.

Such operations are performed sequentially for each field, and the results are switched by the switch circuit 12 in synchronization with the vertical synchronizing signal supplied from the input terminal 13.
That is, the pulse signal _S4 derived to the output side of the AND gate 11 is input to the integrator circuit 14 in the case of the A field.
On the other hand, in the case of the B field, it is integrated by the integrating circuit 15 and converted to a DC signal, and the difference between the two is detected by the difference detection circuit 16 and taken out as a detected voltage. In this example, the frequency characteristics of field A are used as a reference, and the frequency characteristics of field B are controlled to match the frequency characteristics of field A. Therefore, the switch circuit 17 is opened when field A is open, and when it is field B, the frequency characteristics of field B are controlled to match the frequency characteristics of field A. It is switched in synchronization with the vertical synchronization signal from the input terminal 13 so as to close the gate. Therefore, if there is a difference in slope between the horizontal synchronizing signal of the A field and the horizontal synchronizing signal of the B field, that is, if the frequency characteristics of the A field and the frequency characteristics of the B field are different, the difference is used as the detection voltage by the adder 18. Added to the fixed voltage from the DC power supply 19 and made variable
The signal is supplied to the LPF 2, and the frequency characteristic of the B field is corrected by the amount of the error so that it matches the frequency characteristic of the A field. As a result, a horizontal synchronizing signal having the same slope between each field is obtained on the output side of the variable LPF 2.

According to this embodiment, since the slope of the horizontal synchronization signal is controlled to be constant between fields, phase modulation of the horizontal synchronization signal between fields is prevented, time axis errors are reduced, and jitter is eliminated. It is possible to obtain stable and clear reproduced images.

FIG. 4 shows a circuit configuration of another embodiment of the present invention. In FIG. 4, parts corresponding to those in FIG. 1 are denoted by the same reference numerals, and detailed explanation thereof will be omitted.

In this embodiment, an LPF is provided for each field, and the configuration is such that the band of one LPF is fixed and the band of the other LPF is variable. That is, as shown in Fig. 4, for example, a fixed LPF 20 with a fixed band is provided for the A field, and a variable LPF 2 similar to Fig. 1 with a variable band is provided for the B field, and these fixed LPF 20 and variable LPF 2 are combined. The switch circuit 21 is configured to switch each field in synchronization with a field switching signal, such as a vertical synchronization signal, from the input terminal 13. The detection voltage obtained at the output side of the difference detection circuit 16 such as an operational amplifier is directly supplied to the variable LPF 2. Note that the band of the fixed LPF 20 is set to be at the center of the variable band of the variable LPF 2. The rest of the circuit configuration is the same as the circuit configuration shown in FIG.

Next, the operation of this embodiment will be explained. The video signal obtained by being played back to the input terminal 1 is sent to the switch circuit 2.
1, the A field is switched to the fixed LPF 20 for derivation, and the B field is switched to the variable LPF 2 for derivation. The video signal containing the horizontal synchronization signal from which the high frequency components have been removed by each LPF is then processed in the same way as in the case of FIG. The frequency characteristic of the B field matches the frequency of the A field, and the band of the variable LPF 2 is varied. As a result, a horizontal synchronizing signal having the same slope between each field is obtained on the output side of the switch circuit 21, that is, on the input side of the pedestal clamp circuit 3, and the time base error between the fields is reduced.

Therefore, in this embodiment, the same effects as in the embodiment shown in FIG. 1 can be obtained.

In each of the above-mentioned embodiments, the detection voltage according to the slope of the horizontal synchronization signal is fed back to the variable LPF to match the frequency characteristics between the fields. A phase shifter 3 provided on the output side of the synchronous separation circuit 30 as shown in
In addition to 2, the horizontal synchronization signal may be phase-shifted to reduce the phase shift difference between fields that occurs in the horizontal synchronization signal during horizontal synchronization separation. Also,
As shown in FIG. 6, the threshold level applied to the synchronization separation circuit 30 may be appropriately controlled by the detection voltage to compensate for the difference in slope of the horizontal synchronization signal waveform.

Furthermore, in each of the above-mentioned embodiments, the present invention is applied to two heads.
Although it has been explained above that the application is applied to the reproduction system of a VTR, the invention is not limited to this. It goes without saying that the present invention can be similarly applied to the case of correction, or to other cases where the slope of a control signal attached to an information signal passing through a plurality of transmission lines is detected and used by switching between the transmission lines as in the above embodiment. Nor.

[Brief explanation of the drawing]

FIG. 1 is a circuit configuration diagram showing an embodiment of the present invention;
Fig. 2 is a signal waveform diagram for explaining the operation of Fig. 1, Fig. 3 is a connection diagram showing a part of the main part of Fig. 1, and Figs. FIG. 3 is a circuit configuration diagram showing another embodiment of the invention. 2 is a variable low frequency generator, 3 is a pedestal clamp circuit, 4 is a window comparator, 10 is a monostable multivibrator, 12, 17, and 21 are switch circuits, 14 and 15 are integration circuits, 16 is a difference detection circuit, and 18 is a The adder 20 is a fixed low frequency amplifier.

Claims (1)

[Claims] 1 A plurality of video signals are time-division multiplexed and used as input signals, and in a horizontal synchronization signal separation circuit that separates horizontal synchronization signals from each of the plurality of video signals, detecting the rising or falling slope of the horizontal synchronization signal. the plurality of horizontal synchronization signals separated from among the plurality of video signals by the correction signal; A horizontal synchronization signal separation circuit characterized by performing signal phase compensation.