JPS6127836B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a recording and reproducing apparatus that utilizes signal processing using the PCM method for analog signals.

Generally, when converting an analog signal into a digital signal using the PCM method and recording it on a recording medium,
Since the signal has a wide band, it is impossible to record it with currently available audio decks, so recording with a video tape recorder (hereinafter abbreviated as VTR) is considered.

When recording on a VTR, it is of course desirable to take care not to damage the form of the television signal, and it is also desirable to take care not to damage the format of the television signal. In other words, a digital signal must be inserted into the PCM data.

In view of the above points, the present invention processes a PCM signal to have the same format as a television signal, thereby making it possible to use the PCM signal for input without making any changes to the VTR. An object of the present invention is to provide a PCM recording and reproducing device which prevents waveform distortion of digital signals by reducing the difference between the lowest level of a digital signal and the highest level of a white reference signal preceding it. It is.

The following types of PCM recording and reproducing apparatuses have been proposed as this type of PCM recording and reproducing apparatus.

Figure 1 shows a schematic diagram of a PCM recording and reproducing device.
FIG. 2 shows a waveform diagram of each part to explain the same operation as above, and FIG. 3 shows a standard television signal diagram.

In the figure, 1 is an input terminal connected to, for example, a microphone, 2 is a low-pass filter, 3 is a sample and hold circuit, 4 is an analog-to-digital converter (hereinafter abbreviated as AD converter), 5 is a memory, and 6 is a The modulation side synchronization signal generation circuit 7 is a video amplifier, and these constitute a modulation side signal processing system.

8 is a VTR.

9 is a signal separation circuit, 10 is a memory, 11 is a digital-to-analog converter (hereinafter abbreviated as DA converter), and 12 is a sample-and-hold circuit (hereinafter referred to as DA converter).
It is abbreviated as SH circuit. ), 13 is a low-pass filter, 14 is a buffer amplifier, 15 is an output terminal, 1
Reference numeral 6 denotes a demodulation side synchronization signal generation circuit, which constitutes a reproduction side signal processing system.

The operation of the above configuration is as follows.

The analog signal S ₀ passes through the input terminal 1 and is band-limited by the low-pass filter 2, and is then passed through the SH circuit 3 in response to the signal S ₁ obtained by dividing the frequency signal generated by the crystal oscillator in the modulation side synchronization signal generation circuit 6. is sampled and output as signal _S2 .

The signal S ₂ is an n-bit parallel digital signal S ₃₁ , S ₃₂ .
... and input to the memory 5 as is or in response to a signal that is a timing pulse that is converted into a serial (serial) signal by a shift register or the like and formed by a modulation-side synchronization signal generation circuit 6. Note that the parallel digital signals S ₃₁ , S ₃₂ ...
The conversion to serial data can be performed in response to a signal formed by the modulation-side synchronization signal generation circuit 6 at a frequency n times that of the signal for the timing of the conversion.

The signal written in the memory 5 is read out in response to the signal _S4 generated by the modulation side synchronization signal generation circuit 6 to obtain the signal _S5 .

Although one channel has been described above as the analog signal S ₀ , other channels can be written in the memory 5 in the same way, and the signals of these channels can be read out alternately.

In the video amplifier 7, this signal _S5 is converted into a vertical synchronizing signal a-b, a horizontal synchronizing signal a-a, an equalization pulse a, and a horizontal synchronizing signal a-a of a composite video signal (television signal) _S6 in accordance with the signal from the modulation-side synchronizing signal generation circuit 6. -c, etc. are provided as digital signals to the video signal parts a to d.

In this way, the signal _S7 , which is given as the signal _S5 to the video signal portion of the television signal, is obtained as the output of the video amplifier 7, and is supplied to the VTR and recorded.

During playback, the playback signal from the VTR, that is, the signal S ₇
is separated into a synchronization signal S ₉ supplied to the demodulation side synchronization signal generation circuit 16 and data S ₈ supplied to the memory in the signal separation circuit.

The demodulation side synchronization signal generation circuit 16 is a signal separation circuit 9
It detects the vertical synchronization period from the synchronization signal from and controls the phase controller (PLL) to form the clock necessary for reproduction. It is formed from synchronization pulses, which control the phase control and form the clock necessary for reproduction.

The data S ₈ is read and written into the memory 10 using a signal from the reproduction side synchronization signal generation circuit 16 .

The data read from the memory 10 is converted from a serial format (serial) to a parallel format (parallel) by a shift register or the like, and is converted into signals S ₁₀ , S ₁₀ . . .
...is obtained.

These signals S ₁₀ , S ₁₀ . Digital and analog conversions are performed at the right timing.

The signal _S11 which is the output of this DA converter 11 is
The width and timing are specified according to the signal _S12 from the demodulation side synchronization signal generation circuit 16 through the SH circuit.
A signal S ₁₃ , which is a PAM wave, is obtained.

The signal S ₁₃ is obtained as an analog signal S ₁₄ through a low-pass filter 13 and is further amplified by a buffer amplifier 15 and output to an output terminal.

The present invention provides a PCM system recording and reproducing device as described above, in which PCM is added to the video signal portion of a television signal.
In other words, the present invention relates to the technical field of inserting digital signals, and provides a method that takes into consideration stable recording and reproducing of a wideband recording and reproducing device such as a VTR.

In the present invention, the digital signal is inserted so that the highest value level of the white reference signal pre-valued therein is set as its highest value level, and the difference between the lowest value level of the digital signal and the highest value level of the white reference signal is reduced. The present invention is characterized in that the waveform distortion of the digital signal is prevented by doing so, and examples thereof will be described below with reference to the drawings.

FIG. 3 is a PCM explaining one embodiment of the present invention.
It shows an enlarged view of the waveform of one horizontal period of a television signal into which a digital signal, which is data, is inserted.

As shown in FIG. 3, the horizontal synchronizing pulse a-a _o
A reference signal b _o and a digital signal _{C o} are inserted into _the video signal portion _between It is in the form of a television signal.

Such a signal according to an embodiment of the present invention is a signal obtained from the modulation side synchronization signal generation circuit 6 and a signal obtained from the memory 5.
It can also be obtained by adjusting the mixing ratio appropriately when mixing the digital signals obtained from the following, for example, as follows.

4 is a waveform diagram of the signals A, B, C obtained from the modulation side synchronization signal generation circuit 6 and the digital signal D obtained from the memory 5, and FIG.
It is a block diagram which shows the principle of the circuit which mixes thru|or D.

In FIG. 5, R ₁ to R ₄ are voltage dividing resistors, and the signal A is an open collector type, and the signal A is divided into voltages through an open collector type driver (hereinafter simply referred to as a driver) O ₁ . To the highest potential point P ₁ , the above signal C is the driver
O ₂ to the next voltage potential point P ₂ of the partial voltage, the above signal B
and D pass through a common OR circuit OR, and their outputs are respectively led to a lower potential point P ₃ through a driver O ₃ . The signal at the highest potential point _P1 passes through the transistor T, and an output is obtained from its emitter side via the resistor _R6 to the output terminal VIDEO/OUT.

The signal obtained at the output terminal VIDEO/OUT is
The mixing ratio of the signals A, B, C, and D can be varied according to the variation of R ₂ , R ₃ , and R ₄ , and by adjusting this appropriately, the digital signal C as shown in FIG. The reference level of _o is made to be the reference level of the reference signal b _o , that is, the white reference level of the television signal. That is, by inserting the digital signal _Co between the highest level of the white reference signal preceding it and a level below it by a certain value (a level higher than the pedestal level), the highest level of the white reference signal and To reduce the difference between the lowest levels of digital signals and prevent waveform distortion of the digital signal that would occur if the difference was large. In addition, the fourth
Signals A, B, and C shown in the figure are generated in the modulation-side synchronization signal generation circuit 6, and can be obtained by applying the technique of generating synchronization signals for television signals.

In this way, a signal in which the video signal portion of the television signal is inserted as a digital signal as shown in FIG. 3 is obtained at the output of the video amplifier 7.

It is clear that this signal is recorded and further reproduced on a VTR in the same way as the signal S ₇ above, and the signal reproduced on this VTR is detected as the reference signal b _o in the signal separation circuit 9. It is also possible to detect the digital signal C _o at a level similar to that of the digital signal level, or even at a level considerably higher than the pedestal level, and supply it to the memory 10. Thereafter, the reproduction side signal processing system operates in the same manner as above. An analog signal is reproduced at the output of the buffer amplifier 14.

By the way, in the present invention, as described above, the relationship between the white reference signal b _o and the digital signal c _o is
The waveform shown in the figure is created by setting the lowest level of the digital signal c _o of the recording signal to the VTR to the same level as the pedestal level of the television signal, as shown in Fig. 8a, and setting the white reference signal b _o as the same level as the pedestal level of the television signal. If the difference between the highest level and the highest level is increased, waveform distortion will occur in the reproduced signal from the VTR due to emphasis, white clipping, etc. In particular, if the beginning of the digital signal _co is at the "0" level, the white reference signal will be distorted. b _o
There is a risk that an undershoot n will occur immediately after this and will be output as a pseudo synchronization signal.

However, according to the present invention, ie, FIG.
As shown in , by reducing the difference between the highest level of the white reference signal b _o and the lowest level of the digital signal c _o , the waveform distortion will be reduced even if the beginning of the digital signal c _o is at the "0" level. As a result, the undershoot n becomes smaller, and the drawbacks of the case shown in FIG. 8a can be avoided.

As another embodiment of the present invention, as shown in FIG. 6, compared to FIG. 4, an example may be given in which a signal d _o is further added to the digital signal c _o , and this can be realized as follows.

As shown in Figure 7, the signal e ₁ obtained by the modulation side synchronization signal generation circuit (the equalization pulse of the standard television signal, the vertical synchronization pulse part is omitted, and the horizontal synchronization pulse part adjacent to the video signal part is shown in Figure 7). ), the modulation-side synchronization signal generation circuit ₆ generates a section with a width equal to or narrower than the section of the video signal portion of the television signal. 1" and "0" for all others, and a generator generates _{a signal e3 which} is an inversion of "0" and "1" of the signal _S5 , and these signals
A DC component is added to e ₃ using a signal e ₂ using an adder to obtain a signal e ₄ . In this way, the signal e ₄ is used and mixed by combining with the signal e ₁ to obtain a television signal having the form shown in FIG.

The present invention is to insert a digital signal obtained by converting an analog signal into PCM as described above with reference to the white reference level of a television signal, in short, to process the digital signal so that it has the same form as a television signal. Therefore, it is possible to provide a PCM recording and reproducing device that can be used for input without making any changes to the VTR.

In addition, in the present invention, a digital signal is inserted between the highest level of the white reference signal which is pre-valued and a level below it by a certain certain value, and the digital signal is inserted between the highest level of the white reference signal and the lowest level of the level signal. Since the head difference is reduced, it is possible to eliminate waveform distortion at the beginning of the digital signal (immediately after the white reference signal).

[Brief explanation of the drawing]

Fig. 1 is a block diagram explaining the PCM recording and reproducing method, Fig. 2 is a waveform diagram of each part explaining the operation of the same, and Fig. 3 is a principle diagram of the main parts to explain the method of the present invention. FIG. 4 is a waveform diagram of each part explaining the operation of the embodiment for obtaining the same as above.
FIG. 5 shows the configuration diagram of the main parts for implementing the above, and FIGS. 6 and 7 are the principle waveform diagrams of the main parts for explaining the method of the present invention, and the embodiment for obtaining the same. FIG. 8 shows waveform diagrams of recording and reproduction signals provided to explain the operation of the present invention. a-a _o , a-a _o+1 : horizontal synchronization pulse, b _o :
Reference signal, c _o : digital signal, _do : reference signal, OR : OR circuit, O ₁ , O ₂ and O ₃ : oven collector type driver, R ₁ , R ₂ , R ₃ , R ₄ : resistance, T: transistor.

Claims (1)

[Claims] 1. A recording signal obtained by converting an analog signal into a digital signal using the PCM method and inserting it between several types of reference signals provided at regular intervals is recorded on a recording medium, and this In a PCM recording and reproducing device that reproduces an analog signal by converting the signal obtained from a recording medium into an analog signal, the digital signal must be set at a level higher than the highest level of the white reference signal preceding it and the pedestal level of the television signal. characterized by being inserted between the levels of
PCM recording and playback method.